Jinghao Shi 079744bec1 fix dot11 port pinout

2017-04-21 13:42:09 -04:00

..

coregen

add coregen files

2017-04-14 16:29:33 -04:00

sim_out

add sim_out dir

2017-04-03 15:25:48 -04:00

usrp2

verilog init

2017-04-03 12:52:03 -04:00

Xilinx/12.2/ISE_DS/ISE/verilog/src

verilog init

2017-04-03 12:52:03 -04:00

atan_lut.coe

verilog init

2017-04-03 12:52:03 -04:00

atan_lut.mif

verilog init

2017-04-03 12:52:03 -04:00

bits_to_bytes.v

verilog init

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calc_mean.v

verilog init

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common_defs.v

verilog init

2017-04-03 12:52:03 -04:00

common_params.v

readme

2017-04-03 14:31:25 -04:00

complex_mult.v

verilog init

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complex_to_mag_sq.v

verilog init

2017-04-03 12:52:03 -04:00

complex_to_mag.v

use delayT

2017-04-07 11:36:21 -04:00

crc32.v

verilog init

2017-04-03 12:52:03 -04:00

deinter_lut.coe

verilog init

2017-04-03 12:52:03 -04:00

deinter_lut.mif

verilog init

2017-04-03 12:52:03 -04:00

deinterleave.v

verilog init

2017-04-03 12:52:03 -04:00

delay_sample.v

verilog init

2017-04-03 12:52:03 -04:00

delayT.v

verilog init

2017-04-03 12:52:03 -04:00

demodulate.v

verilog init

2017-04-03 12:52:03 -04:00

descramble.v

remve unused variable in descramble.v

2017-04-21 13:41:28 -04:00

divider.v

verilog init

2017-04-03 12:52:03 -04:00

dot11_modules.list

verilog init

2017-04-03 12:52:03 -04:00

dot11_tb.v

fix dot11 port pinout

2017-04-21 13:42:09 -04:00

dot11.v

fix port pinout

2017-04-21 13:41:49 -04:00

equalizer.v

fix polarity pattern

2017-04-14 11:00:01 -04:00

ht_sig_crc.v

verilog init

2017-04-03 12:52:03 -04:00

Makefile

makefile

2017-04-03 14:05:07 -04:00

moving_avg.v

verilog init

2017-04-03 12:52:03 -04:00

ofdm_decoder.v

verilog init

2017-04-03 12:52:03 -04:00

phase.v

fix comment

2017-04-14 11:00:12 -04:00

power_trigger.v

working

2017-04-03 15:48:25 -04:00

rand_gen_tb.v

verilog init

2017-04-03 12:52:03 -04:00

rand_gen.v

verilog init

2017-04-03 12:52:03 -04:00

rate_to_idx.v

verilog init

2017-04-03 12:52:03 -04:00

rot_lut.coe

verilog init

2017-04-03 12:52:03 -04:00

rot_lut.mif

verilog init

2017-04-03 12:52:03 -04:00

rotate.v

rotate

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stage_mult.v

verilog init

2017-04-03 12:52:03 -04:00

sync_long.v

variable name

2017-04-14 11:00:46 -04:00

sync_short.v

refactor name

2017-04-07 11:36:41 -04:00

viterbi.v

verilog init

2017-04-03 12:52:03 -04:00