Commit Graph

141 Commits

Author SHA1 Message Date
Jinghao Shi
126c1037f5 readme 2017-04-25 15:24:48 -04:00
Jinghao Shi
cceefb6c77 usrp 2017-04-25 15:19:32 -04:00
Jinghao Shi
39b6115360 docs 2017-04-21 13:42:20 -04:00
Jinghao Shi
079744bec1 fix dot11 port pinout 2017-04-21 13:42:09 -04:00
Jinghao Shi
b7361b2feb fix port pinout 2017-04-21 13:41:49 -04:00
Jinghao Shi
c0ad55abb6 remve unused variable in descramble.v 2017-04-21 13:41:28 -04:00
Jinghao Shi
436aa53ea1 rewrite test.py 2017-04-21 13:41:03 -04:00
Jinghao Shi
2315d0fc74 fix window size 2017-04-21 13:40:46 -04:00
Jinghao Shi
cc5effe283 ht-sig 2017-04-17 15:55:36 -04:00
Jinghao Shi
25c5d67904 descrabmle 2017-04-17 12:53:44 -04:00
Jinghao Shi
556794ae2e add coregen files 2017-04-14 16:29:33 -04:00
Jinghao Shi
a827623ab5 doc 2017-04-14 16:29:19 -04:00
Jinghao Shi
e5d4dc7cfc enlarge num_sample 2017-04-14 11:01:18 -04:00
Jinghao Shi
bcee4f66a1 fix packet detection 2017-04-14 11:01:05 -04:00
Jinghao Shi
701cbb70c9 variable name 2017-04-14 11:00:46 -04:00
Jinghao Shi
0b0723899a rotate 2017-04-14 11:00:33 -04:00
Jinghao Shi
47577f7099 fix comment 2017-04-14 11:00:12 -04:00
Jinghao Shi
191b197d5e fix polarity pattern 2017-04-14 11:00:01 -04:00
Jinghao Shi
4f313f3ef9 doc 2017-04-14 10:59:40 -04:00
Jinghao Shi
4e3c57c5f3 working on eq 2017-04-12 15:49:17 -04:00
Jinghao Shi
297162af13 working 2017-04-07 16:51:06 -04:00
Jinghao Shi
c4c81b2766 fix lts index 2017-04-07 16:50:16 -04:00
Jinghao Shi
20279b42a4 fix long preamble sample beginning index 2017-04-07 16:49:41 -04:00
Jinghao Shi
652c8c1bb7 working on sync_long 2017-04-07 16:48:34 -04:00
Jinghao Shi
df46bc5309 phase lut 2017-04-07 11:37:11 -04:00
Jinghao Shi
779b3651a4 remove unused verilog files 2017-04-07 11:36:51 -04:00
Jinghao Shi
8375779a03 refactor name 2017-04-07 11:36:41 -04:00
Jinghao Shi
4dd053ebf8 use delayT 2017-04-07 11:36:21 -04:00
Jinghao Shi
28c57fc17f doc 2017-04-05 16:06:23 -04:00
Jinghao Shi
63dd5a42f2 working 2017-04-03 15:48:37 -04:00
Jinghao Shi
cf42e1b7ae working 2017-04-03 15:48:25 -04:00
Jinghao Shi
506472dec3 add sim_out dir 2017-04-03 15:25:48 -04:00
Jinghao Shi
23e1c270e0 requirements.txt 2017-04-03 14:42:56 -04:00
Jinghao Shi
8b4df2fcfe doc init 2017-04-03 14:42:37 -04:00
Jinghao Shi
1ad9302fc3 readme 2017-04-03 14:31:25 -04:00
Jinghao Shi
d3ff9e7ce8 makefile 2017-04-03 14:05:07 -04:00
Jinghao Shi
bf4701fb39 makefile 2017-04-03 12:59:32 -04:00
Jinghao Shi
cf69020661 init 2017-04-03 12:52:37 -04:00
Jinghao Shi
379f20e652 testing inputs init 2017-04-03 12:52:31 -04:00
Jinghao Shi
20a33eb560 scripts init 2017-04-03 12:52:21 -04:00
Jinghao Shi
9edf1899bd verilog init 2017-04-03 12:52:03 -04:00