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Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
2 Commits 1 Branch 0 Tags 28 MiB
Verilog 54.6%
VHDL 44.3%
Python 0.6%
Tcl 0.5%
20a33eb560
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Jinghao Shi 20a33eb560 scripts init
2017-04-03 12:52:21 -04:00
scripts scripts init 2017-04-03 12:52:21 -04:00
verilog verilog init 2017-04-03 12:52:03 -04:00