Jinghao Shi 20a33eb560 scripts init
2017-04-03 12:52:21 -04:00
2017-04-03 12:52:21 -04:00
2017-04-03 12:52:03 -04:00
Description
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
28 MiB
Languages
Verilog 54.6%
VHDL 44.3%
Python 0.6%
Tcl 0.5%