Jinghao Shi d3ff9e7ce8 makefile

2017-04-03 14:05:07 -04:00

scripts

scripts init

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testing_inputs

testing inputs init

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verilog

makefile

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.gitignore

init

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Description

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

802-11ofdmverilog

28 MiB

Languages

Verilog 54.6%

VHDL 44.3%

Python 0.6%

Tcl 0.5%