Xianjun Jiao
0b4b8cc75d
Add all Europe 5GHz channel support into driver
2022-03-28 13:58:05 +02:00
Xianjun Jiao
6a9949ee81
Replace some constants of number of NIC by MAX_NUM_VIF
2022-03-28 13:56:19 +02:00
Xianjun Jiao
61a639784b
Add sysfs file based driver/FPGA access interface
2022-03-28 12:46:49 +02:00
Xianjun Jiao
7d0af6df9e
Move sdrctl testmode cmd out to sdrctl_intf.c
2022-03-28 12:46:18 +02:00
Xianjun Jiao
8dc97f7f08
Avoid the git_rev.h issue:
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When user download the repo instead of clone it.
2022-03-26 20:47:02 +01:00
Xianjun Jiao
ce40e055d2
Add modified ad9361_conv.c of our own:
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Sometimes the unstable hardware can not pass the 61.44Msps self-test/calibration. Override it to 40Msps
2022-03-26 20:34:55 +01:00
mmehari
9cd584f8de
Missing aggregation rules
2022-01-06 15:12:03 +01:00
mmehari
385339ab4b
tx_interrupt if/else optimization
2022-01-06 15:11:05 +01:00
mmehari
0c0d5d827e
use FPGA fifo count registers instead of software queue_cnt
2022-01-06 15:07:50 +01:00
mmehari
c098112487
bug fixes:
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1) update start_idx and blk_ack_ssn variables,
2) revert printing switch
3) update use_short_gi type (bool -> u8),
4) advance skb->tail by num_byte_pad for non aggregation flow
2022-01-06 14:53:39 +01:00
mmehari
2d12c07d4d
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type
2022-01-06 14:43:32 +01:00
mmehari
f738aefa50
A-MPDU tx aggregation support
2022-01-06 14:42:01 +01:00
mmehari
261bb9eef7
A-MPDU rx aggregation support
2022-01-06 14:13:24 +01:00
Jiao Xianjun
abdb610f56
Scripts are adapted for SW HW decouple
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To avoid openwifi-hw github submodule in openwifi. More flexible now.
2021-10-20 22:50:30 +02:00
Jiao Xianjun
72c90e5e32
Merge pull request #104 from open-sdr/fix_large_ping_delay_igent
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Fix the issue of iGent env related big ping delay:
2021-10-13 09:32:21 +02:00
Xianjun Jiao
b60e485eb5
Fix the possible wrong last_auto_fpga_lbt_th saving:
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1. Remove the last_auto_fpga_lbt_th saving from sdrctl set reg command. Otherwise, repeated sdrctl set reg will save wrong value into last_auto_fpga_lbt_th
2. The last_auto_fpga_lbt_th is only set in ad9361_rf_set_channel, which is called at least once by Linux after NIC is up
2021-10-04 09:59:43 +02:00
Xianjun Jiao
109b1cfd3a
Fix the issue of iGent env related big ping delay:
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1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard
2. The issue does not happen when zcu102 is client and zedboard is AP
3. The issue (most likely) does not happen in places other than iGent (like Pablo home)
4. Sometimes it does happen at my home when I test zcu102 as AP together with COTS WiFi
5. Indeed seems like the environment related. Guess some quick small packets in the environment quickly flush/round-up/mess-up the rx dma cyclic buffer, and the rx interrupt internal static variable target_buf_idx_old loses track of the background automatic rx dma cyclic buffer
6. The fix is for all board types (zcu102, zedboard, 7035, etc)
7. The driver compiling make_all.sh script generates USE_NEW_RX_INTERRUPT macro to pre_def.h to enable the new code (while keeping the old code). You can use the script as before.
8. The logic of the fix is that exhaustive search all the rx dma cyclic buffer in rx interrupt to get packet to Linux in the first place.
2021-09-29 16:52:45 +02:00
Xianjun Jiao
8598d2949d
Use drv_xpu register 0 for LBT threshold setting. 0 will enable FPGA threshold auto setting by ad9361_rf_set_channel() in sdr.c. Other value will set static threshold (that value) to FPGA
2021-09-28 21:52:31 +02:00
Xianjun Jiao
d14d06e508
CSI fuzzer feature -- document to be finished
2021-05-13 17:45:39 +02:00
Xianjun Jiao
7cf9ba6e31
Add dmesg printing option for broadcasting packet
2021-05-10 14:04:34 +02:00
Xianjun Jiao
c24e0a046d
sdr.c: change the legacy tx_itrpt1 to tx_itrpt
2021-05-05 16:53:15 +02:00
Xianjun Jiao
c687b19dde
minor update on xilinx dma driver related stuffs
2021-05-05 16:46:28 +02:00
Xianjun Jiao
56fcab2044
udpate ad9361 driver related stuffs:
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we do not maintain our own (modified) ad9361 driver anymore! The original ad9361 driver in the Linux kernel tree can be used with some extra EXPORT_SYMBOL.
2021-05-05 16:44:39 +02:00
Xianjun Jiao
fc47ee1d62
fix the bug when retry_limit_raw==0 in sdr.c (0 is the abnormal number encountered in the monitor mode. normally it should >= 1). the bug causes 15 times transmissions for a packet if no ack is received
2021-04-05 21:53:29 +02:00
Xianjun Jiao
913a9e947c
add ack disable register in xpu in case ack needs to be disabled in monitor mode
2021-04-05 21:51:47 +02:00
Xianjun Jiao
aed16d0502
add missing soft decoding api in hw_def.h
2021-04-05 21:50:40 +02:00
Xianjun Jiao
bb0a2c5897
in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).
2021-04-05 21:49:59 +02:00
Xianjun Jiao
1196ed1fef
remove our customized xilinx_dma.c. the original xilinx_dma.c in kernel can be used now
2021-04-05 21:45:27 +02:00
Xianjun Jiao
95d3c7c5f3
remove all the compiling warnings when build 32bit driver
2021-04-05 21:42:46 +02:00
Xianjun Jiao
e1c2ba0915
turn on soft decoding by default in openofdm_rx.c driver
2021-04-05 21:41:31 +02:00
Xianjun Jiao
027d42ec5b
Fix the state unsync issue between rx interrupt and mac80211. When the issue happens, only a new packet incoming could trigger an old rx packet going to mac80211 rx. And this new fix also could work with the original xilinx dma driver. Our slightly modified xilinx dma driver is not needed anymore.
2021-03-22 23:59:41 +01:00
luz paz
46c420ae77
Follow-up typo
2021-02-04 20:42:04 +01:00
luz paz
b1dd94e387
Fix various typos
...
Found via codespell v2.1.dev0
`codespell -q 3 -L ans,filp,fils,hsi`
2021-02-04 20:41:51 +01:00
Jiao Xianjun
55c2866f7c
Merge pull request #54 from lnceballosz/master
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NGI0 - Updating licensing aspects according REUSE
2021-02-03 16:14:49 +01:00
Jiao Xianjun
9e7be83fb0
Update xpu.c
2021-02-03 15:45:09 +01:00
Jiao Xianjun
20f54826cd
Update xilinx_dma.c
2021-02-03 15:44:30 +01:00
Jiao Xianjun
1ed5453a9a
Update make_xilinx_dma.sh
2021-02-03 15:43:59 +01:00
Jiao Xianjun
ad98df511b
Update README.md
2021-02-03 15:43:34 +01:00
Jiao Xianjun
c4306a8baf
Update tx_intf.c
2021-02-03 15:42:49 +01:00
Jiao Xianjun
541ccd3ce3
Update side_ch.h
2021-02-03 15:42:17 +01:00
Jiao Xianjun
ebf4978ece
Update side_ch.c
2021-02-03 15:41:35 +01:00
Jiao Xianjun
a415fa7ffb
Update make_driver.sh
2021-02-03 15:41:02 +01:00
Jiao Xianjun
d8d76f8862
Update sdr.h
2021-02-03 15:40:16 +01:00
Jiao Xianjun
32bfd1abde
Update sdr.c
2021-02-03 15:39:58 +01:00
Jiao Xianjun
8598124eec
Update rx_intf.c
2021-02-03 15:39:36 +01:00
Jiao Xianjun
5355b2b8ea
Update openofdm_tx.c
2021-02-03 15:38:47 +01:00
Jiao Xianjun
a3cbb385b8
Update openofdm_rx.c
2021-02-03 15:38:20 +01:00
Jiao Xianjun
9e46321135
Update make_all.sh
2021-02-03 15:37:12 +01:00
Jiao Xianjun
d5f8d0d664
Update hw_def.h
2021-02-03 15:36:30 +01:00
Jiao Xianjun
f0cca53ce0
Update ad9361_private.h
2021-02-03 15:35:25 +01:00
Jiao Xianjun
eede959f93
Update ad9361.h
2021-02-03 15:34:39 +01:00
Jiao Xianjun
56c954897d
Update ad9361.c
2021-02-03 15:34:08 +01:00
weiliu
2238b42bb8
improve csma state machine, force ch_idle high after decode, log cw and num_slot_random in the last attempt
2021-01-28 14:15:29 +01:00
Lina Ceballos
a6085186d9
adding license and copyright headers
2021-01-20 13:30:12 +01:00
Jiao Xianjun
09316927a9
change the rssi_half_db_offset back to original
...
to get the correct rssi report.
2021-01-19 16:49:27 +01:00
mmehari
6e3730c0c1
Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information
2020-12-29 21:33:36 +01:00
weiliu
5680efab70
enable dynamic cw
2020-12-28 16:03:51 +01:00
Xianjun Jiao
aa239344c1
use a better cca rssi threshold in sdr.c
2020-12-17 16:48:56 +01:00
Xianjun Jiao
5deb8d18f6
sync internal
2020-12-14 13:32:15 +01:00
mmehari
b6d7171315
sdr driver update for 80211n
2020-11-05 18:22:24 +01:00
Xianjun Jiao
f71252c537
iq capture feature
2020-10-19 10:13:51 +02:00
Xianjun Jiao
22dd0cc486
the side channel (timestamp, frequency offset, CSI, equalizer) feature
2020-10-08 15:07:57 +02:00
Xianjun Jiao
0a92505df2
add recent update:
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1. add git revision software register 7 to DRV_XPU module (not FPGA XPU module)
2. fix the print of hdr->seq_ctrl in sdr.c
3. add ht_flag display to sdr.c
4. remove the sysid from devicetree because new we have our own git revision read back solution in FPGA (XPU register 63) and driver (the sotware register 7 of drv_xpu)
5. add sudo to update_sdcard.sh to make the image generation without SD card in the test-bed easier
2020-09-04 10:57:04 +02:00
Xianjun Jiao
838a9007cf
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
2020-06-12 10:50:34 +02:00
Jiao Xianjun
b5ead9efdd
sync master ( #21 )
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* fix the branch name, since we use master in public repositry
* track correct git repository
* track correct openofdm_rx
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
* Update README.md
2020-06-11 15:50:12 +02:00
Xianjun Jiao
febc5adf73
prepare upgrade
2020-04-27 09:37:04 +02:00
Xianjun Jiao
75042a3073
fix the tsf warning in sdr.c and sdrctl
2020-03-06 14:05:47 +01:00
Xianjun Jiao
e63d1ec300
Jetmir: add tsf set command to sdrctl
2020-03-05 08:50:41 +01:00
Xianjun Jiao
b73660ad79
prepare for release
2020-03-04 19:39:12 +01:00
Xianjun Jiao
2a1e074623
fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz
2020-01-07 14:17:08 +01:00
Xianjun Jiao
2054f92c88
Fix the bug for monitor mode in driver sdr.c openwifi_configure_filter() function. Seems like monitor mode will create and use a new virtual interface, so priv-vif[0] is not valid anymore when monitor mode start and call openwifi_configure_filter()
2020-01-03 18:53:21 +01:00
Xianjun Jiao
2ee6717882
initial commit
2019-12-10 14:03:47 +01:00
