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in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).

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This commit is contained in:
Xianjun Jiao 2021-04-05 21:49:59 +02:00
parent 1196ed1fef
commit bb0a2c5897
3 changed files with 33 additions and 29 deletions
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4
driver/hw_def.h
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@ -253,6 +253,7 @@ const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
@ -348,6 +349,9 @@ struct xpu_driver_api {
void (*XPU_REG_DIFS_ADVANCE_write)(u32 value);
u32 (*XPU_REG_DIFS_ADVANCE_read)(void);
void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value);
u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void);
u32 (*XPU_REG_TRX_STATUS_read)(void);
u32 (*XPU_REG_TX_RESULT_read)(void);

33
driver/sdr.c
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@ -126,7 +126,7 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
{
struct openwifi_priv *priv = dev->priv;
u32 actual_rx_lo = conf->chandef.chan->center_freq - priv->rx_freq_offset_to_lo_MHz + priv->drv_rx_reg_val[DRV_RX_REG_IDX_EXTRA_FO];
u32 actual_tx_lo, reg_val;
u32 actual_tx_lo;
bool change_flag = (actual_rx_lo != priv->actual_rx_lo);
if (change_flag) {
@ -152,8 +152,7 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
}
// xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62)<<1); // -62dBm
reg_val=xpu_api->XPU_REG_LBT_TH_read();
xpu_api->XPU_REG_LBT_TH_write( (reg_val & 0xFFFF0000) | ((priv->rssi_correction-62-16)<<1)); // wei's magic value is 135, here is 134 @ ch 44
xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44
if (actual_rx_lo < 2500) {
//priv->slot_time = 20; //20 is default slot time in ERP(OFDM)/11g 2.4G; short one is 9.
@ -1013,9 +1012,7 @@ static int openwifi_start(struct ieee80211_hw *dev)
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
// rssi_half_db_th = 87<<1; // -62dBm // will setup in runtime in _rf_set_channel
// xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
reg=xpu_api->XPU_REG_LBT_TH_read();
xpu_api->XPU_REG_LBT_TH_write((reg & 0xFF00FFFF) | (75 << 16) ); // bit 23:16 of LBT TH reg is set to control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
// xpu_api->XPU_REG_CSMA_CFG_write(3); // cw_min -- already set in xpu.c
xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
@ -1417,29 +1414,22 @@ u32 log2val(u32 val){
static int openwifi_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
const struct ieee80211_tx_queue_params *params)
{
u32 reg19_val, reg8_val, cw_min_exp, cw_max_exp;
u32 reg_val, cw_min_exp, cw_max_exp;
printk("%s openwifi_conf_tx: WARNING [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\n",
printk("%s openwifi_conf_tx: [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\n",
sdr_compatible_str,queue,params->aifs,params->cw_min,params->cw_max,params->txop);
reg19_val=xpu_api->XPU_REG_CSMA_CFG_read();
reg8_val=xpu_api->XPU_REG_LBT_TH_read();
reg_val=xpu_api->XPU_REG_CSMA_CFG_read();
cw_min_exp = (log2val(params->cw_min + 1) & 0x0F);
cw_max_exp = (log2val(params->cw_max + 1) & 0x0F);
switch(queue){
case 0: reg19_val = (reg19_val & 0xFFFFFF00) | cw_min_exp | (cw_max_exp << 4); break ;
case 1: reg19_val = (reg19_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8); break ;
case 2: reg19_val = (reg19_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16); break ;
case 3: reg8_val = (reg8_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24); break ;
case 0: reg_val = ( (reg_val & 0xFFFFFF00) | ((cw_min_exp | (cw_max_exp << 4)) << 0) ); break;
case 1: reg_val = ( (reg_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8) ); break;
case 2: reg_val = ( (reg_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16) ); break;
case 3: reg_val = ( (reg_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24) ); break;
default: printk("%s openwifi_conf_tx: WARNING queue %d does not exist",sdr_compatible_str, queue); return(0);
}
reg19_val = reg19_val | 0x10000000 ; // enable dynamic contention window.
xpu_api->XPU_REG_LBT_TH_write(reg8_val);
xpu_api->XPU_REG_CSMA_CFG_write(reg19_val);
//printk("reg19 val target val %08x, reg8 target val %08x", reg19_val, reg8_val);
//reg19_val=xpu_api->XPU_REG_CSMA_CFG_read();
//reg8_val=xpu_api->XPU_REG_LBT_TH_read();
//printk("reg19 val read back %08x, reg8 read back %08x", reg19_val, reg8_val);
xpu_api->XPU_REG_CSMA_CFG_write(reg_val);
return(0);
}
@ -1677,7 +1667,6 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]);
printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp);
tmp = (tmp | (xpu_api->XPU_REG_LBT_TH_read() & 0xFFFF0000));
xpu_api->XPU_REG_LBT_TH_write(tmp);
return 0;
case OPENWIFI_CMD_GET_RSSI_TH:

25
driver/xpu/xpu.c
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@ -142,6 +142,14 @@ static inline u32 XPU_REG_DIFS_ADVANCE_read(void){
return reg_read(XPU_REG_DIFS_ADVANCE_ADDR);
}
static inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) {
reg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data);
}
static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){
return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);
}
static inline u32 XPU_REG_TRX_STATUS_read(void){
return reg_read(XPU_REG_TRX_STATUS_ADDR);
}
@ -253,7 +261,6 @@ static inline u32 XPU_REG_SLICE_COUNT_END_read(void){
return reg_read(XPU_REG_SLICE_COUNT_END_ADDR);
}
static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
}
@ -286,7 +293,7 @@ EXPORT_SYMBOL(xpu_api);
static inline u32 hw_init(enum xpu_mode mode){
int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
u32 filter_flag = 0, reg_val;
u32 filter_flag = 0;
printk("%s hw_init mode %d\n", xpu_compatible_str, mode);
@ -339,7 +346,7 @@ static inline u32 hw_init(enum xpu_mode mode){
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"!
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz
//xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
//xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
// xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47);
xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed
@ -397,14 +404,15 @@ static inline u32 hw_init(enum xpu_mode mode){
//rssi_half_db_th = 70<<1; // with splitter
rssi_half_db_th = 87<<1; // -62dBm
reg_val=xpu_api->XPU_REG_LBT_TH_read();
xpu_api->XPU_REG_LBT_TH_write((reg_val & 0xFFFF0000) | rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
xpu_api->XPU_REG_CSMA_DEBUG_write(0);
xpu_api->XPU_REG_CSMA_CFG_write(268435459); // 0x10000003, min CSMA cw exp = 3, set bit 28 high for dynamic CW
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
// xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
@ -475,6 +483,9 @@ static int dev_probe(struct platform_device *pdev)
xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write;
xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read;
xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;
xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;
xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read;
xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read;