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add ack disable register in xpu in case ack needs to be disabled in monitor mode

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This commit is contained in:
Xianjun Jiao 2021-04-05 21:51:47 +02:00
parent aed16d0502
commit 913a9e947c
2 changed files with 26 additions and 19 deletions
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34
driver/hw_def.h
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@ -249,22 +249,22 @@ struct openofdm_tx_driver_api {
const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4)
#define XPU_REG_SLICE_COUNT_START_ADDR (21*4)
@ -397,7 +397,9 @@ struct xpu_driver_api {
u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value);
void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value);
u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void);
void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
};

11
driver/xpu/xpu.c
View File

@ -265,8 +265,11 @@ static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
}
static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value);
static inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value);
}
static inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){
return reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR);
}
static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){
@ -522,7 +525,9 @@ static int dev_probe(struct platform_device *pdev)
xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read;
xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;
xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read;
xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write;