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Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information

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This commit is contained in:
mmehari 2020-12-29 21:33:36 +01:00
parent 5680efab70
commit 6e3730c0c1
4 changed files with 33 additions and 9 deletions
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7
driver/hw_def.h
View File

@ -2,6 +2,11 @@
const char *sdr_compatible_str = "sdr,sdr";
enum openwifi_fpga_type {
SMALL_FPGA = 0,
LARGE_FPGA = 1,
};
enum openwifi_band {
BAND_900M = 0,
BAND_2_4GHZ,
@ -54,7 +59,7 @@ const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
struct tx_intf_driver_api {
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);

19
driver/sdr.c
View File

@ -978,7 +978,7 @@ static int openwifi_start(struct ieee80211_hw *dev)
priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
xpu_api->hw_init(priv->xpu_cfg);
@ -1836,7 +1836,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
struct ieee80211_hw *dev;
struct openwifi_priv *priv;
int err=1, rand_val;
const char *chip_name;
const char *chip_name, *fpga_model;
u32 reg;//, reg1;
struct device_node *np = pdev->dev.of_node;
@ -1871,6 +1871,19 @@ static int openwifi_dev_probe(struct platform_device *pdev)
priv = dev->priv;
priv->pdev = pdev;
err = of_property_read_string(of_find_node_by_path("/"), "model", &fpga_model);
if(err < 0) {
printk("%s openwifi_dev_probe: WARNING unknown openwifi FPGA model %d\n",sdr_compatible_str, err);
priv->fpga_type = SMALL_FPGA;
} else {
// LARGE FPGAs (i.e. ZCU102, Z7035, ZC706)
if(strstr(fpga_model, "ZCU102") != NULL || strstr(fpga_model, "Z7035") != NULL || strstr(fpga_model, "ZC706") != NULL)
priv->fpga_type = LARGE_FPGA;
// SMALL FPGA: (i.e. ZED, ZC702, Z7020)
else if(strstr(fpga_model, "ZED") != NULL || strstr(fpga_model, "ZC702") != NULL || strstr(fpga_model, "Z7020") != NULL)
priv->fpga_type = SMALL_FPGA;
}
// //-------------find ad9361-phy driver for lo/channel control---------------
priv->actual_rx_lo = 0;
tmp_dev = bus_find_device( &spi_bus_type, NULL, "ad9361-phy", custom_match_spi_dev );
@ -2024,7 +2037,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
printk("%s openwifi_dev_probe: ad9361_update_rf_bandwidth %dHz err %d\n",sdr_compatible_str, priv->rf_bw,err);
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
printk("%s openwifi_dev_probe: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\n",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);

1
driver/sdr.h
View File

@ -304,6 +304,7 @@ struct openwifi_priv {
struct ieee80211_vif *vif[MAX_NUM_VIF];
const struct openwifi_rf_ops *rf;
enum openwifi_fpga_type fpga_type;
struct cf_axi_dds_state *dds_st; //axi_ad9361 hdl ref design module, dac channel
struct axiadc_state *adc_st; //axi_ad9361 hdl ref design module, adc channel

15
driver/tx_intf/tx_intf.c
View File

@ -194,7 +194,7 @@ static struct tx_intf_driver_api tx_intf_driver_api_inst;
static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
EXPORT_SYMBOL(tx_intf_api);
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){
int err=0, i;
u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0;
@ -208,7 +208,12 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
for (i=0;i<8;i++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
switch(mode)
{
case TX_INTF_AXIS_LOOP_BACK:
@ -378,9 +383,9 @@ static int dev_probe(struct platform_device *pdev)
printk("%s dev_probe succeed!\n", tx_intf_compatible_str);
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8);
//err = hw_init(TX_INTF_BYPASS, 8, 8);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA);
//err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma
return err;
}