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https://github.com/open-sdr/openwifi.git
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enable dynamic cw
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parent
a2548b82c9
commit
5680efab70
11
driver/sdr.c
11
driver/sdr.c
@ -442,7 +442,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
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struct openwifi_ring *ring;
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struct sk_buff *skb;
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struct ieee80211_tx_info *info;
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u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, loop_count=0;//, i;
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u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, cw, loop_count=0;//, i;
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u8 tx_result_report;
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// u16 prio_rd_idx_store[64]={0};
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@ -450,8 +450,9 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
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while(1) { // loop all packets that have been sent by FPGA
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reg_val = tx_intf_api->TX_INTF_REG_PKT_INFO_read();
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if (reg_val!=0x7FFFF) {
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prio = (reg_val>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
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if (reg_val!=0x7FFFFF) {
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prio = ((0x7FFFF & reg_val)>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
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cw = (reg_val>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
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ring = &(priv->tx_ring[prio]);
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ring->bd_rd_idx = ((reg_val>>5)&MAX_PHY_TX_SN);
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skb = ring->bds[ring->bd_rd_idx].skb_linked;
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@ -506,6 +507,8 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
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if ( (tx_result_report&0x10) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&1) )
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printk("%s openwifi_tx_interrupt: WARNING tx_result %02x prio%d wr%d rd%d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx);
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if ( ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&2) )
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printk("%s openwifi_tx_interrupt: tx_result %02x prio%d wr%d rd%d cw %d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx, cw);
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ieee80211_tx_status_irqsafe(dev, skb);
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@ -981,7 +984,7 @@ static int openwifi_start(struct ieee80211_hw *dev)
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xpu_api->hw_init(priv->xpu_cfg);
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agc_gain_delay = 50; //samples
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rssi_half_db_offset = 150;
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rssi_half_db_offset = 134; // to be consistent
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xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );
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xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );
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@ -400,7 +400,7 @@ static inline u32 hw_init(enum xpu_mode mode){
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//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
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xpu_api->XPU_REG_CSMA_DEBUG_write(0);
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xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
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xpu_api->XPU_REG_CSMA_CFG_write(268435459); // 0x10000003, min CSMA cw exp = 3, set bit 28 high for dynamic CW
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// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
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xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
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@ -1 +1 @@
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Subproject commit 1106691bafd82c877366e35d0a2458dbdc1bac91
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Subproject commit 5871295ebbbc6d1373c2b3ddee567d1c73c4156d
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