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tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type

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This commit is contained in:
mmehari 2022-01-06 14:43:32 +01:00
parent f738aefa50
commit 2d12c07d4d
2 changed files with 41 additions and 11 deletions
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2
driver/hw_def.h
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@ -66,7 +66,7 @@ const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
struct tx_intf_driver_api {
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);

50
driver/tx_intf/tx_intf.c
View File

@ -112,8 +112,20 @@ static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){
return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO_read(void){
return reg_read(TX_INTF_REG_PKT_INFO_ADDR);
static inline u32 TX_INTF_REG_PKT_INFO1_read(void){
return reg_read(TX_INTF_REG_PKT_INFO1_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO2_read(void){
return reg_read(TX_INTF_REG_PKT_INFO2_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO3_read(void){
return reg_read(TX_INTF_REG_PKT_INFO3_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO4_read(void){
return reg_read(TX_INTF_REG_PKT_INFO4_ADDR);
}
static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){
@ -198,8 +210,20 @@ static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){
reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value);
}
static inline void TX_INTF_REG_PKT_INFO_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO_ADDR,value);
static inline void TX_INTF_REG_PKT_INFO1_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO1_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO2_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO2_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO3_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO3_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO4_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO4_ADDR,value);
}
static const struct of_device_id dev_of_ids[] = {
@ -362,7 +386,10 @@ static int dev_probe(struct platform_device *pdev)
tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;
tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_read=TX_INTF_REG_PHY_HDR_CONFIG_read;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read;
tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read;
tx_intf_api->TX_INTF_REG_PKT_INFO1_read=TX_INTF_REG_PKT_INFO1_read;
tx_intf_api->TX_INTF_REG_PKT_INFO2_read=TX_INTF_REG_PKT_INFO2_read;
tx_intf_api->TX_INTF_REG_PKT_INFO3_read=TX_INTF_REG_PKT_INFO3_read;
tx_intf_api->TX_INTF_REG_PKT_INFO4_read=TX_INTF_REG_PKT_INFO4_read;
tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read;
tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write;
@ -384,7 +411,10 @@ static int dev_probe(struct platform_device *pdev)
tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;
tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write=TX_INTF_REG_PHY_HDR_CONFIG_write;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write;
tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write;
tx_intf_api->TX_INTF_REG_PKT_INFO1_write=TX_INTF_REG_PKT_INFO1_write;
tx_intf_api->TX_INTF_REG_PKT_INFO2_write=TX_INTF_REG_PKT_INFO2_write;
tx_intf_api->TX_INTF_REG_PKT_INFO3_write=TX_INTF_REG_PKT_INFO3_write;
tx_intf_api->TX_INTF_REG_PKT_INFO4_write=TX_INTF_REG_PKT_INFO4_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -392,16 +422,16 @@ static int dev_probe(struct platform_device *pdev)
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);
printk("%s dev_probe succeed!\n", tx_intf_compatible_str);
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA);
//err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8);
//err = hw_init(TX_INTF_BYPASS, 8, 8);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma
return err;
}