prepare upgrade

2025-02-21 10:01:52 +00:00 · 2020-04-27 09:37:04 +02:00 · 2020-04-27 09:37:04 +02:00 · febc5adf73
commit febc5adf73
parent 0d75936c8d
47 changed files with 9152 additions and 679 deletions
--- a/README.md
+++ b/README.md
@ -35,11 +35,10 @@ board_name|board combination|status
 -------|-------|----
 zc706_fmcs2|Xilinx ZC706 dev board + FMCOMMS2/3/4|Done
 zed_fmcs2|Xilinx zed board + FMCOMMS2/3/4|Done
-adrv9364z7020|ADRV9364Z7020 SOM + ADRV1CRR-BOB carrier board|Done
-adrv9361z7035|ADRV9361Z7035 SOM + ADRV1CRR-BOB carrier board|Done
-adrv9361z7035_fmc|ADRV9361Z7035 SOM + ADRV1CRR-FMC carrier board|Done
+adrv9364z7020|ADRV9364Z7020 SOM|Done
+adrv9361z7035|ADRV9361Z7035 SOM|Done
 zc702_fmcs2|Xilinx ZC702 dev board + FMCOMMS2/3/4|Done
-zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Coming soon!
+zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Done
 zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future

 - board_name is used to identify FPGA design in openwifi-hw/boards/
@ -58,7 +57,9 @@ zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future
 [[Cite openwifi project](#Cite-openwifi-project)]

 ## Quick start
- Burn [openwifi image](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-1.img.xz) into a SD card (Double click or "Open With Disk Image Writer"). The SD card has two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **platform you have** by operating the SD card on your computer: **overwrite** the BOOT.BIN and devicetree.dtb in the base directory of BOOT partiton with the files in **openwifi/board_name** directory. (DO **NOT** touch **uImage**!)
+- Burn [openwifi image](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2.img.xz) into a SD card ("Open With Disk Image Writer". Or "dd" command after unzip). The SD card has two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: 
+  - Copy files in **openwifi/board_name** to the base directory of BOOT partiton.
+  - Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partiton
 - Connect two antennas to RXA/TXA ports. Config the board to SD card boot mode (check the board manual). Insert the SD card to the board. 
 - Power on. login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with one time password **analog**.
  ```
@ -116,7 +117,13 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
 - Get the latest FPGA bitstream from openwifi-hw, generate BOOT.BIN and transfer it on board via ssh channel:
  ```
  $OPENWIFI_DIR/user_space/get_fpga.sh $OPENWIFI_DIR
+  
+  For Zynq 7000:
  $OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME
+  
+  For Zynq MPSoC (like zcu102 board):
+  $OPENWIFI_DIR/user_space/boot_bin_gen_zynqmp.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME
+  
  scp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN root@192.168.10.122:
  ```
 - On board: Put the BOOT.BIN into the BOOT partition.
@ -132,11 +139,13 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
 Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to udpate the driver on board.
 - Prepare Analog Devices Linux kernel source code (only need to run once):
  ```
-  $OPENWIFI_DIR/user_space/prepare_kernel_src.sh $OPENWIFI_DIR $XILINX_DIR
+  $OPENWIFI_DIR/user_space/prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
+  (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
  ```
 - Compile the latest openwifi driver
  ```
-  $OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR
+  $OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
+  (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
  ```
 - Copy the driver files to the board via ssh channel
  ```
@ -169,7 +178,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
   - Input password "openwifi"

 ## Build openwifi Linux img from scratch
- Download [2017_R1-2018_01_29.img.xz](http://swdownloads.analog.com/cse/2017_R1-2018_01_29.img.xz) from [Analog Devices Wiki](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images). Burn it to a SD card.
+- Download [2019_R1-2020_02_04.img.xz](swdownloads.analog.com/cse/2019_R1-2020_02_04.img.xz) from [Analog Devices Wiki](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images). Burn it to a SD card.
 - Insert the SD card to your Linux PC. Find out the mount point (that has two sub directories BOOT and rootfs), and setup environment variables (use absolute path):
  ```
  export SDCARD_DIR=sdcard_mount_point
@ -198,7 +207,7 @@ $OPENWIFI_DIR/user_space/build_wpa_supplicant_wo11b.sh $OPENWIFI_DIR
 ```
 ## Porting guide

-This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. We use **2018_r1** of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
+This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on f61d9707 (2019 r1) of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
 - Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help)
 - Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository)
 - "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor".
--- a/driver/Makefile
+++ b/driver/Makefile
@ -3,7 +3,8 @@
 obj-m += sdr.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/ad9361/Makefile
+++ b/driver/ad9361/Makefile
@ -4,7 +4,8 @@ ad9361_drv-y := ad9361.o ad9361_conv.o
 obj-m += ad9361_drv.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/ad9361/ad9361.c
+++ b/driver/ad9361/ad9361.c
@ -1182,86 +1182,6 @@ static u64 ad9361_from_clk(unsigned long freq)
 	return ((u64)freq << 1);
 }

-static int ad9361_load_gt(struct ad9361_rf_phy *phy, u64 freq, u32 dest)
-{
-	struct ad9361_rf_phy_state *st = phy->state;
-	struct spi_device *spi = phy->spi;
-	u8 (*tab)[3];
-	u32 band, index_max, i, lna, lpf_tia_mask, set_gain;
-
-	dev_dbg(&phy->spi->dev, "%s: frequency %llu", __func__, freq);
-
-	band = ad9361_gt_tableindex(phy, freq);
-
-	dev_dbg(&phy->spi->dev, "%s: frequency %llu (band %d)",
-		__func__, freq, band);
-
-	/* check if table is present */
-	if (st->current_table == band)
-		return 0;
-
-	tab = phy->gt_info[band].tab;
-	index_max = phy->gt_info[band].max_index;
-
-	ad9361_spi_writef(spi, REG_AGC_CONFIG_2,
-			  AGC_USE_FULL_GAIN_TABLE, !phy->pdata->split_gt);
-
-	ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, index_max - 1); /* Max Full/LMT Gain Table Index */
-
-	set_gain = ad9361_spi_readf(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
-				    RX_FULL_TBL_IDX_MASK);
-	if (set_gain > (index_max - 1))
-		ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
-				  RX_FULL_TBL_IDX_MASK,  index_max - 1); /* Rx1 Full/LMT Gain Index */
-
-	set_gain = ad9361_spi_readf(spi, REG_RX2_MANUAL_LMT_FULL_GAIN,
-				    RX_FULL_TBL_IDX_MASK);
-	if (set_gain > (index_max - 1))
-		ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN,
-				 index_max - 1); /* Rx2 Full/LMT Gain Index */
-
-	lna = phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en ?
-		EXT_LNA_CTRL : 0;
-
-	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK |
-			RECEIVER_SELECT(dest)); /* Start Gain Table Clock */
-
-	/* TX QUAD Calibration */
-	if (phy->pdata->split_gt)
-		lpf_tia_mask = 0x20;
-	else
-		lpf_tia_mask = 0x3F;
-
-	st->tx_quad_lpf_tia_match = -EINVAL;
-
-	for (i = 0; i < index_max; i++) {
-		ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, i); /* Gain Table Index */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA1, tab[i][0] | lna); /* Ext LNA, Int LNA, & Mixer Gain Word */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA2, tab[i][1]); /* TIA & LPF Word */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA3, tab[i][2]); /* DC Cal bit & Dig Gain Word */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG,
-				START_GAIN_TABLE_CLOCK |
-				WRITE_GAIN_TABLE |
-				RECEIVER_SELECT(dest)); /* Gain Table Index */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay 3 ADCCLK/16 cycles */
-		ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
-
-		if ((tab[i][1] & lpf_tia_mask) == 0x20)
-			st->tx_quad_lpf_tia_match = i;
-
-	}
-
-	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK |
-			RECEIVER_SELECT(dest)); /* Clear Write Bit */
-	ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
-	ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
-	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, 0); /* Stop Gain Table Clock */
-
-	st->current_table = band;
-
-	return 0;
-}
-
 static int ad9361_setup_ext_lna(struct ad9361_rf_phy *phy,
 				struct elna_control *ctrl)
 {
@ -1325,7 +1245,7 @@ int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
 	dev_dbg(&phy->spi->dev, "%s : attenuation %u mdB tx1=%d tx2=%d",
 		__func__, atten_mdb, tx1, tx2);

-	if (atten_mdb > 89750) /* 89.75 dB */
+	if (atten_mdb > MAX_TX_ATTENUATION_DB) /* 89.75 dB */
 		return -EINVAL;

 	atten_mdb /= 250; /* Scale to 0.25dB / LSB */
@ -1417,6 +1337,9 @@ static int ad9361_trx_ext_lo_control(struct ad9361_rf_phy *phy,
 		ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2,
 					POWER_DOWN_TX_SYNTH, mcs_rf_enable ? 0 : enable);

+		ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2,
+					TX_SYNTH_READY_MASK, enable);
+
 		ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS,
 					 TX_VCO_DIVIDER(~0), enable ? 7 :
 					 st->cached_tx_rfpll_div);
@ -1443,6 +1366,9 @@ static int ad9361_trx_ext_lo_control(struct ad9361_rf_phy *phy,
 		ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2,
 					POWER_DOWN_RX_SYNTH, mcs_rf_enable ? 0 : enable);

+		ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2,
+					RX_SYNTH_READY_MASK, enable);
+
 		ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS,
 					 RX_VCO_DIVIDER(~0), enable ? 7 :
 					 st->cached_rx_rfpll_div);
@ -1859,6 +1785,112 @@ static int find_table_index(struct ad9361_rf_phy *phy, int gain)
 	return -EINVAL;
 }

+static int ad9361_load_gt(struct ad9361_rf_phy *phy, u64 freq, u32 dest)
+{
+	struct ad9361_rf_phy_state *st = phy->state;
+	struct spi_device *spi = phy->spi;
+	u8 (*tab)[3];
+	u32 band, index_max, i, lna, lpf_tia_mask, set_gain;
+	int ret, rx1_gain, rx2_gain;
+
+	dev_dbg(&phy->spi->dev, "%s: frequency %llu", __func__, freq);
+
+	band = ad9361_gt_tableindex(phy, freq);
+
+	dev_dbg(&phy->spi->dev, "%s: frequency %llu (band %d)",
+		__func__, freq, band);
+
+	/* check if table is present */
+	if (st->current_table == band)
+		return 0;
+
+	tab = phy->gt_info[band].tab;
+	index_max = phy->gt_info[band].max_index;
+
+	ad9361_spi_writef(spi, REG_AGC_CONFIG_2,
+			  AGC_USE_FULL_GAIN_TABLE, !phy->pdata->split_gt);
+
+	ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, index_max - 1); /* Max Full/LMT Gain Table Index */
+
+	set_gain = ad9361_spi_readf(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
+				    RX_FULL_TBL_IDX_MASK);
+
+	if (st->current_table >= 0) {
+		rx1_gain = phy->gt_info[st->current_table].abs_gain_tbl[set_gain];
+	} else {
+		if (set_gain > (index_max - 1))
+			set_gain = index_max - 1;
+
+		rx1_gain = phy->gt_info[band].abs_gain_tbl[set_gain];
+	}
+
+	set_gain = ad9361_spi_readf(spi, REG_RX2_MANUAL_LMT_FULL_GAIN,
+				    RX_FULL_TBL_IDX_MASK);
+
+	if (st->current_table >= 0) {
+		rx2_gain = phy->gt_info[st->current_table].abs_gain_tbl[set_gain];
+	} else {
+		if (set_gain > (index_max - 1))
+			set_gain = index_max - 1;
+
+		rx2_gain = phy->gt_info[band].abs_gain_tbl[set_gain];
+	}
+
+	lna = phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en ?
+		EXT_LNA_CTRL : 0;
+
+	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK |
+			 RECEIVER_SELECT(dest)); /* Start Gain Table Clock */
+
+	/* TX QUAD Calibration */
+	if (phy->pdata->split_gt)
+		lpf_tia_mask = 0x20;
+	else
+		lpf_tia_mask = 0x3F;
+
+	st->tx_quad_lpf_tia_match = -EINVAL;
+
+	for (i = 0; i < index_max; i++) {
+		ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, i); /* Gain Table Index */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA1, tab[i][0] | lna); /* Ext LNA, Int LNA, & Mixer Gain Word */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA2, tab[i][1]); /* TIA & LPF Word */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA3, tab[i][2]); /* DC Cal bit & Dig Gain Word */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG,
+				 START_GAIN_TABLE_CLOCK |
+				 WRITE_GAIN_TABLE |
+				 RECEIVER_SELECT(dest)); /* Gain Table Index */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay 3 ADCCLK/16 cycles */
+		ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
+
+		if ((tab[i][1] & lpf_tia_mask) == 0x20)
+			st->tx_quad_lpf_tia_match = i;
+
+	}
+
+	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK |
+			 RECEIVER_SELECT(dest)); /* Clear Write Bit */
+	ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
+	ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */
+	ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, 0); /* Stop Gain Table Clock */
+
+	st->current_table = band;
+
+	ret = find_table_index(phy, rx1_gain);
+	if (ret < 0)
+		ret = phy->gt_info[band].max_index - 1;
+
+	ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN,
+			  RX_FULL_TBL_IDX_MASK, ret); /* Rx1 Full/LMT Gain Index */
+
+	ret = find_table_index(phy, rx2_gain);
+	if (ret < 0)
+		ret = phy->gt_info[band].max_index - 1;
+
+	ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, ret); /* Rx2 Full/LMT Gain Index */
+
+	return 0;
+}
+
 static int set_split_table_gain(struct ad9361_rf_phy *phy, u32 idx_reg,
 		struct rf_rx_gain *rx_gain)
 {
@ -3949,13 +3981,22 @@ static int ad9361_ensm_set_state(struct ad9361_rf_phy *phy, u8 ensm_state,

 	 if (!phy->pdata->fdd && !pinctrl && !phy->pdata->tdd_use_dual_synth &&
 		 (ensm_state == ENSM_STATE_TX || ensm_state == ENSM_STATE_RX)) {
+		u32 reg, check;
+
+		if (ensm_state == ENSM_STATE_TX) {
+			reg = REG_TX_CP_OVERRANGE_VCO_LOCK;
+			check = !(st->cached_synth_pd[0] &
+				TX_SYNTH_VCO_POWER_DOWN);
+		} else {
+			reg = REG_RX_CP_OVERRANGE_VCO_LOCK;
+			check = !(st->cached_synth_pd[1] &
+				RX_SYNTH_VCO_POWER_DOWN);
+		}
+
 		ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2,
 				  TXNRX_SPI_CTRL, ensm_state == ENSM_STATE_TX);
-
-		ad9361_check_cal_done(phy, (ensm_state == ENSM_STATE_TX) ?
-				      REG_TX_CP_OVERRANGE_VCO_LOCK :
-				      REG_RX_CP_OVERRANGE_VCO_LOCK,
-				      VCO_LOCK, 1);
+		if (check)
+			ad9361_check_cal_done(phy, reg, VCO_LOCK, 1);
 	}

 	rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val);
@ -4349,7 +4390,8 @@ static int ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctr
 	ad9361_spi_write(phy->spi, REG_ENSM_MODE, fdd ? FDD_MODE : 0);

 	val = ad9361_spi_read(phy->spi, REG_ENSM_CONFIG_2);
-	val &= POWER_DOWN_RX_SYNTH | POWER_DOWN_TX_SYNTH;
+	val &= POWER_DOWN_RX_SYNTH | POWER_DOWN_TX_SYNTH |
+		RX_SYNTH_READY_MASK | TX_SYNTH_READY_MASK;

 	if (fdd)
 		ret = ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2,
@ -5618,8 +5660,8 @@ static int ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
 		ad9361_dig_tune(phy, 0, RESTORE_DEFAULT);

 	return ad9361_update_rf_bandwidth(phy,
-		valid ? st->filt_rx_bw_Hz : st->current_rx_bw_Hz,
-		valid ? st->filt_tx_bw_Hz : st->current_tx_bw_Hz);
+		(valid && st->filt_rx_bw_Hz) ? st->filt_rx_bw_Hz : st->current_rx_bw_Hz,
+		(valid && st->filt_tx_bw_Hz) ? st->filt_tx_bw_Hz : st->current_tx_bw_Hz);
 }

 static void ad9361_work_func(struct work_struct *work)
@ -7898,9 +7940,11 @@ static int ad9361_phy_read_avail(struct iio_dev *indio_dev,
 	switch (mask) {
 	case IIO_CHAN_INFO_HARDWAREGAIN:
 		if (chan->output) {
-			static const int tx_hw_gain[3] = {-89750, 250, 0};
+			static const int tx_hw_gain[] = {
+				89, -750000, 0, 250000, 0, 0
+			};
 			*vals = tx_hw_gain;
-			*type = IIO_VAL_INT;
+			*type = IIO_VAL_INT_PLUS_MICRO;
 			return IIO_AVAIL_RANGE;
 		} else {
 			st->rx_gain_avail[0] = phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[0];
@ -7925,6 +7969,9 @@ static int ad9361_phy_read_avail(struct iio_dev *indio_dev,
 			else
 				int_dec = st->tx_fir_int;

+			if (int_dec == 4)
+				max = MAX_TX_HB1 / 4;
+
 			st->tx_sampl_freq_avail[0] = MIN_ADC_CLK / (12 * int_dec);
 			st->tx_sampl_freq_avail[1] = 1;
 			st->tx_sampl_freq_avail[2] = max;
@ -7938,6 +7985,9 @@ static int ad9361_phy_read_avail(struct iio_dev *indio_dev,
 			else
 				int_dec = st->rx_fir_dec;

+			if (int_dec == 4)
+				max = MAX_RX_HB1 / 4;
+
 			st->rx_sampl_freq_avail[0] = MIN_ADC_CLK / (12 * int_dec);
 			st->rx_sampl_freq_avail[1] = 1;
 			st->rx_sampl_freq_avail[2] = max;
@ -8110,7 +8160,8 @@ static ssize_t ad9361_debugfs_write(struct file *file,
 {
 	struct ad9361_debugfs_entry *entry = file->private_data;
 	struct ad9361_rf_phy *phy = entry->phy;
-	u32 val, val2, val3, val4;
+	struct gpo_control *ctrl = &phy->pdata->gpo_ctrl;
+	u32 val, val2, val3, val4, mask;
 	char buf[80];
 	int ret;

@ -8215,6 +8266,60 @@ static ssize_t ad9361_debugfs_write(struct file *file,
 		entry->val = val;
 		return count;
 	case DBGFS_BIST_DT_ANALYSIS:
+		entry->val = val;
+		return count;
+	case DBGFS_GPO_SET:
+		if (ret != 2)
+			return -EINVAL;
+
+		if (!ctrl->gpo_manual_mode_en) {
+			dev_warn(&phy->spi->dev, "GPO manual mode not enabled!");
+			return -EINVAL;
+		}
+
+		switch (val) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			mask = BIT(val);
+			if (val2)
+				val3 = mask;
+			else
+				val3 = 0;
+			break;
+		case 0xF:
+			mask = 0xF;
+			val3 = val2 & 0xF;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		mutex_lock(&phy->indio_dev->mlock);
+		ctrl->gpo_manual_mode_enable_mask &= ~mask;
+		ctrl->gpo_manual_mode_enable_mask |= val3;
+
+		ret = ad9361_spi_write(phy->spi, REG_GPO_FORCE_AND_INIT,
+			GPO_MANUAL_CTRL(ctrl->gpo_manual_mode_enable_mask) |
+			GPO_INIT_STATE(ctrl->gpo0_inactive_state_high_en |
+			(ctrl->gpo1_inactive_state_high_en << 1) |
+			(ctrl->gpo2_inactive_state_high_en << 2) |
+			(ctrl->gpo3_inactive_state_high_en << 3)));
+
+		/*
+		 * GPO manual mode conflicts with automatic ENSM slave
+		 * and eLNA mode
+		 */
+
+		val3 = ad9361_spi_read(phy->spi, REG_EXTERNAL_LNA_CTRL);
+		if (!(val3 & GPO_MANUAL_SELECT))
+			ad9361_spi_write(phy->spi, REG_EXTERNAL_LNA_CTRL,
+					 val3 | GPO_MANUAL_SELECT);
+		mutex_unlock(&phy->indio_dev->mlock);
+		if (ret < 0)
+			return ret;
+
 		entry->val = val;
 		return count;
 	default:
@ -8278,6 +8383,7 @@ static int ad9361_register_debugfs(struct iio_dev *indio_dev)
 	ad9361_add_debugfs_entry(phy, "loopback", DBGFS_LOOPBACK);
 	ad9361_add_debugfs_entry(phy, "bist_prbs", DBGFS_BIST_PRBS);
 	ad9361_add_debugfs_entry(phy, "bist_tone", DBGFS_BIST_TONE);
+	ad9361_add_debugfs_entry(phy, "gpo_set", DBGFS_GPO_SET);
 	ad9361_add_debugfs_entry(phy, "bist_timing_analysis",
 		DBGFS_BIST_DT_ANALYSIS);
 	ad9361_add_debugfs_entry(phy, "gaininfo_rx1", DBGFS_RXGAIN_1);
@ -9215,28 +9321,34 @@ ad9361_gt_bin_read(struct file *filp, struct kobject *kobj,

 	struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj));
 	struct ad9361_rf_phy *phy = iio_priv(indio_dev);
-	int j, len = 0;
+	int ret, j, len = 0;
+	char *tab;

-	if (off)
-		return 0;
+	tab = kzalloc(bin_attr->size, GFP_KERNEL);
+	if (tab == NULL)
+		return -ENOMEM;

-	len += snprintf(buf + len, count - len,
+	len += snprintf(tab + len, bin_attr->size - len,
 		"<gaintable AD%i type=%s dest=%d start=%lli end=%lli>\n", 9361,
 		phy->gt_info[ad9361_gt(phy)].split_table ? "SPLIT" : "FULL", 3,
 		phy->gt_info[ad9361_gt(phy)].start,
 		phy->gt_info[ad9361_gt(phy)].end);

 	for (j = 0; j < phy->gt_info[ad9361_gt(phy)].max_index; j++)
-		len += snprintf(buf + len, count - len,
+		len += snprintf(tab + len, bin_attr->size - len,
 			"%d, 0x%.2X, 0x%.2X, 0x%.2X\n",
 			phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[j],
 			phy->gt_info[ad9361_gt(phy)].tab[j][0],
 			phy->gt_info[ad9361_gt(phy)].tab[j][1],
 			phy->gt_info[ad9361_gt(phy)].tab[j][2]);

-	len += snprintf(buf + len, count - len,"</gaintable>\n\n");
+	len += snprintf(tab + len, bin_attr->size - len, "</gaintable>\n");

-	return len;
+	ret = memory_read_from_buffer(buf, count, &off, tab, bin_attr->size);
+
+	kfree(tab);
+
+	return ret;
 }

 static int ad9361_probe(struct spi_device *spi)
@ -9351,7 +9463,7 @@ static int ad9361_probe(struct spi_device *spi)
 	phy->bin_gt.attr.mode = S_IWUSR | S_IRUGO;
 	phy->bin_gt.write = ad9361_gt_bin_write;
 	phy->bin_gt.read = ad9361_gt_bin_read;
-	phy->bin_gt.size = 32768;
+	phy->bin_gt.size = 4096;

 	indio_dev->dev.parent = &spi->dev;

--- a/driver/ad9361/ad9361.h
+++ b/driver/ad9361/ad9361.h
@ -4,16 +4,14 @@
 * Copyright 2013-2018 Analog Devices Inc.
 * 
 * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
+ *
 * Licensed under the GPL-2.
 */

 #ifndef IIO_FREQUENCY_AD9361_H_
 #define IIO_FREQUENCY_AD9361_H_

-//#define IIO_AD9361_USE_PRIVATE_H_
-
 #include "ad9361_regs.h"
-//#include "ad9361_private.h"

 enum ad9361_clocks {
 	BB_REFCLK,
@ -51,6 +49,7 @@ enum debugfs_cmd {
 	DBGFS_MCS,
 	DBGFS_CAL_SW_CTRL,
 	DBGFS_DIGITAL_TUNE,
+	DBGFS_GPO_SET,
 };

 enum dig_tune_flags {
@ -172,7 +171,7 @@ struct ad9361_rf_phy {
 	struct refclk_scale	clk_priv[NUM_AD9361_CLKS];
 	struct clk_onecell_data	clk_data;
 	struct ad9361_phy_platform_data *pdata;
-	struct ad9361_debugfs_entry debugfs_entry[181];
+	struct ad9361_debugfs_entry debugfs_entry[182];
 	struct bin_attribute 	bin;
 	struct bin_attribute 	bin_gt;
 	struct iio_dev 		*indio_dev;
@ -185,6 +184,7 @@ struct ad9361_rf_phy {
 	struct ad9361_ext_band_ctl	*ext_band_ctl;
 	struct ad9361_rf_phy_state	*state;
 };
+
 int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);
 int ad9361_clk_set_rate(struct clk *clk, unsigned long rate);
 int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
--- a/driver/ad9361/ad9361_conv.c
+++ b/driver/ad9361/ad9361_conv.c
@ -2,8 +2,6 @@
 * AD9361 Agile RF Transceiver
 *
 * Copyright 2013-2017 Analog Devices Inc.
- * 
- * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
 *
 * Licensed under the GPL-2.
 */
@ -346,7 +344,7 @@ int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
 	version = axiadc_read(st, 0x4000);

 	/* Still there but implemented a bit different */
-	if (PCORE_VERSION_MAJOR(version) > 7)
+	if (ADI_AXI_PCORE_VER_MAJOR(version) > 7)
 		addr = 0x4418;
 	else
 		addr = 0x4414;
@ -354,10 +352,12 @@ int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
 	for (chan = 0; chan < conv->chip_info->num_channels; chan++) {
 		reg = axiadc_read(st, addr + (chan) * 0x40);

-		if (PCORE_VERSION_MAJOR(version) > 7) {
-			if (enable && reg != 0x8) {
-				conv->scratch_reg[chan] = reg;
-				reg = 0x8;
+		if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) {
+			if (enable) {
+				if (reg != 0x8) {
+					conv->scratch_reg[chan] = reg;
+					reg = 0x8;
+				}
 			} else if (reg == 0x8) {
 				reg = conv->scratch_reg[chan];
 			}
@ -379,7 +379,7 @@ static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane,
 			      unsigned val, bool tx)
 {
 	if (tx) {
-		if (PCORE_VERSION_MAJOR(st->pcore_version) > 8)
+		if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8)
 			axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val);
 		else
 			return -ENODEV;
@ -463,7 +463,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
 				 unsigned long max_freq,
 				 enum dig_tune_flags flags, bool tx)
 {
-	static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
+	//static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; //some low end FPGA, such as z7020, lvds ADC interface seems not stable enough to support 61.44Msps
+	static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
 	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
 	unsigned int s0, s1, c0, c1;
 	unsigned int i, j, r;
@ -565,7 +566,7 @@ static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
 			ADI_ENABLE | ADI_IQCOR_ENB);
 		axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM);
 		saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40);
-		if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) {
+		if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
 			saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40);
 			axiadc_write(st, 0x4418 + (chan) * 0x40, 9);
 			axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */
@ -574,7 +575,7 @@ static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
 			axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */
 		}
 	}
-	if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) {
+	if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) {
 		saved = tmp = axiadc_read(st, 0x4048);
 		tmp &= ~0xF;
 		tmp |= 1;
@ -585,14 +586,14 @@ static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
 	if (flags & DO_ODELAY)
 		ad9361_dig_tune_iodelay(phy, true);

-	if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8)
+	if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8)
 		axiadc_write(st, 0x4048, saved);

 	for (chan = 0; chan < num_chan; chan++) {
 		axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
 			     saved_chan_ctrl0[chan]);
 		axiadc_set_pnsel(st, chan, ADC_PN9);
-		if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) {
+		if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
 			axiadc_write(st, 0x4418 + chan * 0x40,
 				     saved_dsel[chan]);
 			axiadc_write(st, 0x4044, 1);
@ -711,13 +712,13 @@ static int ad9361_post_setup(struct iio_dev *indio_dev)

 	flags = 0;

-	ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
+	ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
 		0 : 61440000, flags);
 	if (ret < 0)
 		goto error;

 	if (flags & (DO_IDELAY | DO_ODELAY)) {
-		ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
+		ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
 			0 : 61440000, flags & BE_VERBOSE);
 		if (ret < 0)
 			goto error;
--- a/driver/ad9361/ad9361_private.h
+++ b/driver/ad9361/ad9361_private.h
@ -180,6 +180,25 @@ struct auxdac_control {
 	u8 dac2_tx_delay_us;
 };

+#if 0
+enum rssi_restart_mode {
+	AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
+	EN_AGC_PIN_IS_PULLED_HIGH,
+	ENTERS_RX_MODE,
+	GAIN_CHANGE_OCCURS,
+	SPI_WRITE_TO_REGISTER,
+	GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
+};
+
+struct rssi_control {
+	enum rssi_restart_mode restart_mode;
+	bool rssi_unit_is_rx_samples;	/* default unit is time */
+	u32 rssi_delay;
+	u32 rssi_wait;
+	u32 rssi_duration;
+};
+#endif
+
 struct rx_gain_info {
 	enum rx_gain_table_type tbl_type;
 	int starting_gain_db;
@ -377,6 +396,15 @@ struct rf_rx_gain {
 	u32 mixer_index;		/* MIXER Index (Split GT mode only) */

 };
+#if 0
+struct rf_rssi {
+	u32 ant;		/* Antenna number for which RSSI is reported */
+	u32 symbol;		/* Runtime RSSI */
+	u32 preamble;		/* Initial RSSI */
+	s32 multiplier;	/* Multiplier to convert reported RSSI */
+	u8 duration;		/* Duration to be considered for measuring */
+};
+#endif

 struct SynthLUT {
 	u16 VCO_MHz;
--- a/driver/ad9361/ad9361_regs.h
+++ b/driver/ad9361/ad9361_regs.h
@ -2,8 +2,6 @@
 * AD9361
 *
 * Copyright 2013-2018 Analog Devices Inc.
- * 
- * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
 *
 * Licensed under the GPL-2.
 */
@ -2795,17 +2793,16 @@
 */

 #define MIN_ADC_CLK			25000000UL /* 25 MHz */
-//#define MIN_ADC_CLK			(MIN_BBPLL_FREQ / MAX_BBPLL_DIV) /* 11.17MHz */
 #define MAX_ADC_CLK			640000000UL /* 640 MHz */
 #define MAX_DAC_CLK			(MAX_ADC_CLK / 2)

 /* Associated with outputs of stage */
-#define MAX_RX_HB1			245760000UL
-#define MAX_RX_HB2			320000000UL
-#define MAX_RX_HB3			640000000UL
+#define MAX_RX_HB1			122880000UL
+#define MAX_RX_HB2			245760000UL
+#define MAX_RX_HB3			320000000UL
 /* Associated with inputs of stage */
-#define MAX_TX_HB1			160000000UL
-#define MAX_TX_HB2			320000000UL
+#define MAX_TX_HB1			122880000UL
+#define MAX_TX_HB2			245760000UL
 #define MAX_TX_HB3			320000000UL

 #define MAX_BASEBAND_RATE		61440000UL
@ -2829,4 +2826,6 @@
 #define MAX_GAIN_TABLE_SIZE		90
 #define MAX_NUM_GAIN_TABLES		16 /* randomly picked */

+#define MAX_TX_ATTENUATION_DB		89750
+
 #endif
--- a/driver/ad9361/cf_axi_adc.h
+++ b/driver/ad9361/cf_axi_adc.h
@ -6,26 +6,12 @@
 * Licensed under the GPL-2.
 *
 * http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
- * 
- * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
- * 
 */

 #ifndef ADI_AXI_ADC_H_
 #define ADI_AXI_ADC_H_

-#define ADI_REG_VERSION		0x0000				/*Version and Scratch Registers */
-#define ADI_VERSION(x)		(((x) & 0xffffffff) << 0)	/* RO, Version number. */
-#define VERSION_IS(x,y,z)	((x) << 16 | (y) << 8 | (z))
-#define ADI_REG_ID		0x0004			 	/*Version and Scratch Registers */
-#define ADI_ID(x)		(((x) & 0xffffffff) << 0)   	/* RO, Instance identifier number. */
-#define ADI_REG_SCRATCH		0x0008			 	/*Version and Scratch Registers */
-#define ADI_SCRATCH(x)		(((x) & 0xffffffff) << 0)	/* RW, Scratch register. */
-
-#define PCORE_VERSION(major, minor, letter) ((major << 16) | (minor << 8) | letter)
-#define PCORE_VERSION_MAJOR(version) (version >> 16)
-#define PCORE_VERSION_MINOR(version) ((version >> 8) & 0xff)
-#define PCORE_VERSION_LETTER(version) (version & 0xff)
+#include <linux/fpga/adi-axi-common.h>

 /* ADC COMMON */

@ -205,6 +191,7 @@ struct axiadc_state {
 	struct device 			*dev_spi;
 	struct iio_info			iio_info;
 	struct clk 			*clk;
+	struct gpio_desc		*gpio_decimation;
 	size_t				regs_size;
 	void __iomem			*regs;
 	void __iomem			*slave_regs;
@ -214,9 +201,11 @@ struct axiadc_state {
 	unsigned			id;
 	unsigned			pcore_version;
 	unsigned			decimation_factor;
+	unsigned int                    oversampling_ratio;
 	bool				dp_disable;
 	unsigned long long		adc_clk;
 	unsigned			have_slave_channels;
+	bool				additional_channel;

 	struct iio_hw_consumer		*frontend;

@ -239,6 +228,7 @@ struct axiadc_converter {
 	unsigned long 		adc_clk;
 	const struct axiadc_chip_info	*chip_info;

+	struct delayed_work	watchdog_work;
 	bool			sample_rate_read_only;

 	int (*reg_access)(struct iio_dev *indio_dev, unsigned int reg,
@ -289,6 +279,7 @@ struct axiadc_converter {
 			int state);

 	int (*post_setup)(struct iio_dev *indio_dev);
+	int (*post_iio_register)(struct iio_dev *indio_dev);
 	int (*set_pnsel)(struct iio_dev *indio_dev, unsigned chan,
 			enum adc_pn_sel sel);
 };
@ -338,7 +329,7 @@ static inline unsigned int axiadc_slave_read(struct axiadc_state *st, unsigned r
 static inline void axiadc_idelay_set(struct axiadc_state *st,
 				unsigned lane, unsigned val)
 {
-	if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) {
+	if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8) {
 		axiadc_write(st, ADI_REG_DELAY(lane), val);
 	} else {
 		axiadc_write(st, ADI_REG_DELAY_CNTRL, 0);
--- a/driver/hw_def.h
+++ b/driver/hw_def.h
@ -26,7 +26,7 @@ const char *tx_intf_compatible_str = "sdr,tx_intf";
 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)
 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)
 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)
-#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL1_ADDR     (12*4)
+#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR         (12*4)
 #define TX_INTF_REG_BB_GAIN_ADDR                   (13*4)
 #define TX_INTF_REG_INTERRUPT_SEL_ADDR             (14*4)
 #define TX_INTF_REG_ANT_SEL_ADDR                   (16*4)
@ -68,6 +68,7 @@ struct tx_intf_driver_api {
 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
 	u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
+	u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
 	u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
 	u32 (*TX_INTF_REG_BB_GAIN_read)(void);
 	u32 (*TX_INTF_REG_ANT_SEL_read)(void);
@ -86,6 +87,7 @@ struct tx_intf_driver_api {
 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
 	void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
+	void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
 	void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
 	void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
 	void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
--- a/driver/make_all.sh
+++ b/driver/make_all.sh
@ -1,11 +1,12 @@
 #!/bin/bash
-if [ "$#" -ne 2 ]; then
-    echo "You must enter exactly 2 arguments: \$OPENWIFI_DIR \$XILINX_DIR"
+if [ "$#" -ne 3 ]; then
+    echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)"
    exit 1
 fi

 OPENWIFI_DIR=$1
 XILINX_DIR=$2
+ARCH_OPTION=$3

 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
    echo "\$OPENWIFI_DIR is found!"
@ -21,47 +22,51 @@ else
    exit 1
 fi

-adi_lnx_dir=$OPENWIFI_DIR/adi-linux/
-xilinx_sdk_dir=$XILINX_DIR/SDK/2017.4/
-
-# check if user entered the right path to SDK
-if [ -d "$xilinx_sdk_dir" ]; then
-  echo " setup sdk path ${xilinx_sdk_dir}"
-  tmp=/settings64.sh
-  sdk_setting="$xilinx_sdk_dir$tmp"
-  source ${sdk_setting}
+if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
+    echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
+    exit 1
 else
-  echo "Error: sdk: ${xilinx_sdk_dir} not found. Can not continue."
-  exit 1
+    echo "\$ARCH_OPTION is valid!"
+fi
+
+source $XILINX_DIR/SDK/2018.3/settings64.sh
+if [ "$ARCH_OPTION" == "64" ]; then
+    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
+    ARCH="arm64"
+    CROSS_COMPILE="aarch64-linux-gnu-"
+else
+    LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/
+    ARCH="arm"
+    CROSS_COMPILE="arm-linux-gnueabihf-"
 fi

 # check if user entered the right path to analog device linux
-if [ -d "$adi_lnx_dir" ]; then
-  echo " setup linux kernel path ${adi_lnx_dir}"
+if [ -d "$LINUX_KERNEL_SRC_DIR" ]; then
+    echo " setup linux kernel path ${LINUX_KERNEL_SRC_DIR}"
 else
-  echo "Error: path to adi linux: ${adi_lnx_dir} not found. Can not continue."
-  exit 1
+    echo "Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue."
+    exit 1
 fi

+set -x
+
 home_dir=$(pwd)

-#source ~/Xilinx/SDK/2017.4/settings64.sh
-#set -x
 cd $OPENWIFI_DIR/driver/
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/openofdm_tx
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/openofdm_rx
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/tx_intf
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/rx_intf
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/xpu
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/ad9361
-make KDIR=$adi_lnx_dir
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/xilinx_dma
-./make_xilinx_dma.sh $adi_lnx_dir $sdk_setting
+./make_xilinx_dma.sh $OPENWIFI_DIR $XILINX_DIR $ARCH_OPTION

 cd $home_dir
--- a/driver/openofdm_rx/Makefile
+++ b/driver/openofdm_rx/Makefile
@ -3,7 +3,8 @@
 obj-m += openofdm_rx.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules 
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/openofdm_tx/Makefile
+++ b/driver/openofdm_tx/Makefile
@ -3,7 +3,8 @@
 obj-m += openofdm_tx.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/rx_intf/Makefile
+++ b/driver/rx_intf/Makefile
@ -3,7 +3,8 @@
 obj-m += rx_intf.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/rx_intf/rx_intf.c
+++ b/driver/rx_intf/rx_intf.c
@ -268,7 +268,7 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
 	}

 	if (mode!=RX_INTF_AXIS_LOOP_BACK) {
-		rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg);
+		// rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); --now rx doesn't have mixer anymore
 		// 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz
 		// 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
 		// 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
@ -296,9 +296,7 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
 		// 0-bw20-ch0; 1-bw2-ch0;  2-bw2-ch2;  3-bw2-ch4;  4-bw2-ch6;  5-s_axis-ch0
 		// 8-bw20-ch1; 9-bw2-ch1; 10-bw2-ch3; 11-bw2-ch5; 12-bw2-ch7; 13-s_axis-ch1

-		//rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(1000|0x80000000); //0x80000000 to enable tsft and rssi gpio test magic value
-		//rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(200*10); //0x80000000 to enable tsft and rssi gpio test magic value
-		rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*200); // delayed interrupt
+		rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed
 		
 		rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0);
 		rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically
--- a/driver/sdr.c
+++ b/driver/sdr.c
@ -156,10 +156,10 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
 				priv->band = BAND_2_4GHZ;
 				xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16) );
 			}
-			// //xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((45+2)*200)<<16) | 200 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time.  let's add 2us for those device that is really "slow"!
-			// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((45+2+2)*200)<<16) | 200 );//add 2us for longer fir. BUT corrding to FPGA probing test, we do not need this
+			// //xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((45+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time.  let's add 2us for those device that is really "slow"!
+			// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((45+2+2)*10)<<16) | 10 );//add 2us for longer fir. BUT corrding to FPGA probing test, we do not need this
 			// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 0 );
-			// tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(((10)*200)<<16);
+			// tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(((10)*10)<<16);
 		}
 		else {
 			//priv->slot_time = 9; //default slot time of OFDM PHY (OFDM by default means 5GHz)
@ -168,11 +168,11 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
 				priv->band = BAND_5_8GHZ;
 				xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16) );
 			}
-			// //xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((51+2)*200)<<16) | 200 ); // because 5GHz needs longer SIFS (16 instead of 10), we need 58 instead of 48 for XPU low mac setting.  let's add 2us for those device that is really "slow"!
-			// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((51+2+2)*200)<<16) | 200 );//add 2us for longer fir.  BUT corrding to FPGA probing test, we do not need this
-			// //xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 1200 );
-			// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 1000 );// for longer fir we need this delay 1us shorter
-			// tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(((16)*200)<<16);
+			// //xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((51+2)*10)<<16) | 10 ); // because 5GHz needs longer SIFS (16 instead of 10), we need 58 instead of 48 for XPU low mac setting.  let's add 2us for those device that is really "slow"!
+			// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP_write( (((51+2+2)*10)<<16) | 10 );//add 2us for longer fir.  BUT corrding to FPGA probing test, we do not need this
+			// //xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 60*10 );
+			// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 50*10 );// for longer fir we need this delay 1us shorter
+			// tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(((16)*10)<<16);
 		}
 		//printk("%s ad9361_rf_set_channel %dM rssi_correction %d\n", sdr_compatible_str,conf->chandef.chan->center_freq,priv->rssi_correction);
 		// //-- use less
@ -261,7 +261,7 @@ static void openwifi_free_tx_ring(struct openwifi_priv *priv)
 //			dev_kfree_skb(ring->bds[i].skb_linked);
 		if ( (ring->bds[i].dma_mapping_addr != 0 && ring->bds[i].skb_linked == 0) ||
 		     (ring->bds[i].dma_mapping_addr == 0 && ring->bds[i].skb_linked != 0))
-			printk("%s openwifi_free_tx_ring: WARNING %d skb_linked %08x dma_mapping_addr %08x\n", sdr_compatible_str, i, (u32)(ring->bds[i].skb_linked), ring->bds[i].dma_mapping_addr);
+			printk("%s openwifi_free_tx_ring: WARNING %d skb_linked %p dma_mapping_addr %08llx\n", sdr_compatible_str, i, (void*)(ring->bds[i].skb_linked), ring->bds[i].dma_mapping_addr);

 		ring->bds[i].skb_linked=0;
 		ring->bds[i].dma_mapping_addr = 0;
@ -298,7 +298,7 @@ static int rx_dma_setup(struct ieee80211_hw *dev){
 	priv->rxd = rx_dev->device_prep_dma_cyclic(priv->rx_chan,priv->rx_cyclic_buf_dma_mapping_addr,RX_BD_BUF_SIZE*NUM_RX_BD,RX_BD_BUF_SIZE,DMA_DEV_TO_MEM,DMA_CTRL_ACK|DMA_PREP_INTERRUPT);
 	if (!(priv->rxd)) {
 		openwifi_free_rx_ring(priv);
-		printk("%s rx_dma_setup: WARNING rx_dev->device_prep_dma_cyclic %d\n", sdr_compatible_str, (u32)(priv->rxd));
+		printk("%s rx_dma_setup: WARNING rx_dev->device_prep_dma_cyclic %p\n", sdr_compatible_str, (void*)(priv->rxd));
 		return(-1);
 	}
 	priv->rxd->callback = 0;
@ -518,7 +518,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
 		//ring_len = (just_wr_idx>=current_rd_idx)?(just_wr_idx-current_rd_idx):(just_wr_idx+NUM_TX_BD-current_rd_idx);
 		ring_len = ((just_wr_idx-current_rd_idx)&(NUM_TX_BD-1));
 		ring_room_left = NUM_TX_BD - ring_len;
-		if (ring_room_left > 2 && priv->tx_queue_stopped) {
+		if (ring_room_left > RING_ROOM_THRESHOLD && priv->tx_queue_stopped) {
 			unsigned int prio = skb_get_queue_mapping(skb);
 			ieee80211_wake_queue(dev, prio);
 			printk("%s openwifi_tx_interrupt: WARNING ieee80211_wake_queue. ring_room_left %d prio %d curr rd %d just wr %d\n", sdr_compatible_str,ring_room_left,prio,current_rd_idx,just_wr_idx);
@ -709,6 +709,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 			sc,info->flags,retry_limit_raw,pkt_need_ack,queue_idx,priv->phy_tx_sn,
 			use_rts_cts,use_cts_protect|force_use_cts_protect,wifi_rate_all[cts_rate_hw_value],cts_duration,
 			ring->bd_wr_idx,ring->bd_rd_idx);
+
 		// printk("%s openwifi_tx: rate&try: %d %d %03x; %d %d %03x; %d %d %03x; %d %d %03x\n", sdr_compatible_str,
 		// 	info->status.rates[0].idx,info->status.rates[0].count,info->status.rates[0].flags,
 		// 	info->status.rates[1].idx,info->status.rates[1].count,info->status.rates[1].flags,
@ -779,11 +780,11 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 	//ring_len = (ring->bd_wr_idx>=ring->bd_rd_idx)?(ring->bd_wr_idx-ring->bd_rd_idx):(ring->bd_wr_idx+NUM_TX_BD-ring->bd_rd_idx);
 	ring_len = ((ring->bd_wr_idx-ring->bd_rd_idx)&(NUM_TX_BD-1));
 	ring_room_left = NUM_TX_BD - ring_len;
-	if (ring_len>28)
+	if (ring_room_left < RING_ROOM_THRESHOLD)
 		printk("%s openwifi_tx: WARNING ring len %d\n", sdr_compatible_str,ring_len);
 //		printk("%s openwifi_tx: WARNING ring len %d HW fifo %d q %d\n", sdr_compatible_str,ring_len,tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read()&0xFFFF, ((tx_intf_api->TX_INTF_REG_PHY_QUEUE_TX_SN_read())>>16)&0xFF );

-	if (ring_room_left <= 2 && priv->tx_queue_stopped == false) {
+	if (ring_room_left <= RING_ROOM_THRESHOLD && priv->tx_queue_stopped == false) {
 		ieee80211_stop_queue(dev, prio);
 		printk("%s openwifi_tx: WARNING ieee80211_stop_queue. ring_room_left %d!\n", sdr_compatible_str,ring_room_left);
 		priv->tx_queue_stopped = true;
@ -822,7 +823,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 	tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(dma_reg);
 	priv->txd = priv->tx_chan->device->device_prep_slave_sg(priv->tx_chan, &(priv->tx_sg),1,DMA_MEM_TO_DEV, DMA_CTRL_ACK | DMA_PREP_INTERRUPT, NULL);
 	if (!(priv->txd)) {
-		printk("%s openwifi_tx: WARNING device_prep_slave_sg %d\n", sdr_compatible_str, (u32)(priv->txd));
+		printk("%s openwifi_tx: WARNING device_prep_slave_sg %p\n", sdr_compatible_str, (void*)(priv->txd));
 		goto openwifi_tx_after_dma_mapping;
 	}

@ -926,17 +927,17 @@ static int openwifi_start(struct ieee80211_hw *dev)
 	// // xpu_api->XPU_REG_CSMA_CFG_write(3); // cw_min
 	// xpu_api->XPU_REG_CSMA_CFG_write(3);

-	//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
-	//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030)<<16)|0 );//now our tx send out I/Q immediately
-	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030+450)<<16)|(0+450) );//we have more time when we use FIR in AD9361
+	//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
+	//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
+	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51+23)<<16)|(0+23) );//we have more time when we use FIR in AD9361

-	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200 + 300)<<16) | 200 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
-	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200 + 300)<<16) | 200 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)

-	tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*200)<<16)|(10*200) );//high 16bit 5GHz; low 16 bit 2.4GHz
+	tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
 	
-	//xpu_api->XPU_REG_BB_RF_DELAY_write(1020); // fine tuned value at 0.005us. old: dac-->ant port: 0.6us, 57 taps fir at 40MHz: 1.425us; round trip: 2*(0.6+1.425)=4.05us; 4.05*200=810
-	xpu_api->XPU_REG_BB_RF_DELAY_write(975);//add .5us for slightly longer fir
+	//xpu_api->XPU_REG_BB_RF_DELAY_write(51); // fine tuned value at 0.005us. old: dac-->ant port: 0.6us, 57 taps fir at 40MHz: 1.425us; round trip: 2*(0.6+1.425)=4.05us; 4.05*10=41
+	xpu_api->XPU_REG_BB_RF_DELAY_write(49);//add .5us for slightly longer fir
 	xpu_api->XPU_REG_MAC_ADDR_write(priv->mac_addr);

 	xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write(50000-1); // total 50ms.
@ -1736,12 +1737,18 @@ static int openwifi_dev_probe(struct platform_device *pdev)
 	// //-------------find ad9361-phy driver for lo/channel control---------------
 	priv->actual_rx_lo = 0;
 	tmp_dev = bus_find_device( &spi_bus_type, NULL, "ad9361-phy", custom_match_spi_dev );
-	if (!tmp_dev) {
+	if (tmp_dev == NULL) {
 		printk(KERN_ERR "%s find_dev ad9361-phy failed\n",sdr_compatible_str);
 		err = -ENOMEM;
 		goto err_free_dev;
 	}
-	printk("%s bus_find_device ad9361-phy: %s\n", sdr_compatible_str, tmp_dev->init_name);
+	printk("%s bus_find_device ad9361-phy: %s. driver_data pointer %p\n", sdr_compatible_str, ((struct spi_device*)tmp_dev)->modalias, (void*)(((struct spi_device*)tmp_dev)->dev.driver_data));
+	if (((struct spi_device*)tmp_dev)->dev.driver_data == NULL) {
+		printk(KERN_ERR "%s find_dev ad9361-phy failed. dev.driver_data == NULL\n",sdr_compatible_str);
+		err = -ENOMEM;
+		goto err_free_dev;
+	}
+	
 	priv->ad9361_phy = ad9361_spi_to_phy((struct spi_device*)tmp_dev);
 	if (!(priv->ad9361_phy)) {
 		printk(KERN_ERR "%s ad9361_spi_to_phy failed\n",sdr_compatible_str);
@ -2043,7 +2050,7 @@ static int openwifi_dev_remove(struct platform_device *pdev)
 	struct ieee80211_hw *dev = platform_get_drvdata(pdev);

 	if (!dev) {
-		pr_info("%s openwifi_dev_remove: dev %d\n", sdr_compatible_str, (u32)dev);
+		pr_info("%s openwifi_dev_remove: dev %p\n", sdr_compatible_str, (void*)dev);
 		return(-1);
 	}

--- a/driver/sdr.h
+++ b/driver/sdr.h
@ -71,6 +71,7 @@ union u16_byte2 {
 #define LEN_PHY_HEADER 16
 #define LEN_PHY_CRC 4

+#define RING_ROOM_THRESHOLD 4
 #define NUM_TX_BD 32
 #define NUM_RX_BD 16
 #define TX_BD_BUF_SIZE (8192)
@ -251,6 +252,35 @@ static const u16 wifi_n_dbps_table[16] =           {24, 24, 24, 24, 24, 36, 48,
 // static const u8 wifi_mcs_table[8] =             {6,9,12,18,24,36,48,54};
 // static const u8 wifi_mcs_table_phy_tx[8]    =   {11,15,10,14,9,13,8,12};

+// ===== copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====
+struct cf_axi_dds_state {
+	struct device			*dev_spi;
+	struct clk			*clk;
+	struct cf_axi_dds_chip_info	*chip_info;
+	struct gpio_desc		*plddrbypass_gpio;
+	struct gpio_desc		*interpolation_gpio;
+
+	bool				standalone;
+	bool				dp_disable;
+	bool				enable;
+	bool				pl_dma_fifo_en;
+	enum fifo_ctrl			gpio_dma_fifo_ctrl;
+
+	struct iio_info			iio_info;
+	size_t				regs_size;
+	void __iomem			*regs;
+	void __iomem			*slave_regs;
+	void __iomem			*master_regs;
+	u64				dac_clk;
+	unsigned int			ddr_dds_interp_en;
+	unsigned int			cached_freq[16];
+	unsigned int			version;
+	unsigned int			have_slave_channels;
+	unsigned int			interpolation_factor;
+	struct notifier_block		clk_nb;
+};
+// ===== end of copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====
+
 #define RX_DMA_CYCLIC_MODE
 struct openwifi_priv {
 	struct platform_device *pdev;
--- a/driver/tx_intf/Makefile
+++ b/driver/tx_intf/Makefile
@ -3,7 +3,8 @@
 obj-m += tx_intf.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/tx_intf/tx_intf.c
+++ b/driver/tx_intf/tx_intf.c
@ -78,6 +78,10 @@ static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){
 	return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
 }

+static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){
+	return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR);
+}
+
 static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){
 	return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR);
 }
@ -148,6 +152,10 @@ static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
 	reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
 }

+static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){
+	reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value);
+}
+
 static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){
 	reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value);
 }
@ -257,11 +265,12 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
 		tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
 		tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel);
 		tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2);
-		tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*200)<<16)|(10*200) );//high 16bit 5GHz; low 16 bit 2.4GHz
+		tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed

 		tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
 		tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
 		tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);
+		tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420);
 		tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x40); //.src_sel0(slv_reg14[2:0]), .src_sel1(slv_reg14[6:4]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-xpu signal
 		tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30040); //disable interrupt
 		tx_intf_api->TX_INTF_REG_BB_GAIN_write(100);
@ -316,6 +325,7 @@ static int dev_probe(struct platform_device *pdev)
 	tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
 	tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
 	tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read;
+	tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read;
 	tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read;
 	tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read;
 	tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;
@ -334,6 +344,7 @@ static int dev_probe(struct platform_device *pdev)
 	tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
 	tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
 	tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write;
+	tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write;
 	tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write;
 	tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write;
 	tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;
@ -346,10 +357,10 @@ static int dev_probe(struct platform_device *pdev)
 	if (IS_ERR(base_addr))
 		return PTR_ERR(base_addr);

-	printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
-	printk("%s dev_probe base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr);
-	printk("%s dev_probe tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) );
-	printk("%s dev_probe             tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api);
+	printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
+	printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
+	printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
+	printk("%s dev_probe             tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);

 	printk("%s dev_probe succeed!\n", tx_intf_compatible_str);

@ -364,9 +375,9 @@ static int dev_remove(struct platform_device *pdev)
 {
 	printk("\n");

-	printk("%s dev_remove base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr);
-	printk("%s dev_remove tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) );
-	printk("%s dev_remove             tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api);
+	printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
+	printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
+	printk("%s dev_remove             tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);

 	printk("%s dev_remove succeed!\n", tx_intf_compatible_str);
 	return 0;
--- a/driver/xilinx_dma/make_xilinx_dma.sh
+++ b/driver/xilinx_dma/make_xilinx_dma.sh
@ -1,17 +1,55 @@
 #!/bin/bash
-set -x
+if [ "$#" -ne 3 ]; then
+    echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$ARCH(32 or 64)"
+    exit 1
+fi

 WORKDIR=$PWD
-KDIR=$1
+OPENWIFI_DIR=$1
+XILINX_DIR=$2
+ARCH_OPTION=$3
+
+set -x
+
+if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
+    echo "\$OPENWIFI_DIR is found!"
+else
+    echo "\$OPENWIFI_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ -d "$XILINX_DIR/SDK" ]; then
+    echo "\$XILINX_DIR is found!"
+else
+    echo "\$XILINX_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
+    echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
+    exit 1
+else
+    echo "\$ARCH_OPTION is valid!"
+fi
+
+source $XILINX_DIR/SDK/2018.3/settings64.sh
+if [ "$ARCH_OPTION" == "64" ]; then
+    KDIR=$OPENWIFI_DIR/adi-linux-64/
+    export ARCH=arm64
+    export CROSS_COMPILE=aarch64-linux-gnu-
+else
+    KDIR=$OPENWIFI_DIR/adi-linux/
+    export ARCH=arm
+    export CROSS_COMPILE=arm-linux-gnueabihf-
+fi
+
 SUBMODULE=xilinx_dma

-source $2
-export ARCH=arm
-export CROSS_COMPILE=arm-linux-gnueabihf-
-
+cp $KDIR/drivers/dma/xilinx/xilinx_dma.c $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak
 cp xilinx_dma.c $KDIR/drivers/dma/xilinx -rf
 cd $KDIR
 make $KDIR/drivers/dma/xilinx/$SUBMODULE.ko
 cp $KDIR/drivers/dma/xilinx/$SUBMODULE.ko $WORKDIR -rf
+# cp $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak $KDIR/drivers/dma/xilinx/xilinx_dma.c
 cd $WORKDIR
 ls $SUBMODULE.ko
--- a/driver/xilinx_dma/xilinx_dma.c
+++ b/driver/xilinx_dma/xilinx_dma.c
@ -74,9 +74,6 @@
 #define XILINX_DMA_DMACR_CIRC_EN		BIT(1)
 #define XILINX_DMA_DMACR_RUNSTOP		BIT(0)
 #define XILINX_DMA_DMACR_FSYNCSRC_MASK		GENMASK(6, 5)
-#define XILINX_DMA_DMACR_DELAY_MASK		GENMASK(31, 24)
-#define XILINX_DMA_DMACR_FRAME_COUNT_MASK	GENMASK(23, 16)
-#define XILINX_DMA_DMACR_MASTER_MASK		GENMASK(11, 8)

 #define XILINX_DMA_REG_DMASR			0x0004
 #define XILINX_DMA_DMASR_EOL_LATE_ERR		BIT(15)
@ -124,7 +121,7 @@
 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP	BIT(0)

 /* HW specific definitions */
-#define XILINX_DMA_MAX_CHANS_PER_DEVICE	0x2
+#define XILINX_DMA_MAX_CHANS_PER_DEVICE	0x20

 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK	\
 		(XILINX_DMA_DMASR_FRM_CNT_IRQ | \
@ -178,6 +175,18 @@
 #define XILINX_DMA_NUM_DESCS		255
 #define XILINX_DMA_NUM_APP_WORDS	5

+/* Multi-Channel DMA Descriptor offsets*/
+#define XILINX_DMA_MCRX_CDESC(x)	(0x40 + (x-1) * 0x20)
+#define XILINX_DMA_MCRX_TDESC(x)	(0x48 + (x-1) * 0x20)
+
+/* Multi-Channel DMA Masks/Shifts */
+#define XILINX_DMA_BD_HSIZE_MASK	GENMASK(15, 0)
+#define XILINX_DMA_BD_STRIDE_MASK	GENMASK(15, 0)
+#define XILINX_DMA_BD_VSIZE_MASK	GENMASK(31, 19)
+#define XILINX_DMA_BD_TDEST_MASK	GENMASK(4, 0)
+#define XILINX_DMA_BD_STRIDE_SHIFT	0
+#define XILINX_DMA_BD_VSIZE_SHIFT	19
+
 /* AXI CDMA Specific Registers/Offsets */
 #define XILINX_CDMA_REG_SRCADDR		0x18
 #define XILINX_CDMA_REG_DSTADDR		0x20
@ -185,8 +194,6 @@
 /* AXI CDMA Specific Masks */
 #define XILINX_CDMA_CR_SGMODE          BIT(3)

-#define xilinx_prep_dma_addr_t(addr)	\
-	((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
 /**
 * struct xilinx_vdma_desc_hw - Hardware Descriptor
 * @next_desc: Next Descriptor Pointer @0x00
@ -214,8 +221,8 @@ struct xilinx_vdma_desc_hw {
 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 * @buf_addr: Buffer address @0x08
 * @buf_addr_msb: MSB of Buffer address @0x0C
- * @reserved1: Reserved @0x10
- * @reserved2: Reserved @0x14
+ * @mcdma_control: Control field for mcdma @0x10
+ * @vsize_stride: Vsize and Stride field for mcdma @0x14
 * @control: Control field @0x18
 * @status: Status field @0x1C
 * @app: APP Fields @0x20 - 0x30
@ -225,8 +232,8 @@ struct xilinx_axidma_desc_hw {
 	u32 next_desc_msb;
 	u32 buf_addr;
 	u32 buf_addr_msb;
-	u32 reserved1;
-	u32 reserved2;
+	u32 mcdma_control;
+	u32 vsize_stride;
 	u32 control;
 	u32 status;
 	u32 app[XILINX_DMA_NUM_APP_WORDS];
@ -296,16 +303,12 @@ struct xilinx_cdma_tx_segment {
 * @segments: TX segments list
 * @node: Node in the channel descriptors list
 * @cyclic: Check for cyclic transfers.
- * @err: Whether the descriptor has an error.
- * @residue: Residue of the completed descriptor
 */
 struct xilinx_dma_tx_descriptor {
 	struct dma_async_tx_descriptor async_tx;
 	struct list_head segments;
 	struct list_head node;
 	bool cyclic;
-	bool err;
-	u32 residue;
 };

 /**
@ -336,12 +339,14 @@ struct xilinx_dma_tx_descriptor {
 * @desc_pendingcount: Descriptor pending count
 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
 * @desc_submitcount: Descriptor h/w submitted count
+ * @residue: Residue for AXI DMA
 * @seg_v: Statically allocated segments base
 * @seg_p: Physical allocated segments base
 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
 * @cyclic_seg_p: Physical allocated segments base for cyclic dma
 * @start_transfer: Differentiate b/w DMA IP's transfer
 * @stop_transfer: Differentiate b/w DMA IP's quiesce
+ * @tdest: TDEST value for mcdma
 * @has_vflip: S2MM vertical flip
 */
 struct xilinx_dma_chan {
@ -371,12 +376,14 @@ struct xilinx_dma_chan {
 	u32 desc_pendingcount;
 	bool ext_addr;
 	u32 desc_submitcount;
+	u32 residue;
 	struct xilinx_axidma_tx_segment *seg_v;
 	dma_addr_t seg_p;
 	struct xilinx_axidma_tx_segment *cyclic_seg_v;
 	dma_addr_t cyclic_seg_p;
 	void (*start_transfer)(struct xilinx_dma_chan *chan);
 	int (*stop_transfer)(struct xilinx_dma_chan *chan);
+	u16 tdest;
 	bool has_vflip;
 	u32 buf_idx; // each irq this value increase 1. in cyclic mode, we use residue return this idx via device_tx_status/xilinx_dma_tx_status
 };
@ -409,6 +416,7 @@ struct xilinx_dma_config {
 * @common: DMA device structure
 * @chan: Driver specific DMA channel
 * @has_sg: Specifies whether Scatter-Gather is present or not
+ * @mcdma: Specifies whether Multi-Channel is present or not
 * @flush_on_fsync: Flush on frame sync
 * @ext_addr: Indicates 64 bit addressing is supported by dma device
 * @pdev: Platform device structure pointer
@ -428,6 +436,7 @@ struct xilinx_dma_device {
 	struct dma_device common;
 	struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
 	bool has_sg;
+	bool mcdma;
 	u32 flush_on_fsync;
 	bool ext_addr;
 	struct platform_device  *pdev;
@ -607,9 +616,6 @@ xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 	}
 	spin_unlock_irqrestore(&chan->lock, flags);

-	if (!segment)
-		dev_dbg(chan->dev, "Could not find free tx segment\n");
-
 	return segment;
 }

@ -786,51 +792,6 @@ static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
 	}
 }

-/**
- * xilinx_dma_get_residue - Compute residue for a given descriptor
- * @chan: Driver specific dma channel
- * @desc: dma transaction descriptor
- *
- * Return: The number of residue bytes for the descriptor.
- */
-static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
-				  struct xilinx_dma_tx_descriptor *desc)
-{
-	struct xilinx_cdma_tx_segment *cdma_seg;
-	struct xilinx_axidma_tx_segment *axidma_seg;
-	struct xilinx_cdma_desc_hw *cdma_hw;
-	struct xilinx_axidma_desc_hw *axidma_hw;
-	struct list_head *entry;
-	u32 residue = 0;
-
-	/**
-	 * VDMA and simple mode do not support residue reporting, so the
-	 * residue field will always be 0.
-	 */
-	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA || !chan->has_sg)
-		return residue;
-
-	list_for_each(entry, &desc->segments) {
-		if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
-			cdma_seg = list_entry(entry,
-					      struct xilinx_cdma_tx_segment,
-					      node);
-			cdma_hw = &cdma_seg->hw;
-			residue += (cdma_hw->control - cdma_hw->status) &
-				   chan->xdev->max_buffer_len;
-		} else {
-			axidma_seg = list_entry(entry,
-						struct xilinx_axidma_tx_segment,
-						node);
-			axidma_hw = &axidma_seg->hw;
-			residue += (axidma_hw->control - axidma_hw->status) &
-				   chan->xdev->max_buffer_len;
-		}
-	}
-
-	return residue;
-}
-
 /**
 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
 * @chan: Driver specific dma channel
@ -865,7 +826,7 @@ static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
 	spin_lock_irqsave(&chan->lock, flags);

 	list_for_each_entry_safe(desc, next, &chan->done_list, node) {
-		struct dmaengine_result result;
+		struct dmaengine_desc_callback cb;

 		if (desc->cyclic) {
 			xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
@ -875,21 +836,13 @@ static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
 		/* Remove from the list of running transactions */
 		list_del(&desc->node);

-		if (unlikely(desc->err)) {
-			if (chan->direction == DMA_DEV_TO_MEM)
-				result.result = DMA_TRANS_READ_FAILED;
-			else
-				result.result = DMA_TRANS_WRITE_FAILED;
-		} else {
-			result.result = DMA_TRANS_NOERROR;
-		}
-
-		result.residue = desc->residue;
-
 		/* Run the link descriptor callback function */
-		spin_unlock_irqrestore(&chan->lock, flags);
-		dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
-		spin_lock_irqsave(&chan->lock, flags);
+		dmaengine_desc_get_callback(&desc->async_tx, &cb);
+		if (dmaengine_desc_callback_valid(&cb)) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			dmaengine_desc_callback_invoke(&cb, NULL);
+			spin_lock_irqsave(&chan->lock, flags);
+		}

 		/* Run any dependencies, then free the descriptor */
 		dma_run_dependencies(&desc->async_tx);
@ -1025,25 +978,36 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
 {
 	struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
 	struct xilinx_dma_tx_descriptor *desc;
+	struct xilinx_axidma_tx_segment *segment;
+	struct xilinx_axidma_desc_hw *hw;
 	enum dma_status ret;
 	unsigned long flags;
+	u32 residue = 0;

 	ret = dma_cookie_status(dchan, cookie, txstate);
 	if (ret == DMA_COMPLETE || !txstate)
 		return ret;

-	spin_lock_irqsave(&chan->lock, flags);
+	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+		spin_lock_irqsave(&chan->lock, flags);

-	desc = list_last_entry(&chan->active_list,
-			       struct xilinx_dma_tx_descriptor, node);
-	desc->residue = xilinx_dma_get_residue(chan, desc);
+		desc = list_last_entry(&chan->active_list,
+				       struct xilinx_dma_tx_descriptor, node);
+		if (chan->has_sg) {
+			list_for_each_entry(segment, &desc->segments, node) {
+				hw = &segment->hw;
+				residue += (hw->control - hw->status) &
+					   chan->xdev->max_buffer_len;
+			}
+		}
+		spin_unlock_irqrestore(&chan->lock, flags);

-	spin_unlock_irqrestore(&chan->lock, flags);
-
-	if (chan->cyclic)
-		dma_set_residue(txstate, chan->buf_idx);
-	else
-		dma_set_residue(txstate, desc->residue);
+		chan->residue = residue;
+		if (chan->cyclic)
+			dma_set_residue(txstate, chan->buf_idx);
+		else
+			dma_set_residue(txstate, chan->residue);
+	}

 	return ret;
 }
@ -1062,9 +1026,8 @@ static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)

 	/* Wait for the hardware to halt */
 	return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
-				       val | (XILINX_DMA_DMASR_IDLE |
-					      XILINX_DMA_DMASR_HALTED),
-				       0, XILINX_DMA_LOOP_COUNT);
+				       val & XILINX_DMA_DMASR_HALTED, 0,
+				       XILINX_DMA_LOOP_COUNT);
 }

 /**
@ -1292,10 +1255,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)

 		hw = &segment->hw;

-		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
-			     xilinx_prep_dma_addr_t(hw->src_addr));
-		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
-			     xilinx_prep_dma_addr_t(hw->dest_addr));
+		xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)
+			     ((u64)hw->src_addr_msb << 32 | hw->src_addr));
+		xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)
+			     ((u64)hw->dest_addr_msb << 32 | hw->dest_addr));

 		/* Start the transfer */
 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
@ -1342,23 +1305,53 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
 	}

-	if (chan->has_sg)
+	if (chan->has_sg && !chan->xdev->mcdma)
 		xilinx_write(chan, XILINX_DMA_REG_CURDESC,
 			     head_desc->async_tx.phys);

+	if (chan->has_sg && chan->xdev->mcdma) {
+		if (chan->direction == DMA_MEM_TO_DEV) {
+			dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
+				       head_desc->async_tx.phys);
+		} else {
+			if (!chan->tdest) {
+				dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
+				       head_desc->async_tx.phys);
+			} else {
+				dma_ctrl_write(chan,
+					XILINX_DMA_MCRX_CDESC(chan->tdest),
+				       head_desc->async_tx.phys);
+			}
+		}
+	}
+
 	xilinx_dma_start(chan);

 	if (chan->err)
 		return;

 	/* Start the transfer */
-	if (chan->has_sg) {
+	if (chan->has_sg && !chan->xdev->mcdma) {
 		if (chan->cyclic)
 			xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
 				     chan->cyclic_seg_v->phys);
 		else
 			xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
 				     tail_segment->phys);
+	} else if (chan->has_sg && chan->xdev->mcdma) {
+		if (chan->direction == DMA_MEM_TO_DEV) {
+			dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
+			       tail_segment->phys);
+		} else {
+			if (!chan->tdest) {
+				dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
+					       tail_segment->phys);
+			} else {
+				dma_ctrl_write(chan,
+					XILINX_DMA_MCRX_TDESC(chan->tdest),
+					tail_segment->phys);
+			}
+		}
 	} else {
 		struct xilinx_axidma_tx_segment *segment;
 		struct xilinx_axidma_desc_hw *hw;
@ -1368,8 +1361,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 					   node);
 		hw = &segment->hw;

-		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
-			     xilinx_prep_dma_addr_t(hw->buf_addr));
+		xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);

 		/* Start the transfer */
 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
@ -1410,9 +1402,6 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
 		return;

 	list_for_each_entry_safe(desc, next, &chan->active_list, node) {
-		desc->residue = xilinx_dma_get_residue(chan, desc);
-		desc->err = chan->err;
-
 		list_del(&desc->node);
 		if (!desc->cyclic)
 			dma_cookie_complete(&desc->async_tx);
@ -1447,7 +1436,6 @@ static int xilinx_dma_reset(struct xilinx_dma_chan *chan)

 	chan->err = false;
 	chan->idle = true;
-	chan->desc_pendingcount = 0;
 	chan->desc_submitcount = 0;

 	return err;
@ -1585,12 +1573,7 @@ static void append_desc_queue(struct xilinx_dma_chan *chan,
 	 */
 append:
 	list_add_tail(&desc->node, &chan->pending_list);
-	/*
-	 * In CDMA each segment is considered as a descriptor, so increment
-	 * pending count in prep_slave_* implementation.
-	 */
-	if (chan->xdev->dma_config->dmatype != XDMA_TYPE_CDMA)
-		chan->desc_pendingcount++;
+	chan->desc_pendingcount++;

 	if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
 	    && unlikely(chan->desc_pendingcount > chan->num_frms)) {
@ -1770,7 +1753,6 @@ xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,

 	/* Insert the segment into the descriptor segments list. */
 	list_add_tail(&segment->node, &desc->segments);
-	chan->desc_pendingcount++;

 	desc->async_tx.phys = segment->phys;
 	hw->next_desc = segment->phys;
@ -1855,7 +1837,6 @@ static struct dma_async_tx_descriptor *xilinx_cdma_prep_sg(
 		dst_avail -= len;
 		src_avail -= len;
 		list_add_tail(&segment->node, &desc->segments);
-		chan->desc_pendingcount++;

 fetch:
 		/* Fetch the next dst scatterlist entry */
@ -2101,6 +2082,90 @@ error:
 	return NULL;
 }

+/**
+ * xilinx_dma_prep_interleaved - prepare a descriptor for a
+ *	DMA_SLAVE transaction
+ * @dchan: DMA channel
+ * @xt: Interleaved template pointer
+ * @flags: transfer ack flags
+ *
+ * Return: Async transaction descriptor on success and NULL on failure
+ */
+static struct dma_async_tx_descriptor *
+xilinx_dma_prep_interleaved(struct dma_chan *dchan,
+				 struct dma_interleaved_template *xt,
+				 unsigned long flags)
+{
+	struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+	struct xilinx_dma_tx_descriptor *desc;
+	struct xilinx_axidma_tx_segment *segment;
+	struct xilinx_axidma_desc_hw *hw;
+
+	if (!is_slave_direction(xt->dir))
+		return NULL;
+
+	if (!xt->numf || !xt->sgl[0].size)
+		return NULL;
+
+	if (xt->frame_size != 1)
+		return NULL;
+
+	/* Allocate a transaction descriptor. */
+	desc = xilinx_dma_alloc_tx_descriptor(chan);
+	if (!desc)
+		return NULL;
+
+	chan->direction = xt->dir;
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
+	desc->async_tx.tx_submit = xilinx_dma_tx_submit;
+
+	/* Get a free segment */
+	segment = xilinx_axidma_alloc_tx_segment(chan);
+	if (!segment)
+		goto error;
+
+	hw = &segment->hw;
+
+	/* Fill in the descriptor */
+	if (xt->dir != DMA_MEM_TO_DEV)
+		hw->buf_addr = xt->dst_start;
+	else
+		hw->buf_addr = xt->src_start;
+
+	hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
+	hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
+			    XILINX_DMA_BD_VSIZE_MASK;
+	hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
+			    XILINX_DMA_BD_STRIDE_MASK;
+	hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
+
+	/*
+	 * Insert the segment into the descriptor segments
+	 * list.
+	 */
+	list_add_tail(&segment->node, &desc->segments);
+
+
+	segment = list_first_entry(&desc->segments,
+				   struct xilinx_axidma_tx_segment, node);
+	desc->async_tx.phys = segment->phys;
+
+	/* For the last DMA_MEM_TO_DEV transfer, set EOP */
+	if (xt->dir == DMA_MEM_TO_DEV) {
+		segment->hw.control |= XILINX_DMA_BD_SOP;
+		segment = list_last_entry(&desc->segments,
+					  struct xilinx_axidma_tx_segment,
+					  node);
+		segment->hw.control |= XILINX_DMA_BD_EOP;
+	}
+
+	return &desc->async_tx;
+
+error:
+	xilinx_dma_free_tx_descriptor(chan, desc);
+	return NULL;
+}
+
 /**
 * xilinx_dma_terminate_all - Halt the channel and free descriptors
 * @dchan: Driver specific DMA Channel pointer
@ -2173,10 +2238,8 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
 	chan->config.gen_lock = cfg->gen_lock;
 	chan->config.master = cfg->master;

-	dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
 	if (cfg->gen_lock && chan->genlock) {
 		dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
-		dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
 		dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
 	}

@ -2192,13 +2255,11 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
 	chan->config.delay = cfg->delay;

 	if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
-		dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
 		dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
 		chan->config.coalesc = cfg->coalesc;
 	}

 	if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
-		dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
 		dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
 		chan->config.delay = cfg->delay;
 	}
@ -2490,6 +2551,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
 	    of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
 		chan->direction = DMA_MEM_TO_DEV;
 		chan->id = chan_id;
+		chan->tdest = chan_id;
 		xdev->common.directions = BIT(DMA_MEM_TO_DEV);

 		chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
@ -2507,6 +2569,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
 					   "xlnx,axi-dma-s2mm-channel")) {
 		chan->direction = DMA_DEV_TO_MEM;
 		chan->id = chan_id;
+		chan->tdest = chan_id - xdev->nr_channels;
 		xdev->common.directions |= BIT(DMA_DEV_TO_MEM);
 		chan->has_vflip = of_property_read_bool(node,
 					"xlnx,enable-vert-flip");
@ -2586,7 +2649,11 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
 				    struct device_node *node)
 {
-	int i, nr_channels = 1;
+	int ret, i, nr_channels = 1;
+
+	ret = of_property_read_u32(node, "dma-channels", &nr_channels);
+	if ((ret < 0) && xdev->mcdma)
+		dev_warn(xdev->dev, "missing dma-channels property\n");

 	for (i = 0; i < nr_channels; i++)
 		xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
@ -2688,6 +2755,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 	xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);

 	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+		xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
 		if (!of_property_read_u32(node, "xlnx,sg-length-width",
 					  &len_width)) {
 			if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
@ -2754,7 +2822,9 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 		xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
 		xdev->common.device_prep_dma_cyclic =
 					  xilinx_dma_prep_dma_cyclic;
-		/* Residue calculation is supported by only AXI DMA and CDMA */
+		xdev->common.device_prep_interleaved_dma =
+					xilinx_dma_prep_interleaved;
+		/* Residue calculation is supported by only AXI DMA */
 		xdev->common.residue_granularity =
 					  DMA_RESIDUE_GRANULARITY_SEGMENT;
 	} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
@ -2762,9 +2832,6 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 		dma_cap_set(DMA_SG, xdev->common.cap_mask);
 		xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
 		xdev->common.device_prep_dma_sg = xilinx_cdma_prep_sg;
-		/* Residue calculation is supported by only AXI DMA and CDMA */
-		xdev->common.residue_granularity =
-					  DMA_RESIDUE_GRANULARITY_SEGMENT;
 	} else {
 		xdev->common.device_prep_interleaved_dma =
 				xilinx_vdma_dma_prep_interleaved;
@ -2850,6 +2917,6 @@ static struct platform_driver xilinx_vdma_driver = {

 module_platform_driver(xilinx_vdma_driver);

-MODULE_AUTHOR("Xilinx and Xianjun Jiao");
+MODULE_AUTHOR("Xilinx, Inc. and Xianjun Jiao");
 MODULE_DESCRIPTION("Xilinx VDMA driver");
 MODULE_LICENSE("GPL v2");
--- a/driver/xpu/Makefile
+++ b/driver/xpu/Makefile
@ -3,7 +3,8 @@
 obj-m += xpu.o

 all:
-	make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+	make -C $(KDIR) M=$(PWD) modules
+	# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-

 clean:
 	rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
--- a/driver/xpu/xpu.c
+++ b/driver/xpu/xpu.c
@ -343,12 +343,12 @@ static inline u32 hw_init(enum xpu_mode mode){
 	//xpu_api->XPU_REG_ACK_FC_FILTER_write((3<<(2+16))|(2<<2)); // low 16 bits target FC 16 bits; high 16 bits -- mask

 	// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel
-	// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*200)<<16) | 200 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time.  let's add 2us for those device that is really "slow"!
-	// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 1200 ); // +6 = 16us for 5GHz
+	// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time.  let's add 2us for those device that is really "slow"!
+	// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz

 	//xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
 	
-	xpu_api->XPU_REG_BB_RF_DELAY_write(975);
+	xpu_api->XPU_REG_BB_RF_DELAY_write(49);

 	xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write(50000-1); // total 50ms
 	xpu_api->XPU_REG_SLICE_COUNT_START0_write(0); //start 0ms
@ -388,11 +388,11 @@ static inline u32 hw_init(enum xpu_mode mode){
 	//xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
 	xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority

-	// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
-	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030)<<16)|0 );//now our tx send out I/Q immediately
+	// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
+	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately

-	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200 + 300)<<16) | 200 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
-	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200 + 300)<<16) | 200 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)

 	printk("%s hw_init err %d\n", xpu_compatible_str, err);
 	return(err);
--- a/kernel_boot/boards/adrv9361z7035/devicetree.dts
+++ b/kernel_boot/boards/adrv9361z7035/devicetree.dts
@ -217,6 +217,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -427,7 +428,7 @@
 			#size-cells = <0x0>;
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -435,11 +436,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 			disable-wp;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -447,10 +447,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
@ -460,6 +460,7 @@
 			phandle = <0x8>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -668,8 +669,8 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c400000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 57 4>;
-			clocks = <0x2 0xf 0xf>;
+			interrupts = <0x0 0x39 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0xb>;
 			phandle = <0xb>;

@ -683,7 +684,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -692,8 +692,8 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c420000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 56 4>;
-			clocks = <0x2 0xf 0xf>;
+			interrupts = <0x0 0x38 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0xd>;
 			phandle = <0xd>;

@ -707,8 +707,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -855,6 +853,11 @@
 			compatible = "mathworks,mwipcore-axi4lite-v1.00";
 			reg = <0x43c00000 0xffff>;
 		};
+
+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};
 	};

 	leds {
--- a/kernel_boot/boards/adrv9361z7035_fmc/devicetree.dts
+++ b/kernel_boot/boards/adrv9361z7035_fmc/devicetree.dts
@ -217,6 +217,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -295,8 +296,8 @@
 				reset-gpios = <0x6 0x64 0x0>;
 				enable-gpios = <0x6 0x65 0x0>;
 				txnrx-gpios = <0x6 0x66 0x0>;
-				linux,phandle = <0x11>;
-				phandle = <0x11>;
+				linux,phandle = <0x10>;
+				phandle = <0x10>;
 			};

 			ad9517@1 {
@ -441,24 +442,22 @@
 			phy-handle = <0x9>;
 			phy-mode = "gmii";

-			gmiitorgmii@8 {
-				compatible = "xlnx,gmii-to-rgmii-1.0";
-				reg = <0x8>;
-				phy-handle = <0xa>;
-				linux,phandle = <0x9>;
-				phandle = <0x9>;
-			};
-
 			phy@1 {
 				device_type = "ethernet-phy";
 				reg = <0x1>;
 				marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
-				linux,phandle = <0xa>;
-				phandle = <0xa>;
+				linux,phandle = <0x9>;
+				phandle = <0x9>;
+			};
+
+			gmiitorgmii@8 {
+				compatible = "xlnx,gmii-to-rgmii-1.0";
+				reg = <0x8>;
+				phy-handle = <0x9>;
 			};
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -466,11 +465,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 			disable-wp;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -478,19 +476,20 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 			reg = <0xf8000000 0x1000>;
 			ranges;
-			linux,phandle = <0xb>;
-			phandle = <0xb>;
+			linux,phandle = <0xa>;
+			phandle = <0xa>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -505,13 +504,13 @@
 				compatible = "xlnx,zynq-reset";
 				reg = <0x200 0x48>;
 				#reset-cells = <0x1>;
-				syscon = <0xb>;
+				syscon = <0xa>;
 			};

 			pinctrl@700 {
 				compatible = "xlnx,pinctrl-zynq";
 				reg = <0x700 0x200>;
-				syscon = <0xb>;
+				syscon = <0xa>;
 			};
 		};

@ -526,8 +525,8 @@
 			#dma-requests = <0x4>;
 			clocks = <0x2 0x1b>;
 			clock-names = "apb_pclk";
-			linux,phandle = <0x16>;
-			phandle = <0x16>;
+			linux,phandle = <0x15>;
+			phandle = <0x15>;
 		};

 		devcfg@f8007000 {
@ -537,7 +536,7 @@
 			reg = <0xf8007000 0x100>;
 			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
 			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
-			syscon = <0xb>;
+			syscon = <0xa>;
 			linux,phandle = <0x4>;
 			phandle = <0x4>;
 		};
@ -634,8 +633,8 @@
 			clock-frequency = <0x2625a00>;
 			clock-accuracy = <0x30d40>;
 			clock-output-names = "XO_40MHz";
-			linux,phandle = <0xc>;
-			phandle = <0xc>;
+			linux,phandle = <0xb>;
+			phandle = <0xb>;
 		};

 		clock@2 {
@ -643,8 +642,8 @@
 			compatible = "fixed-clock";
 			clock-frequency = <0x16e3600>;
 			clock-output-names = "24MHz";
-			linux,phandle = <0xd>;
-			phandle = <0xd>;
+			linux,phandle = <0xc>;
+			phandle = <0xc>;
 		};

 		clock@3 {
@ -660,15 +659,15 @@
 			compatible = "fixed-clock";
 			#clock-cells = <0x0>;
 			clock-frequency = <0xbb8000>;
-			linux,phandle = <0xf>;
-			phandle = <0xf>;
+			linux,phandle = <0xe>;
+			phandle = <0xe>;
 		};
 	};

 	ad9361-refclk-gpio-gate@0 {
 		#clock-cells = <0x0>;
 		compatible = "gpio-gate-clock";
-		clocks = <0xc>;
+		clocks = <0xb>;
 		enable-gpios = <0x6 0x69 0x0>;
 		clk-set-rate-parent-enable;
 		clock-output-names = "ad9361_ext_refclk";
@ -679,7 +678,7 @@
 	usb-ulpe-gpio-gate@0 {
 		#clock-cells = <0x0>;
 		compatible = "gpio-gate-clock";
-		clocks = <0xd>;
+		clocks = <0xc>;
 		enable-gpios = <0x6 0x9 0x1>;
 	};

@ -738,8 +737,8 @@
 						adi,input-justification = "left";
 						adi,clock-delay = <0x0>;
 						#sound-dai-cells = <0x0>;
-						linux,phandle = <0x18>;
-						phandle = <0x18>;
+						linux,phandle = <0x17>;
+						phandle = <0x17>;

 						ports {
 							#address-cells = <0x1>;
@ -749,9 +748,9 @@
 								reg = <0x0>;

 								endpoint {
-									remote-endpoint = <0xe>;
-									linux,phandle = <0x15>;
-									phandle = <0x15>;
+									remote-endpoint = <0xd>;
+									linux,phandle = <0x14>;
+									phandle = <0x14>;
 								};
 							};

@ -770,11 +769,11 @@
 					adau1761@3b {
 						compatible = "adi,adau1761";
 						reg = <0x3b>;
-						clocks = <0xf>;
+						clocks = <0xe>;
 						clock-names = "mclk";
 						#sound-dai-cells = <0x0>;
-						linux,phandle = <0x1a>;
-						phandle = <0x1a>;
+						linux,phandle = <0x19>;
+						phandle = <0x19>;
 					};
 				};

@ -818,10 +817,10 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c400000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 57 4>;
-			clocks = <0x2 0xf 0xf>;
-			linux,phandle = <0x10>;
-			phandle = <0x10>;
+			interrupts = <0x0 0x39 0x0>;
+			clocks = <0x2 0x10>;
+			linux,phandle = <0xf>;
+			phandle = <0xf>;

 			adi,channels {
 				#size-cells = <0x0>;
@ -833,7 +832,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -842,10 +840,10 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c420000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 56 4>;
-			clocks = <0x2 0xf 0xf>;
-			linux,phandle = <0x12>;
-			phandle = <0x12>;
+			interrupts = <0x0 0x38 0x0>;
+			clocks = <0x2 0x10>;
+			linux,phandle = <0x11>;
+			phandle = <0x11>;

 			adi,channels {
 				#size-cells = <0x0>;
@ -857,8 +855,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -987,17 +983,17 @@
 		cf-ad9361-lpc@79020000 {
 			compatible = "adi,axi-ad9361-6.00.a";
 			reg = <0x79020000 0x6000>;
-			dmas = <0x10 0x0>;
+			dmas = <0xf 0x0>;
 			dma-names = "rx";
-			spibus-connected = <0x11>;
+			spibus-connected = <0x10>;
 		};

 		cf-ad9361-dds-core-lpc@79024000 {
 			compatible = "adi,axi-ad9361-dds-6.00.a";
 			reg = <0x79024000 0x1000>;
-			clocks = <0x11 0xd>;
+			clocks = <0x10 0xd>;
 			clock-names = "sampl_clk";
-			dmas = <0x12 0x0>;
+			dmas = <0x11 0x0>;
 			dma-names = "tx";
 		};

@ -1006,31 +1002,31 @@
 			reg = <0x43c00000 0xffff>;
 		};

-		axivdma@43000000 {
-			compatible = "xlnx,axi-vdma-1.00.a";
-			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_mm2s_aclk";
-			clocks = <2 15>, <2 15>, <2 15>;
-			interrupt-names = "mm2s_introut";
-			interrupt-parent = <1>;
-			interrupts = <0 59 4>;
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			#dma-cells = <0x1>;
-			#dma-channels = <0x1>;
-			reg = <0x43000000 0x1000>;
-			xlnx,addrwidth = <0x20>;
-			xlnx,flush-fsync = <0x1>;
-			xlnx,num-fstores = <0x3>;
-			linux,phandle = <0x13>;
-			phandle = <0x13>;
+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};

-			dma-channel@43000000 {
-				compatible = "xlnx,axi-vdma-mm2s-channel";
-				interrupts = <0 59 4>;
-				xlnx,datawidth = <0x40>;
-				xlnx,device-id = <0x0>;
-				xlnx,genlock-mode ;
-				xlnx,include-dre = <0x0>;
+		dma@43000000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x43000000 0x10000>;
+			#dma-cells = <0x1>;
+			interrupts = <0x0 0x3b 0x0>;
+			clocks = <0x2 0x10>;
+			linux,phandle = <0x12>;
+			phandle = <0x12>;
+
+			adi,channels {
+				#size-cells = <0x0>;
+				#address-cells = <0x1>;
+
+				dma-channel@0 {
+					reg = <0x0>;
+					adi,source-bus-width = <0x40>;
+					adi,source-bus-type = <0x0>;
+					adi,destination-bus-width = <0x40>;
+					adi,destination-bus-type = <0x1>;
+				};
 			};
 		};

@ -1039,23 +1035,23 @@
 			reg = <0x79000000 0x10000>;
 			#clock-cells = <0x0>;
 			clocks = <0x2 0x10>;
-			linux,phandle = <0x14>;
-			phandle = <0x14>;
+			linux,phandle = <0x13>;
+			phandle = <0x13>;
 		};

 		axi_hdmi@70e00000 {
 			compatible = "adi,axi-hdmi-tx-1.00.a";
 			reg = <0x70e00000 0x10000>;
-			dmas = <0x13 0x0>;
+			dmas = <0x12 0x0>;
 			dma-names = "video";
-			clocks = <0x14>;
+			clocks = <0x13>;

 			port {

 				endpoint {
-					remote-endpoint = <0x15>;
-					linux,phandle = <0xe>;
-					phandle = <0xe>;
+					remote-endpoint = <0x14>;
+					linux,phandle = <0xd>;
+					phandle = <0xd>;
 				};
 			};
 		};
@ -1063,25 +1059,25 @@
 		axi-spdif-tx@75c00000 {
 			compatible = "adi,axi-spdif-tx-1.00.a";
 			reg = <0x75c00000 0x1000>;
-			dmas = <0x16 0x0>;
+			dmas = <0x15 0x0>;
 			dma-names = "tx";
-			clocks = <0x2 0xf 0xf>;
+			clocks = <0x2 0xf 0xe>;
 			clock-names = "axi", "ref";
 			#sound-dai-cells = <0x0>;
-			linux,phandle = <0x17>;
-			phandle = <0x17>;
+			linux,phandle = <0x16>;
+			phandle = <0x16>;
 		};

 		axi-i2s@77600000 {
 			compatible = "adi,axi-i2s-1.00.a";
 			reg = <0x77600000 0x1000>;
-			dmas = <0x16 0x1 0x16 0x2>;
+			dmas = <0x15 0x1 0x15 0x2>;
 			dma-names = "tx", "rx";
-			clocks = <0x2 0xf 0xf>;
+			clocks = <0x2 0xf 0xe>;
 			clock-names = "axi", "ref";
 			#sound-dai-cells = <0x0>;
-			linux,phandle = <0x19>;
-			phandle = <0x19>;
+			linux,phandle = <0x18>;
+			phandle = <0x18>;
 		};
 	};

@ -1095,13 +1091,13 @@
 			format = "spdif";

 			cpu {
-				sound-dai = <0x17>;
+				sound-dai = <0x16>;
 				frame-master;
 				bitclock-master;
 			};

 			codec {
-				sound-dai = <0x18>;
+				sound-dai = <0x17>;
 			};
 		};
 	};
@ -1116,13 +1112,13 @@
 			format = "i2s";

 			cpu {
-				sound-dai = <0x19>;
+				sound-dai = <0x18>;
 				frame-master;
 				bitclock-master;
 			};

 			codec {
-				sound-dai = <0x1a>;
+				sound-dai = <0x19>;
 			};
 		};
 	};
--- a/kernel_boot/boards/adrv9364z7020/devicetree.dts
+++ b/kernel_boot/boards/adrv9364z7020/devicetree.dts
@ -217,6 +217,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -427,7 +428,7 @@
 			#size-cells = <0x0>;
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -435,11 +436,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 			disable-wp;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -447,10 +447,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
@ -460,6 +460,7 @@
 			phandle = <0x8>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -672,7 +673,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -696,8 +696,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -844,6 +842,11 @@
 			compatible = "mathworks,mwipcore-axi4lite-v1.00";
 			reg = <0x43c00000 0xffff>;
 		};
+
+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};
 	};

 	leds {
--- a/kernel_boot/boards/zc702_fmcs2/devicetree.dts
+++ b/kernel_boot/boards/zc702_fmcs2/devicetree.dts
@ -192,9 +192,6 @@
 			#size-cells = <0x0>;

 			ad9361-phy@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
-				#clock-cells = <0x1>;
 				compatible = "adi,ad9361";
 				reg = <0x0>;
 				spi-cpha;
@ -202,6 +199,7 @@
 				clocks = <0x5 0x0>;
 				clock-names = "ad9361_ext_refclk";
 				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+				#clock-cells = <0x1>;
 				adi,digital-interface-tune-skip-mode = <0x0>;
 				adi,pp-tx-swap-enable;
 				adi,pp-rx-swap-enable;
@ -217,6 +215,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -312,8 +311,6 @@
 			#size-cells = <0x0>;

 			adf4351-udc-tx-pmod@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x0>;
 				spi-max-frequency = <0x989680>;
@ -330,8 +327,6 @@
 			};

 			adf4351-udc-rx-pmod@1 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x1>;
 				spi-max-frequency = <0x989680>;
@ -456,7 +451,7 @@
 			#size-cells = <0x0>;
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -464,10 +459,9 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -475,10 +469,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
@ -488,6 +482,7 @@
 			phandle = <0x9>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -813,22 +808,26 @@
 			};
 		};
 /*
-		axivdma@43000000 {
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
+		dma@43000000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x43000000 0x10000>;
 			#dma-cells = <0x1>;
-			compatible = "xlnx,axi-vdma-1.00.a";
-			reg = <0x43000000 0x1000>;
-			xlnx,num-fstores = <0x3>;
+			interrupts = <0x0 0x3b 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0xb>;
 			phandle = <0xb>;

-			dma-channel@7e200000 {
-				compatible = "xlnx,axi-vdma-mm2s-channel";
-				interrupts = <0x0 0x3b 0x4>;
-				xlnx,datawidth = <0x40>;
-				xlnx,genlock-mode = <0x0>;
-				xlnx,include-dre = <0x0>;
+			adi,channels {
+				#size-cells = <0x0>;
+				#address-cells = <0x1>;
+
+				dma-channel@0 {
+					reg = <0x0>;
+					adi,source-bus-width = <0x40>;
+					adi,source-bus-type = <0x0>;
+					adi,destination-bus-width = <0x40>;
+					adi,destination-bus-type = <0x1>;
+				};
 			};
 		};

@ -870,6 +869,11 @@
 			phandle = <0x13>;
 		};
 */
+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};
+
 		dma@7c400000 {
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c400000 0x10000>;
@ -889,7 +893,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -913,8 +916,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -1090,19 +1091,19 @@
 	clocks {

 		clock@0 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x2625a00>;
 			clock-output-names = "ad9361_ext_refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x5>;
 			phandle = <0x5>;
 		};

 		clock@1 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x17d7840>;
 			clock-output-names = "refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x7>;
 			phandle = <0x7>;
 		};
--- a/kernel_boot/boards/zc706_fmcs2/devicetree.dts
+++ b/kernel_boot/boards/zc706_fmcs2/devicetree.dts
@ -192,9 +192,6 @@
 			#size-cells = <0x0>;

 			ad9361-phy@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
-				#clock-cells = <0x1>;
 				compatible = "adi,ad9361";
 				reg = <0x0>;
 				spi-cpha;
@ -202,6 +199,7 @@
 				clocks = <0x5 0x0>;
 				clock-names = "ad9361_ext_refclk";
 				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+				#clock-cells = <0x1>;
 				adi,digital-interface-tune-skip-mode = <0x0>;
 				adi,pp-tx-swap-enable;
 				adi,pp-rx-swap-enable;
@ -217,6 +215,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -312,8 +311,6 @@
 			#size-cells = <0x0>;

 			adf4351-udc-tx-pmod@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x0>;
 				spi-max-frequency = <0x989680>;
@ -330,8 +327,6 @@
 			};

 			adf4351-udc-rx-pmod@1 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x1>;
 				spi-max-frequency = <0x989680>;
@ -457,7 +452,7 @@
 			#size-cells = <0x0>;
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -465,10 +460,9 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -476,10 +470,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
@ -489,6 +483,7 @@
 			phandle = <0x9>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -808,30 +803,26 @@
 			};
 		};

-		axivdma@43000000 {
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
+		dma@43000000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x43000000 0x10000>;
 			#dma-cells = <0x1>;
-			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_mm2s_aclk";
-			clocks = <2 15>, <2 15>, <2 15>;
-			compatible = "xlnx,axi-vdma-1.00.a";
-			interrupt-names = "mm2s_introut";
-			interrupt-parent = <1>;
-			interrupts = <0 59 4>;
-			reg = <0x43000000 0x1000>;
-			xlnx,addrwidth = <0x20>;
-			xlnx,flush-fsync = <0x1>;
-			xlnx,num-fstores = <0x3>;
+			interrupts = <0x0 0x3b 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0xb>;
 			phandle = <0xb>;

-			dma-channel@43000000 {
-				compatible = "xlnx,axi-vdma-mm2s-channel";
-				interrupts = <0 59 4>;
-				xlnx,datawidth = <0x40>;
-				xlnx,device-id = <0x0>;
-				xlnx,genlock-mode ;
-				xlnx,include-dre = <0x0>;
+			adi,channels {
+				#size-cells = <0x0>;
+				#address-cells = <0x1>;
+
+				dma-channel@0 {
+					reg = <0x0>;
+					adi,source-bus-width = <0x40>;
+					adi,source-bus-type = <0x0>;
+					adi,destination-bus-width = <0x40>;
+					adi,destination-bus-type = <0x1>;
+				};
 			};
 		};

@ -874,12 +865,17 @@
 			phandle = <0x13>;
 		};

+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};
+
 		dma@7c400000 {
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c400000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 57 4>;
-			clocks = <0x2 0xf 0xf>;
+			interrupts = <0x0 0x39 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0x10>;
 			phandle = <0x10>;

@ -893,7 +889,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -902,8 +897,8 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x7c420000 0x10000>;
 			#dma-cells = <0x1>;
-			interrupts = <0 56 4>;
-			clocks = <0x2 0xf 0xf>;
+			interrupts = <0x0 0x38 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0x12>;
 			phandle = <0x12>;

@ -917,8 +912,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -1059,8 +1052,6 @@
 			clock-names = "sampl_clk";
 			dmas = <0x12 0x0>;
 			dma-names = "tx";
-			adi,axi-dds-rate = <0x1>;
-			adi,axi-dds-1-rf-channel;
 		};

 		mwipcore@43c00000 {
@ -1101,19 +1092,19 @@
 	clocks {

 		clock@0 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x2625a00>;
 			clock-output-names = "ad9361_ext_refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x5>;
 			phandle = <0x5>;
 		};

 		clock@1 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x17d7840>;
 			clock-output-names = "refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x7>;
 			phandle = <0x7>;
 		};
--- a/kernel_boot/boards/zcu102_fmcs2/bl31.elf
+++ b/kernel_boot/boards/zcu102_fmcs2/bl31.elf
--- a/kernel_boot/boards/zcu102_fmcs2/system.dts
+++ b/kernel_boot/boards/zcu102_fmcs2/system.dts
--- a/kernel_boot/boards/zcu102_fmcs2/u-boot-zcu.elf
+++ b/kernel_boot/boards/zcu102_fmcs2/u-boot-zcu.elf
--- a/kernel_boot/boards/zed_fmcs2/devicetree.dts
+++ b/kernel_boot/boards/zed_fmcs2/devicetree.dts
@ -192,9 +192,6 @@
 			#size-cells = <0x0>;

 			ad9361-phy@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
-				#clock-cells = <0x1>;
 				compatible = "adi,ad9361";
 				reg = <0x0>;
 				spi-cpha;
@ -202,6 +199,7 @@
 				clocks = <0x5 0x0>;
 				clock-names = "ad9361_ext_refclk";
 				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+				#clock-cells = <0x1>;
 				adi,digital-interface-tune-skip-mode = <0x0>;
 				adi,pp-tx-swap-enable;
 				adi,pp-rx-swap-enable;
@ -217,6 +215,7 @@
 				adi,rx-rf-port-input-select = <0x0>;
 				adi,tx-rf-port-input-select = <0x0>;
 				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
 				adi,rf-rx-bandwidth-hz = <0x112a880>;
 				adi,rf-tx-bandwidth-hz = <0x112a880>;
 				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
@ -312,8 +311,6 @@
 			#size-cells = <0x0>;

 			adf4351-udc-tx-pmod@0 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x0>;
 				spi-max-frequency = <0x989680>;
@ -330,8 +327,6 @@
 			};

 			adf4351-udc-rx-pmod@1 {
-				#address-cells = <0x1>;
-				#size-cells = <0x0>;
 				compatible = "adi,adf4351";
 				reg = <0x1>;
 				spi-max-frequency = <0x989680>;
@ -456,7 +451,7 @@
 			#size-cells = <0x0>;
 		};

-		sdhci@e0100000 {
+		mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "okay";
 			clock-names = "clk_xin", "clk_ahb";
@ -464,10 +459,9 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x18 0x4>;
 			reg = <0xe0100000 0x1000>;
-			broken-adma2;
 		};

-		sdhci@e0101000 {
+		mmc@e0101000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			clock-names = "clk_xin", "clk_ahb";
@ -475,10 +469,10 @@
 			interrupt-parent = <0x1>;
 			interrupts = <0x0 0x2f 0x4>;
 			reg = <0xe0101000 0x1000>;
-			broken-adma2;
 		};

 		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
@ -488,6 +482,7 @@
 			phandle = <0x9>;

 			clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <0x1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0xf>;
@ -685,23 +680,26 @@
 		};

 /*
-		axivdma@43000000 {
-			compatible = "xlnx,axi-vdma-1.00.a";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
+		dma@43000000 {
+			compatible = "adi,axi-dmac-1.00.a";
+			reg = <0x43000000 0x10000>;
 			#dma-cells = <0x1>;
-			#dma-channels = <0x1>;
-			reg = <0x43000000 0x1000>;
-			xlnx,num-fstores = <0x3>;
+			interrupts = <0x0 0x3b 0x0>;
+			clocks = <0x2 0x10>;
 			linux,phandle = <0xc>;
 			phandle = <0xc>;

-			dma-channel@43000000 {
-				compatible = "xlnx,axi-vdma-mm2s-channel";
-				interrupts = <0x0 0x3b 0x4>;
-				xlnx,datawidth = <0x40>;
-				xlnx,genlock-mode = <0x0>;
-				xlnx,include-dre = <0x0>;
+			adi,channels {
+				#size-cells = <0x0>;
+				#address-cells = <0x1>;
+
+				dma-channel@0 {
+					reg = <0x0>;
+					adi,source-bus-width = <0x40>;
+					adi,source-bus-type = <0x0>;
+					adi,destination-bus-width = <0x40>;
+					adi,destination-bus-type = <0x1>;
+				};
 			};
 		};

@ -756,6 +754,11 @@
 			phandle = <0x15>;
 		};

+		axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};
+
 		i2c@41620000 {
 			compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
 			reg = <0x41620000 0x10000>;
@ -796,7 +799,6 @@
 					adi,source-bus-type = <0x2>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x0>;
-					adi,length-width = <0x18>;
 				};
 			};
 		};
@ -820,8 +822,6 @@
 					adi,source-bus-type = <0x0>;
 					adi,destination-bus-width = <0x40>;
 					adi,destination-bus-type = <0x2>;
-					adi,length-width = <0x18>;
-					adi,cyclic;
 				};
 			};
 		};
@ -1064,19 +1064,19 @@
 	clocks {

 		clock@0 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x2625a00>;
 			clock-output-names = "ad9361_ext_refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x5>;
 			phandle = <0x5>;
 		};

 		clock@1 {
-			#clock-cells = <0x0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0x17d7840>;
 			clock-output-names = "refclk";
+			#clock-cells = <0x0>;
 			linux,phandle = <0x7>;
 			phandle = <0x7>;
 		};
--- a/kernel_boot/build_boot_bin.sh
+++ b/kernel_boot/build_boot_bin.sh
@ -1,13 +1,14 @@
 #!/bin/bash
+# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_2014r2

 if [ "$#" -ne 1 ]; then
    echo "You must enter the \$BOARD_NAME as argument"
-    echo "Like: adrv9364z7020 adrv9361z7035 adrv9361z7035_fmc zc706_fmcs2 zed_fmcs2 zc702_fmcs2"
+    echo "Like: adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371"
    exit 1
 fi
 BOARD_NAME=$1

-if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9361z7035_fmc" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
+if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
    echo "\$BOARD_NAME is not correct. Please check!"
    exit 1
 else
--- a/kernel_boot/build_zynqmp_boot_bin.sh
+++ b/kernel_boot/build_zynqmp_boot_bin.sh
@ -0,0 +1,162 @@
+#!/bin/bash
+# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp
+
+set -ex
+
+HDF_FILE=$1
+UBOOT_FILE=$2
+ATF_FILE=${3:-download}
+BUILD_DIR=build_boot_bin
+OUTPUT_DIR=output_boot_bin
+
+usage () {
+	echo "usage: $0 system_top.hdf u-boot.elf  (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]"
+	exit 1
+}
+
+depends () {
+	echo "Xilinx $1 must be installed and in your PATH"
+	echo "try: source /opt/Xilinx/Vivado/201x.x/settings64.sh"
+	exit 1
+}
+
+### Check command line parameters
+echo $HDF_FILE | grep -q ".hdf" || usage
+echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage
+
+if [ ! -f $HDF_FILE ]; then
+    echo $HDF_FILE: File not found!
+    usage
+fi
+
+if [ ! -f $UBOOT_FILE ]; then
+    echo $UBOOT_FILE: File not found!
+    usage
+fi
+
+### Check for required Xilinx tools
+command -v xsdk >/dev/null 2>&1 || depends xsdk
+command -v bootgen >/dev/null 2>&1 || depends bootgen
+command -v hsi >/dev/null 2>&1 || depends hsi
+
+rm -Rf $BUILD_DIR $OUTPUT_DIR
+mkdir -p $OUTPUT_DIR
+mkdir -p $BUILD_DIR
+
+# 2017.4 use 47af34b94a52b8cdc8abbac44b6f3ffab33a2206
+# 2018.1 use df4a7e97d57494c7d79de51b1e0e450d982cea98
+# 2018.2 use 93a69a5a3bc318027da4af5911124537f4907642
+# 2018.3 use 08560c36ea5b6f48b962cb4bd9a79b35bb3d95ce
+
+hsi_ver=$(hsi -version | head -1 | cut -d' ' -f2)
+if [ -z "$hsi_ver" ] ; then
+	echo "Could not determine Vivado version"
+	exit 1
+fi
+atf_version=xilinx-$hsi_ver
+
+### Check if ATF_FILE is .elf or path to arm-trusted-firmware
+if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then
+### Build arm-trusted-firmware bl31.elf
+(
+	cd $ATF_FILE
+	make distclean
+	git checkout $atf_version
+	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1
+)
+	cp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
+elif [ "$ATF_FILE" == "download" ]; then
+(
+	command -v git >/dev/null 2>&1 || depends git
+	cd $BUILD_DIR
+	git clone https://github.com/Xilinx/arm-trusted-firmware.git
+	cd arm-trusted-firmware
+	git checkout $atf_version
+	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1
+)
+	cp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
+else
+	echo $ATF_FILE | grep -q -e "bl31.elf" || usage
+	if [ ! -f $ATF_FILE ]; then
+		echo $ATF_FILE: File not found!
+		usage
+	fi
+	cp $ATF_FILE $OUTPUT_DIR/bl31.elf
+fi
+
+cp $HDF_FILE $BUILD_DIR/
+cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf
+cp $HDF_FILE $OUTPUT_DIR/
+
+# get the tools version (e.g., v2018.3)
+tool_version=$(hsi -version)
+tool_version=${tool_version#hsi\ }
+tool_version=${tool_version%\ (64-bit)*}
+
+# Work-arownd for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change
+# (https://www.xilinx.com/support/answers/71961.html)
+if [ $tool_version == "v2018.3" ];then
+(
+	wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
+	unzip $BUILD_DIR/72113-files.zip -d  $BUILD_DIR
+)
+fi
+
+### Create create_fsbl_project.tcl file used by xsdk to create the fsbl
+echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
+echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
+echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
+echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
+echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
+echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
+if [ $tool_version == "v2018.3" ];then
+(
+	echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+	echo "file copy -force xfsbl_hooks.c    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+	echo "file copy -force xfsbl_hooks.h    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+)
+fi
+echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
+
+### Create create_pmufw_project.tcl
+echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl
+echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl
+echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl
+
+### Create zynq.bif file used by bootgen
+echo "the_ROM_image:" > $OUTPUT_DIR/zynq.bif
+echo "{" >> $OUTPUT_DIR/zynq.bif
+echo "[bootloader,destination_cpu=a53-0] fsbl.elf" >> $OUTPUT_DIR/zynq.bif
+echo "[pmufw_image] pmufw.elf" >> $OUTPUT_DIR/zynq.bif
+echo "[destination_device=pl] system_top.bit" >> $OUTPUT_DIR/zynq.bif
+echo "[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf" >> $OUTPUT_DIR/zynq.bif
+echo "[destination_cpu=a53-0, exception_level=el-2] u-boot.elf" >> $OUTPUT_DIR/zynq.bif
+echo "}" >> $OUTPUT_DIR/zynq.bif
+
+
+### Build fsbl.elf & pmufw.elf
+(
+	cd $BUILD_DIR
+	xsdk -batch -source create_fsbl_project.tcl
+	hsi -source create_pmufw_project.tcl
+	### There was a bug in some vivado version where they build would fail -> check CC_FLAGS
+	grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile
+	cd pmufw
+	make
+)
+
+### Copy fsbl and system_top.bit into the output folder
+cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf
+cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit
+cp $BUILD_DIR/pmufw/executable.elf $OUTPUT_DIR/pmufw.elf
+
+### Build BOOT.BIN
+(
+	cd $OUTPUT_DIR
+	bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w
+)
+
+### Optionally tar.gz the entire output folder with the name given in argument 3
+if [ ${#4} -ne 0 ]; then
+	tar czvf $4.tar.gz $OUTPUT_DIR
+fi
--- a/kernel_boot/kernel_config
+++ b/kernel_boot/kernel_config
@ -1459,6 +1459,7 @@ CONFIG_SWPHY=y
 #
 # MII PHY device drivers
 #
+# CONFIG_ADIN_PHY is not set
 # CONFIG_AMD_PHY is not set
 # CONFIG_AQUANTIA_PHY is not set
 # CONFIG_AT803X_PHY is not set
@ -1676,7 +1677,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_IFX6X60 is not set
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-CONFIG_SERIAL_XILINX_NR_UARTS=2
 # CONFIG_SERIAL_ARC is not set
 # CONFIG_SERIAL_FSL_LPUART is not set
 # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
@ -1932,6 +1932,7 @@ CONFIG_HWMON=y
 #
 # CONFIG_SENSORS_AD7314 is not set
 # CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
 # CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
@ -1966,6 +1967,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_POWR1220 is not set
 # CONFIG_SENSORS_LINEAGE is not set
 # CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
 # CONFIG_SENSORS_LTC2990 is not set
 # CONFIG_SENSORS_LTC4151 is not set
 # CONFIG_SENSORS_LTC4215 is not set
@ -2378,6 +2381,7 @@ CONFIG_VIDEO_IMAGEON_BRIDGE=y
 # CONFIG_SOC_CAMERA is not set
 # CONFIG_VIDEO_XILINX is not set
 # CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER is not set
 # CONFIG_V4L_TEST_DRIVERS is not set

 #
@ -2668,6 +2672,8 @@ CONFIG_SND_SOC_ADRV936X_BOX=y
 # STMicroelectronics STM32 SOC audio support
 #
 # CONFIG_SND_SOC_XILINX_DP is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_I2S is not set
 # CONFIG_SND_SOC_XTFPGA_I2S is not set
 # CONFIG_ZX_TDM is not set
 CONFIG_SND_SOC_I2C_AND_SPI=y
@ -2677,6 +2683,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 #
 # CONFIG_SND_SOC_AC97_CODEC is not set
 CONFIG_SND_SOC_ADAU_UTILS=y
+# CONFIG_SND_SOC_ADAU1373 is not set
 CONFIG_SND_SOC_ADAU1701=y
 CONFIG_SND_SOC_ADAU17X1=y
 CONFIG_SND_SOC_ADAU1761=y
@ -3410,9 +3417,6 @@ CONFIG_ADIS16240=y
 #
 # Analog to digital converters
 #
-CONFIG_AD7606=y
-# CONFIG_AD7606_IFACE_PARALLEL is not set
-CONFIG_AD7606_IFACE_SPI=y
 CONFIG_AD7780=y
 CONFIG_AD7816=y
 CONFIG_AD7192=y
@ -3536,6 +3540,7 @@ CONFIG_FB_FLEX=y
 # CONFIG_TYPEC_TCPM is not set
 # CONFIG_PI433 is not set
 # CONFIG_XILINX_FCLK is not set
+# CONFIG_XROE_FRAMER is not set
 # CONFIG_GOLDFISH is not set
 # CONFIG_CHROME_PLATFORMS is not set
 CONFIG_CLKDEV_LOOKUP=y
@ -3545,12 +3550,12 @@ CONFIG_COMMON_CLK=y
 #
 # Common Clock Framework
 #
-# CONFIG_COMMON_CLK_ADF4360 is not set
 CONFIG_ICST=y
 # CONFIG_CLK_HSDK is not set
 # CONFIG_COMMON_CLK_SI5351 is not set
 # CONFIG_COMMON_CLK_SI514 is not set
 CONFIG_COMMON_CLK_SI570=y
+# CONFIG_COMMON_CLK_SI5324 is not set
 # CONFIG_COMMON_CLK_IDT8T49N24X is not set
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
@ -3681,15 +3686,21 @@ CONFIG_ADXL345_SPI=y
 # Analog to digital converters
 #
 CONFIG_AD_SIGMA_DELTA=y
+# CONFIG_AD400X is not set
 CONFIG_AD7091R5=y
+# CONFIG_AD7124 is not set
 CONFIG_AD7173=y
 CONFIG_AD7266=y
 CONFIG_AD7291=y
 CONFIG_AD7298=y
 CONFIG_AD738X=y
 CONFIG_AD7476=y
+CONFIG_AD7606=y
+# CONFIG_AD7606_IFACE_PARALLEL is not set
+CONFIG_AD7606_IFACE_SPI=y
 CONFIG_AD7766=y
 CONFIG_AD7768=y
+# CONFIG_AD7768_1 is not set
 CONFIG_AD7791=y
 CONFIG_AD7793=y
 CONFIG_AD7887=y
@ -3698,6 +3709,7 @@ CONFIG_AD799X=y
 CONFIG_AD9963=y
 CONFIG_ADM1177=y
 CONFIG_CF_AXI_ADC=y
+# CONFIG_AD9208 is not set
 CONFIG_AD9361=m
 # CONFIG_AD9361_EXT_BAND_CONTROL is not set
 CONFIG_AD9371=y
@ -3707,6 +3719,7 @@ CONFIG_AD9467=y
 CONFIG_AD9680=y
 CONFIG_ADMC=y
 CONFIG_CF_AXI_TDD=y
+# CONFIG_AXI_PULSE_CAPTURE is not set
 # CONFIG_AXI_FMCADC5_SYNC is not set
 # CONFIG_CC10001_ADC is not set
 # CONFIG_ENVELOPE_DETECTOR is not set
@ -3780,11 +3793,13 @@ CONFIG_AD5593R=y
 CONFIG_AD5504=y
 CONFIG_AD5624R_SPI=y
 CONFIG_LTC2632=y
-CONFIG_AD5686=y
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5696_I2C is not set
 CONFIG_AD5755=y
 # CONFIG_AD5758 is not set
 CONFIG_AD5761=y
 CONFIG_AD5764=y
+# CONFIG_AD5770R is not set
 CONFIG_AD5791=y
 CONFIG_AD7303=y
 CONFIG_AD8801=y
@ -3821,13 +3836,17 @@ CONFIG_CF_AXI_DDS=y
 CONFIG_CF_AXI_DDS_AD9122=y
 CONFIG_CF_AXI_DDS_AD9144=y
 CONFIG_CF_AXI_DDS_AD9162=y
+# CONFIG_CF_AXI_DDS_AD9172 is not set
 CONFIG_CF_AXI_DDS_AD9739A=y
+# CONFIG_M2K_DAC is not set

 #
 # Phase-Locked Loop (PLL) frequency synthesizers
 #
 CONFIG_ADF4350=y
 CONFIG_ADF5355=y
+# CONFIG_ADF4371 is not set
+# CONFIG_ADF4360 is not set

 #
 # Digital gyroscope sensors
@ -4007,6 +4026,7 @@ CONFIG_IIO_SYSFS_TRIGGER=y
 # Temperature sensors
 #
 # CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_LTC2983 is not set
 # CONFIG_MLX90614 is not set
 # CONFIG_TMP006 is not set
 # CONFIG_TMP007 is not set
@ -4061,13 +4081,16 @@ CONFIG_ARM_PMU=y
 # CONFIG_ANDROID is not set
 # CONFIG_DAX is not set
 CONFIG_NVMEM=y
+# CONFIG_NVMEM_AXI_SYSID is not set
 # CONFIG_STM is not set
 # CONFIG_INTEL_TH is not set
 CONFIG_FPGA=y
+# CONFIG_FPGA_MGR_DEBUG_FS is not set
 # CONFIG_FPGA_MGR_ICE40_SPI is not set
 # CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
 # CONFIG_FPGA_MGR_XILINX_SPI is not set
 CONFIG_FPGA_MGR_ZYNQ_FPGA=y
+# CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA is not set
 # CONFIG_FPGA_BRIDGE is not set
 # CONFIG_ALTERA_PR_IP_CORE is not set

--- a/kernel_boot/kernel_config_zynqmp
+++ b/kernel_boot/kernel_config_zynqmp
--- a/user_space/boot_bin_gen.sh
+++ b/user_space/boot_bin_gen.sh
@ -22,7 +22,7 @@ else
    exit 1
 fi

-if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9361z7035_fmc" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
+if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
    echo "\$BOARD_NAME is not correct. Please check!"
    exit 1
 else
@ -34,19 +34,9 @@ home_dir=$(pwd)
 set -ex

 # check if user entered the right path to SDK
-if [ -d "$XILINX_DIR" ]; then
-  source $XILINX_DIR/SDK/2017.4/settings64.sh
-else
-  echo "Error: XILINX_DIR: ${XILINX_DIR} not found. Can not continue."
-  exit 1
-fi
+source $XILINX_DIR/SDK/2018.3/settings64.sh

-if [ -d "$OPENWIFI_DIR" ]; then
-  cd $OPENWIFI_DIR/kernel_boot
-else
-  echo "Error: OPENWIFI_DIR: ${OPENWIFI_DIR} not found. Can not continue."
-  exit 1
-fi
+cd $OPENWIFI_DIR/kernel_boot

 ./build_boot_bin.sh $BOARD_NAME

--- a/user_space/boot_bin_gen_zynqmp.sh
+++ b/user_space/boot_bin_gen_zynqmp.sh
@ -0,0 +1,47 @@
+#!/bin/bash
+if [ "$#" -ne 3 ]; then
+    echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME"
+    exit 1
+fi
+
+OPENWIFI_DIR=$1
+XILINX_DIR=$2
+BOARD_NAME=$3
+
+if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
+    echo "\$OPENWIFI_DIR is found!"
+else
+    echo "\$OPENWIFI_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ -d "$XILINX_DIR/SDK" ]; then
+    echo "\$XILINX_DIR is found!"
+else
+    echo "\$XILINX_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
+    echo "\$BOARD_NAME is not correct. Please check!"
+    exit 1
+else
+    echo "\$BOARD_NAME is found!"
+fi
+
+home_dir=$(pwd)
+
+set -ex
+
+# check if user entered the right path to SDK
+source $XILINX_DIR/SDK/2018.3/settings64.sh
+
+cd $OPENWIFI_DIR/kernel_boot
+
+./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf
+# ./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf download
+rm -rf build_boot_bin
+rm -rf boards/$BOARD_NAME/output_boot_bin
+mv output_boot_bin boards/$BOARD_NAME/
+
+cd $home_dir
--- a/user_space/get_fpga.sh
+++ b/user_space/get_fpga.sh
@ -22,7 +22,7 @@ cd $OPENWIFI_DIR/
 git submodule init openwifi-hw
 git submodule update openwifi-hw
 cd openwifi-hw
-git checkout master
+git checkout zcu102_fmcs2
 git pull

 cd $home_dir
--- a/user_space/post_config.sh
+++ b/user_space/post_config.sh
@ -2,15 +2,27 @@

 set -ex

+MACHINE_TYPE=`uname -m`
+
 # setup kernel module directory
 if [ -d "/lib/modules/$(uname -r)" ]; then
    echo "/lib/modules/$(uname -r) already exists."
 else
-    ln -s /lib/modules/openwifi /lib/modules/$(uname -r)
+    if [ ${MACHINE_TYPE} == 'aarch64' ]; then
+        ln -s /lib/modules/adi-linux-64 /lib/modules/$(uname -r)
+    else
+        ln -s /lib/modules/adi-linux /lib/modules/$(uname -r)
+    fi
 fi
 depmod
 modprobe mac80211

+if [ ${MACHINE_TYPE} == 'aarch64' ]; then
+    cp ~/openwifi/drv64/* ~/openwifi/ -rf
+else
+    cp ~/openwifi/drv32/* ~/openwifi/ -rf
+fi
+
 # add gateway (PC) for internet access
 route add default gw 192.168.10.1 || true

--- a/user_space/prepare_kernel.sh
+++ b/user_space/prepare_kernel.sh
@ -0,0 +1,74 @@
+  
+#!/bin/bash
+if [ "$#" -lt 3 ]; then
+    echo "You must enter at least 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)"
+    exit 1
+fi
+
+OPENWIFI_DIR=$1
+XILINX_DIR=$2
+ARCH_OPTION=$3
+
+if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
+    echo "\$OPENWIFI_DIR is found!"
+else
+    echo "\$OPENWIFI_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ -d "$XILINX_DIR/SDK" ]; then
+    echo "\$XILINX_DIR is found!"
+else
+    echo "\$XILINX_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
+    echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
+    exit 1
+else
+    echo "\$ARCH_OPTION is valid!"
+fi
+
+if [ "$ARCH_OPTION" == "64" ]; then
+    LINUX_KERNEL_SRC_DIR_NAME=adi-linux-64
+    LINUX_KERNEL_CONFIG_FILE=$OPENWIFI_DIR/kernel_boot/kernel_config_zynqmp
+    ARCH_NAME="arm64"
+    CROSS_COMPILE_NAME="aarch64-linux-gnu-"
+    IMAGE_TYPE=Image
+else
+    LINUX_KERNEL_SRC_DIR_NAME=adi-linux
+    LINUX_KERNEL_CONFIG_FILE=$OPENWIFI_DIR/kernel_boot/kernel_config
+    ARCH_NAME="arm"
+    CROSS_COMPILE_NAME="arm-linux-gnueabihf-"
+    IMAGE_TYPE=uImage
+fi
+
+home_dir=$(pwd)
+
+set -x
+
+cd $OPENWIFI_DIR/
+git submodule init $LINUX_KERNEL_SRC_DIR_NAME
+git submodule update $LINUX_KERNEL_SRC_DIR_NAME
+cd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME
+git checkout 2019_R1
+git pull origin 2019_R1
+cp $OPENWIFI_DIR/driver/xilinx_dma/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/dma/xilinx/xilinx_dma.c
+cp $LINUX_KERNEL_CONFIG_FILE ./.config
+source $XILINX_DIR/SDK/2018.3/settings64.sh
+export ARCH=$ARCH_NAME
+export CROSS_COMPILE=$CROSS_COMPILE_NAME
+
+make oldconfig && make prepare && make modules_prepare
+
+if [ "$#" -gt 3 ]; then
+    if [ -f "$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/arch/$ARCH_NAME/boot/$IMAGE_TYPE" ]; then
+        echo "Kernel found! Skip the time costly Linux kernel compiling."
+    else
+        make -j12 $IMAGE_TYPE UIMAGE_LOADADDR=0x8000
+        make modules
+    fi
+fi
+
+cd $home_dir
--- a/user_space/prepare_kernel_src.sh
+++ b/user_space/prepare_kernel_src.sh
@ -1,39 +0,0 @@
-  
-#!/bin/bash
-if [ "$#" -ne 2 ]; then
-    echo "You must enter exactly 2 arguments: \$OPENWIFI_DIR \$XILINX_DIR"
-    exit 1
-fi
-
-OPENWIFI_DIR=$1
-XILINX_DIR=$2
-
-
-if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
-    echo "\$OPENWIFI_DIR is found!"
-else
-    echo "\$OPENWIFI_DIR is not correct. Please check!"
-    exit 1
-fi
-
-if [ -d "$XILINX_DIR/SDK" ]; then
-    echo "\$XILINX_DIR is found!"
-else
-    echo "\$XILINX_DIR is not correct. Please check!"
-    exit 1
-fi
-
-home_dir=$(pwd)
-
-cd $OPENWIFI_DIR/
-git submodule init adi-linux
-git submodule update adi-linux
-cd adi-linux
-git reset --hard 4220d5d24c6c7589fc702db4f941f0632b5ad767
-cp ../kernel_boot/kernel_config ./.config
-source $XILINX_DIR/SDK/2017.4/settings64.sh
-export ARCH=arm
-export CROSS_COMPILE=arm-linux-gnueabihf-
-make oldconfig && make prepare && make modules_prepare
-
-cd $home_dir
--- a/user_space/sdcard_boot_update.sh
+++ b/user_space/sdcard_boot_update.sh
@ -1,36 +1,62 @@
 #!/bin/bash
 if [ "$#" -ne 1 ]; then
    echo "You must enter the \$BOARD_NAME as argument"
-    echo "Like: adrv9364z7020 adrv9361z7035 adrv9361z7035_fmc zc706_fmcs2 zed_fmcs2 zc702_fmcs2"
+    echo "Like: adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371"
    exit 1
 fi
 BOARD_NAME=$1

+if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
+    echo "\$BOARD_NAME is not correct. Please check!"
+    exit 1
+else
+    echo "\$BOARD_NAME is found!"
+fi
+
+if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
+    dtb_filename="system.dtb"
+    image_filepath="arch/arm64/boot/"
+    image_filename="Image"
+    LINUX_KERNEL_SRC_DIR_NAME=adi-linux-64
+else
+    dtb_filename="devicetree.dtb"
+    image_filepath="arch/arm/boot/"
+    image_filename="uImage"
+    LINUX_KERNEL_SRC_DIR_NAME=adi-linux
+fi
+echo $dtb_filename
+echo $image_filepath
+echo $image_filename
+
 set -x

 rm BOOT.BIN
 sync
 wget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN
 sync
-rm uImage
+rm $image_filename
 sync
-wget ftp://192.168.10.1/adi-linux/arch/arm/boot/uImage
+wget ftp://192.168.10.1/$LINUX_KERNEL_SRC_DIR_NAME/$image_filepath/$image_filename
 sync
-rm devicetree.dtb
+rm $dtb_filename
 sync
-wget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/devicetree.dtb
+wget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/$dtb_filename
 sync
 #slepp 0.5
 mount /dev/mmcblk0p1  /mnt
 sync
 #sleep 0.5
 cp BOOT.BIN /mnt/ -f
-cp uImage /mnt/ -f
-cp devicetree.dtb /mnt/ -f
+rm /mnt/Image -f
+rm /mnt/uImage -f
+cp $image_filename /mnt/ -f
+rm /mnt/*.dtb -f
+cp $dtb_filename /mnt/ -f
+cd /mnt/
 sync
+cd ~
 #sleep 0.5
 umount /mnt
 sync
 #sleep 3
 sudo reboot now
-
--- a/user_space/set_csma_high.sh
+++ b/user_space/set_csma_high.sh
--- a/user_space/set_csma_normal.sh
+++ b/user_space/set_csma_normal.sh
--- a/user_space/slice_cfg.sh
+++ b/user_space/slice_cfg.sh
--- a/user_space/update_sdcard.sh
+++ b/user_space/update_sdcard.sh
@ -25,7 +25,7 @@ else
    exit 1
 fi

-if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9361z7035_fmc" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
+if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
    echo "\$BOARD_NAME is not correct. Please check!"
    exit 1
 else
@ -36,6 +36,7 @@ fi
 if [ -d "$SDCARD_DIR/BOOT/" ]; then
    echo "$SDCARD_DIR/BOOT/"
    mkdir $SDCARD_DIR/BOOT/openwifi
+    rm -rf $SDCARD_DIR/BOOT/README.txt
 else
    echo "$SDCARD_DIR/BOOT/ does not exist!"
    exit 1
@ -48,65 +49,96 @@ else
    exit 1
 fi

-sudo ls
+if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
+    dtb_filename="system.dtb"
+    dts_filename="system.dts"
+else
+    dtb_filename="devicetree.dtb"
+    dts_filename="devicetree.dts"
+fi
+echo $dtb_filename
+echo $dts_filename
+
+sudo true

 home_dir=$(pwd)

 set -x

-if [ -f "$OPENWIFI_DIR/adi-linux/arch/arm/boot/uImage" ]; then
-    echo "Skip the time costly Linux kernel compiling."
-else
-    # Build the Linux kernel uImage and modules
-    cd $OPENWIFI_DIR/
-    git submodule init adi-linux
-    git submodule update adi-linux
-    cd adi-linux
-    git reset --hard 4220d5d24c6c7589fc702db4f941f0632b5ad767
-    cp ../kernel_boot/kernel_config ./.config
-    source $XILINX_DIR/SDK/2017.4/settings64.sh
-    export ARCH=arm
-    export CROSS_COMPILE=arm-linux-gnueabihf-
-    make oldconfig && make prepare && make modules_prepare
-    make -j12 UIMAGE_LOADADDR=0x8000 uImage
-    make modules
-fi
+cd $OPENWIFI_DIR/user_space/
+./prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR 32 build
+sudo true
+./prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR 64 build
+sudo true
+
+LINUX_KERNEL_SRC_DIR_NAME32=adi-linux
+LINUX_KERNEL_SRC_DIR_NAME64=adi-linux-64

 $OPENWIFI_DIR/user_space/get_fpga.sh $OPENWIFI_DIR

-BOARD_NAME_ALL="zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9361z7035_fmc adrv9364z7020"
+BOARD_NAME_ALL="zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 zcu102_9371"
+# BOARD_NAME_ALL="zcu102_fmcs2"
+# BOARD_NAME_ALL="adrv9361z7035"
 for BOARD_NAME_TMP in $BOARD_NAME_ALL
 do
-# if [ -f "$OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN" ]; then
-#     echo "Skip the BOOT.BIN generation."
-# else
-#     # Build BOOT.BIN
-    $OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME_TMP
-# fi
-    dtc -I dts -O dtb -o $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/devicetree.dtb $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/devicetree.dts
+    if [ "$BOARD_NAME_TMP" == "zcu102_fmcs2" ] || [ "$BOARD_NAME_TMP" == "zcu102_9371" ]; then
+        dtb_filename_tmp="system.dtb"
+        dts_filename_tmp="system.dts"
+        $OPENWIFI_DIR/user_space/boot_bin_gen_zynqmp.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME_TMP
+    else
+        dtb_filename_tmp="devicetree.dtb"
+        dts_filename_tmp="devicetree.dts"
+        $OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME_TMP
+    fi
+    echo $dtb_filename_tmp
+    echo $dts_filename_tmp
+
+    dtc -I dts -O dtb -o $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dts_filename_tmp
    mkdir $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP
-    cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/devicetree.dtb $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP
+    cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP
    cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP
+    sudo true
 done

+mkdir $SDCARD_DIR/BOOT/openwifi/zynq-common
+cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage  $SDCARD_DIR/BOOT/openwifi/zynq-common/
+mkdir $SDCARD_DIR/BOOT/openwifi/zynqmp-common
+cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/openwifi/zynqmp-common/
+
 # Copy uImage BOOT.BIN and devicetree to SD card BOOT partition
-cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/devicetree.dtb $SDCARD_DIR/BOOT/
+cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/$dtb_filename $SDCARD_DIR/BOOT/
 cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/
-cp $OPENWIFI_DIR/adi-linux/arch/arm/boot/uImage $SDCARD_DIR/BOOT/
+if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
+    cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/
+else
+    cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/BOOT/
+fi

-# build openwifi driver
-$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR
-
-# Copy files to SD card rootfs partition
 sudo mkdir $SDCARD_DIR/rootfs/root/openwifi
-sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/ \;
 sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/ -rf
 sudo wget -P $SDCARD_DIR/rootfs/root/openwifi/webserver/ https://users.ugent.be/~xjiao/openwifi-low-aac.mp4

+# build openwifi driver
+$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR 32
+# Copy files to SD card rootfs partition
+sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv32
+sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv32 \;
+
+# build openwifi driver
+$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR 64
+# Copy files to SD card rootfs partition
+sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv64
+sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv64 \;
+
 sudo mkdir $SDCARD_DIR/rootfs/lib/modules
-sudo mkdir $SDCARD_DIR/rootfs/lib/modules/openwifi
-sudo find $OPENWIFI_DIR/adi-linux -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/openwifi/ \;
-sudo rm $SDCARD_DIR/rootfs/lib/modules/openwifi/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f
+
+sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32
+sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/ \;
+sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f
+
+sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64
+sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/ \;
+sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f

 sudo rm $SDCARD_DIR/rootfs/etc/udev/rules.d/70-persistent-net.rules
 sudo cp $OPENWIFI_DIR/kernel_boot/70-persistent-net.rules $SDCARD_DIR/rootfs/etc/udev/rules.d/