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https://github.com/open-sdr/openwifi.git
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fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz
This commit is contained in:
Xianjun Jiao
parent
a984b3fbc7
commit
2a1e074623
46
driver/sdr.c
46
driver/sdr.c
@ -327,7 +327,7 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
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u8 *pdata_tmp, fcs_ok, phy_rx_sn_hw, target_buf_idx;
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s8 signal;
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u16 rssi_val, addr1_high16=0, addr2_high16=0, addr3_high16=0, sc=0;
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bool content_ok = false;
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bool content_ok = false, len_overflow = false;
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struct dma_tx_state state;
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static u8 target_buf_idx_old = 0xFF;
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@ -347,7 +347,9 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
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tsft_high = (*((u32*)(pdata_tmp+4 )));
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rssi_val = (*((u16*)(pdata_tmp+8 )));
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len = (*((u16*)(pdata_tmp+12)));
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//len_new = (((len>>3) + ((len&0x7)!=0))<<3);
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len_overflow = (len>(RX_BD_BUF_SIZE-16)?true:false);
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rate_idx = (*((u16*)(pdata_tmp+14)));
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// fc_di = (*((u32*)(pdata_tmp+16)));
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@ -371,16 +373,16 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
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if (len>=28)
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sc = hdr->seq_ctrl;
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fcs_ok = (*(( u8*)(pdata_tmp+16+len-1)));
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fcs_ok = ( len_overflow?0:(*(( u8*)(pdata_tmp+16+len-1))) );
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//phy_rx_sn_hw = (fcs_ok&(NUM_RX_BD-1));
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phy_rx_sn_hw = (fcs_ok&0x7f);//0x7f is FPGA limitation
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dma_driver_buf_idx_mod = (state.residue&0x7f);
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//phy_rx_sn_hw = (fcs_ok&(NUM_RX_BD-1));
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fcs_ok = ((fcs_ok&0x80)!=0);
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ht_flag = ((rate_idx&0x10)!=0);
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rate_idx = (rate_idx&0xF);
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if ( (len>=14 && len<=8191) && (rate_idx>=8 && rate_idx<=15)) {
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if ( (len>=14 && (!len_overflow)) && (rate_idx>=8 && rate_idx<=15)) {
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// if ( phy_rx_sn_hw!=dma_driver_buf_idx_mod) {
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// printk("%s openwifi_rx_interrupt: WARNING sn %d next buf_idx %d!\n", sdr_compatible_str,phy_rx_sn_hw,dma_driver_buf_idx_mod);
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// }
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@ -395,11 +397,12 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
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signal = -128;
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else
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signal = rssi_val - priv->rssi_correction;
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if (addr1_low32!=0xffffffff && addr1_high16!=0xffff)
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printk("%s openwifi_rx_interrupt:%4dbytes ht%d %2dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x fcs%d sn%d i%d %ddBm\n", sdr_compatible_str,
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len, ht_flag, wifi_rate_table[rate_idx], hdr->frame_control,hdr->duration_id,
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reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
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sc,fcs_ok, phy_rx_sn_hw,dma_driver_buf_idx_mod,signal);
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printk("%s openwifi_rx_interrupt:%4dbytes ht%d %2dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x fcs%d sn%d i%d %ddBm\n", sdr_compatible_str,
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len, ht_flag, wifi_rate_table[rate_idx], hdr->frame_control,hdr->duration_id,
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reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
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sc,fcs_ok, phy_rx_sn_hw,dma_driver_buf_idx_mod,signal);
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// priv->phy_rx_sn_hw_old = phy_rx_sn_hw;
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if (content_ok) {
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@ -664,9 +667,12 @@ static void openwifi_tx(struct ieee80211_hw *dev,
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rate_hw_value = priv->drv_tx_reg_val[0];
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// check current packet belonging to which slice/hw-queue
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for (i=0; i<MAX_NUM_HW_QUEUE; i++) {
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if ( priv->dest_mac_addr_queue_map[i] == addr1_low32 && ( !addr_flag ) ) {
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break;
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i=0;
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if (fc_type==2 && fc_subtype==0 && (!addr_flag)) {
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for (; i<MAX_NUM_HW_QUEUE; i++) {
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if ( priv->dest_mac_addr_queue_map[i] == addr1_low32 ) {
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break;
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}
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}
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}
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queue_idx = i;
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@ -696,8 +702,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
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cts_duration = traffic_pkt_duration + sifs + pkt_need_ack*(sifs+ack_duration);
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}
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//if (addr1_low32!=0xffffffff && addr1_high16!=0xffff)
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if ( !addr_flag ) {
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if ( !addr_flag )
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printk("%s openwifi_tx: %4dbytes %2dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x flag%08x retry%d ack%d q%d sn%04d R/CTS %d%d %dM %dus wr/rd %d/%d\n", sdr_compatible_str,
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len_mac_pdu, wifi_rate_all[rate_hw_value],frame_control,duration_id,
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reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
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@ -709,7 +714,6 @@ static void openwifi_tx(struct ieee80211_hw *dev,
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// info->status.rates[1].idx,info->status.rates[1].count,info->status.rates[1].flags,
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// info->status.rates[2].idx,info->status.rates[2].count,info->status.rates[2].flags,
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// info->status.rates[3].idx,info->status.rates[3].count,info->status.rates[3].flags);
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}
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// this is 11b stuff
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// if (info->flags&IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
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@ -922,15 +926,11 @@ static int openwifi_start(struct ieee80211_hw *dev)
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// // xpu_api->XPU_REG_CSMA_CFG_write(3); // cw_min
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// xpu_api->XPU_REG_CSMA_CFG_write(3);
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//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( (1200<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz
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xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
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//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
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xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030)<<16)|0 );//now our tx send out I/Q immediately
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//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200)<<16) | 400 );//2.4GHz
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//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200)<<16) | 400 );//5GHz
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// // value from openwifi-pre0 csma_test branch
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200)<<16) | 200 );//2.4GHz
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200)<<16) | 200 );//5GHz
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200 + 300)<<16) | 200 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200 + 300)<<16) | 200 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
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tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*200)<<16)|(10*200) );//high 16bit 5GHz; low 16 bit 2.4GHz
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@ -388,13 +388,11 @@ static inline u32 hw_init(enum xpu_mode mode){
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//xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
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xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
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xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
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//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200)<<16) | 400 );//2.4GHz
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//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200)<<16) | 400 );//5GHz
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// // value from openwifi-preo csma_test
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+6)*200)<<16) | 200 );//2.4GHz, still need to find out why sometimes the PI in ad-hoc 2.4GHz mode give ack so slow: 18us
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*200)<<16) | 200 );//5GHz
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// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
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xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030)<<16)|0 );//now our tx send out I/Q immediately
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200 + 300)<<16) | 200 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
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xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200 + 300)<<16) | 200 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
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printk("%s hw_init err %d\n", xpu_compatible_str, err);
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return(err);
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59
user_space/link_perf_test.sh
Executable file
59
user_space/link_perf_test.sh
Executable file
@ -0,0 +1,59 @@
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#!/bin/bash
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PL_MIN=100
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PL_INC=100
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PL_MAX=1500
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PAYLOAD=( $(seq -s' ' $PL_MIN $PL_INC $PL_MAX) ) # paload size in bytes
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MCS_BPS=( 6 9 12 18 24 36 48 54 )
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MCS_IDX=( 4 5 6 7 8 9 10 11 )
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INTERVAL=0.001 # Wait interval seconds between sending each packet
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PKT_CNT=700 # Stop after sending count ECHO_REQUEST packets
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DEADLINE=1 # Specify a timeout, in seconds, before ping exits regardless of how many packets have been sent or received
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SDRCTL_EXEC="./sdrctl_src/sdrctl"
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CLIENT_IP="192.168.13.2"
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# Bandwidth = 1.4 MHz
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printf "LINK PERFORMANCE TEST\n"
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printf "=====================\n"
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printf "RATE/PL\t"
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for (( j = 0 ; j < ${#PAYLOAD[@]} ; j++ )) do
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printf "%*s" 12 "${PAYLOAD[j]}"
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done
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printf "\n"
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for (( i = 0 ; i < ${#MCS_IDX[@]} ; i++ )) do
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# configure MCS
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$SDRCTL_EXEC dev sdr0 set reg drv_tx 0 ${MCS_IDX[$i]} > /dev/null
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printf "%sMbps\t" ${MCS_BPS[$i]}
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for (( j = 0 ; j < ${#PAYLOAD[@]} ; j++ )) do
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# Measure link performance
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link_per_str=$(ping $CLIENT_IP -i $INTERVAL -c $PKT_CNT -w $DEADLINE -s ${PAYLOAD[$j]} -nq | while read line; do
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# Skip non packet-loss and non rtt responses
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[[ ! "$line" =~ "packet loss" ]] && [[ ! "$line" =~ "rtt" ]] && continue
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# Extract packet loss
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if [[ "$line" =~ "packet loss" ]]; then
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PL=$(echo $line | grep 'packet loss' | cut -d' ' -f6)
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if [[ $PL == "100%" ]]; then
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printf "%s,INF" $PL
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else
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printf "%s," $PL
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fi
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# Extract rtt
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else
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RTT=$(echo $line | grep rtt | cut -d/ -f5)
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printf "%s" $RTT
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fi
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done)
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printf "%*s" 12 $link_per_str
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done
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printf "\n"
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done
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