Xianjun Jiao ce40e055d2 Add modified ad9361_conv.c of our own: ... Sometimes the unstable hardware can not pass the 61.44Msps self-test/calibration. Override it to 40Msps		2022-03-26 20:34:55 +01:00
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ad9361	Add modified ad9361_conv.c of our own:	2022-03-26 20:34:55 +01:00
openofdm_rx	turn on soft decoding by default in openofdm_rx.c driver	2021-04-05 21:41:31 +02:00
openofdm_tx	Update openofdm_tx.c	2021-02-03 15:38:47 +01:00
rx_intf	Fix various typos	2021-02-04 20:41:51 +01:00
side_ch	Scripts are adapted for SW HW decouple	2021-10-20 22:50:30 +02:00
tx_intf	use FPGA fifo count registers instead of software queue_cnt	2022-01-06 15:07:50 +01:00
xilinx_dma	Scripts are adapted for SW HW decouple	2021-10-20 22:50:30 +02:00
xpu	A-MPDU rx aggregation support	2022-01-06 14:13:24 +01:00
hw_def.h	use FPGA fifo count registers instead of software queue_cnt	2022-01-06 15:07:50 +01:00
make_all.sh	Scripts are adapted for SW HW decouple	2021-10-20 22:50:30 +02:00
Makefile	prepare upgrade	2020-04-27 09:37:04 +02:00
sdr.c	Missing aggregation rules	2022-01-06 15:12:03 +01:00
sdr.h	tx_interrupt if/else optimization	2022-01-06 15:11:05 +01:00