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openofdm/verilog
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Jiao Xianjun 19acdbe82f
Merge pull request #6 from ytakeuch/dot11zynq 
fix unsigned signals to signed signals
2023-01-28 12:00:50 +01:00
..
coregen
change the latency of divider from automatic 60 clocks to the original 36 clock
2020-09-02 16:49:59 +02:00
sim_out
add sim_out dir
2017-04-03 15:25:48 -04:00
usrp2
verilog init
2017-04-03 12:52:03 -04:00
Xilinx
Workaround to supress the error message when the 1st time run simulation
2022-05-13 13:21:19 +02:00
bits_to_bytes.v
verilog init
2017-04-03 12:52:03 -04:00
calc_mean.v
verilog init
2017-04-03 12:52:03 -04:00
common_defs.v
phase estimation update: quadrant quantization from 256 slices -> 512 slices
2022-01-04 22:15:16 +01:00
common_params.v
extend the status_code to more formated style
2023-01-09 14:40:46 +01:00
complex_mult.v
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
complex_to_mag_sq.v
verilog init
2017-04-03 12:52:03 -04:00
complex_to_mag.v
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
crc32.v
verilog init
2017-04-03 12:52:03 -04:00
deinter_lut.coe
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
deinter_lut.mif
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
deinterleave.v
remove debug
2020-06-12 10:24:59 +02:00
delay_sample.v
verilog init
2017-04-03 12:52:03 -04:00
delayT.v
verilog init
2017-04-03 12:52:03 -04:00
demodulate.v
soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM
2019-12-10 13:45:43 +01:00
descramble.v
remve unused variable in descramble.v
2017-04-21 13:41:28 -04:00
divider.v
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
dot11_modules.list
verilog init
2017-04-03 12:52:03 -04:00
dot11_side_ch_tb.v
Add conditional compiling framework
2022-05-13 13:24:41 +02:00
dot11_tb.v
Change the phase control value to the most safe one
2023-01-09 15:57:28 +01:00
dot11.v
Merge pull request #6 from ytakeuch/dot11zynq
2023-01-28 12:00:50 +01:00
equalizer.v
LVPE correction before estimation
2023-01-09 15:45:05 +01:00
fifo_sample_delay.v
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
ht_sig_crc.v
verilog init
2017-04-03 12:52:03 -04:00
intf_64bit.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
last_sym_indicator.v
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
Makefile
makefile
2017-04-03 14:05:07 -04:00
moving_avg.v
verilog init
2017-04-03 12:52:03 -04:00
mv_avg_dual_ch.v
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
mv_avg.v
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
ofdm_decoder.v
Shrink the bits of num_bits_to_decode and deinter_out_count:
2023-01-09 15:24:42 +01:00
openofdm_rx_s_axi.v
Add FFT window shift register
2023-01-09 15:40:42 +01:00
openofdm_rx.v
Add antsdr/e200 and sdrpi
2023-01-09 16:00:47 +01:00
phase.v
bug fix: increase phase calculation delay by 1 CLK
2022-01-04 22:22:00 +01:00
phy_len_calculation.v
Add phy len indication for decoding latency prediciton:
2023-01-09 15:28:25 +01:00
power_trigger.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
rand_gen_tb.v
verilog init
2017-04-03 12:52:03 -04:00
rand_gen.v
verilog init
2017-04-03 12:52:03 -04:00
rate_to_idx.v
verilog init
2017-04-03 12:52:03 -04:00
rot_lut.coe
verilog init
2017-04-03 12:52:03 -04:00
rot_lut.mif
verilog init
2017-04-03 12:52:03 -04:00
rotate.v
phase register size reduction: 32bit -> 16bit
2022-01-04 22:10:36 +01:00
running_sum_dual_ch.v
Add signal_watchdog module to prevent fake demod in early phase:
2022-03-15 16:03:40 +01:00
running_sum.v
Add signal_watchdog module to prevent fake demod in early phase:
2022-03-15 16:03:40 +01:00
signal_watchdog.v
signal watchdog only work while rssi above threshold:
2023-01-09 15:31:52 +01:00
stage_mult.v
LTF cross-correlation window update: 16->32 complex samples
2022-01-04 22:16:18 +01:00
sync_long.v
Add FFT window shift register
2023-01-09 15:40:42 +01:00
sync_short.v
Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved)
2023-01-09 14:48:34 +01:00
viterbi.v
verilog init
2017-04-03 12:52:03 -04:00