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coregen
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change the latency of divider from automatic 60 clocks to the original 36 clock
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2020-09-02 16:49:59 +02:00 |
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sim_out
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add sim_out dir
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2017-04-03 15:25:48 -04:00 |
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usrp2
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verilog init
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2017-04-03 12:52:03 -04:00 |
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Xilinx
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Workaround to supress the error message when the 1st time run simulation
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2022-05-13 13:21:19 +02:00 |
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bits_to_bytes.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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calc_mean.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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common_defs.v
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phase estimation update: quadrant quantization from 256 slices -> 512 slices
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2022-01-04 22:15:16 +01:00 |
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common_params.v
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extend the status_code to more formated style
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2023-01-09 14:40:46 +01:00 |
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complex_mult.v
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Make some basic block simpler and its delay more deterministic
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2023-01-09 14:47:34 +01:00 |
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complex_to_mag_sq.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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complex_to_mag.v
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Make some basic block simpler and its delay more deterministic
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2023-01-09 14:47:34 +01:00 |
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crc32.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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deinter_lut.coe
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necessary bug fixes and improvements for openwifi
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2019-12-10 13:31:16 +01:00 |
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deinter_lut.mif
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necessary bug fixes and improvements for openwifi
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2019-12-10 13:31:16 +01:00 |
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deinterleave.v
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remove debug
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2020-06-12 10:24:59 +02:00 |
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delay_sample.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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delayT.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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demodulate.v
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soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM
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2019-12-10 13:45:43 +01:00 |
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descramble.v
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remve unused variable in descramble.v
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2017-04-21 13:41:28 -04:00 |
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divider.v
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extend support to zcu102/Zynq MPSoC ultra_scale
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2020-04-27 15:46:16 +02:00 |
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dot11_modules.list
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verilog init
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2017-04-03 12:52:03 -04:00 |
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dot11_side_ch_tb.v
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Add conditional compiling framework
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2022-05-13 13:24:41 +02:00 |
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dot11_tb.v
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Change the phase control value to the most safe one
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2023-01-09 15:57:28 +01:00 |
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dot11.v
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Merge pull request #6 from ytakeuch/dot11zynq
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2023-01-28 12:00:50 +01:00 |
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equalizer.v
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LVPE correction before estimation
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2023-01-09 15:45:05 +01:00 |
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fifo_sample_delay.v
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Make some basic block simpler and its delay more deterministic
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2023-01-09 14:47:34 +01:00 |
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ht_sig_crc.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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intf_64bit.v
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port dot11 to zynq
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2019-12-10 14:09:31 +01:00 |
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last_sym_indicator.v
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necessary bug fixes and improvements for openwifi
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2019-12-10 13:31:16 +01:00 |
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Makefile
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makefile
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2017-04-03 14:05:07 -04:00 |
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moving_avg.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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mv_avg_dual_ch.v
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Make some basic block simpler and its delay more deterministic
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2023-01-09 14:47:34 +01:00 |
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mv_avg.v
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Make some basic block simpler and its delay more deterministic
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2023-01-09 14:47:34 +01:00 |
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ofdm_decoder.v
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Shrink the bits of num_bits_to_decode and deinter_out_count:
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2023-01-09 15:24:42 +01:00 |
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openofdm_rx_s_axi.v
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Add FFT window shift register
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2023-01-09 15:40:42 +01:00 |
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openofdm_rx.v
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Add antsdr/e200 and sdrpi
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2023-01-09 16:00:47 +01:00 |
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phase.v
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bug fix: increase phase calculation delay by 1 CLK
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2022-01-04 22:22:00 +01:00 |
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phy_len_calculation.v
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Add phy len indication for decoding latency prediciton:
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2023-01-09 15:28:25 +01:00 |
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power_trigger.v
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port dot11 to zynq
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2019-12-10 14:09:31 +01:00 |
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rand_gen_tb.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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rand_gen.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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rate_to_idx.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
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rot_lut.coe
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verilog init
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2017-04-03 12:52:03 -04:00 |
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rot_lut.mif
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verilog init
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2017-04-03 12:52:03 -04:00 |
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rotate.v
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phase register size reduction: 32bit -> 16bit
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2022-01-04 22:10:36 +01:00 |
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running_sum_dual_ch.v
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Add signal_watchdog module to prevent fake demod in early phase:
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2022-03-15 16:03:40 +01:00 |
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running_sum.v
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Add signal_watchdog module to prevent fake demod in early phase:
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2022-03-15 16:03:40 +01:00 |
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signal_watchdog.v
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signal watchdog only work while rssi above threshold:
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2023-01-09 15:31:52 +01:00 |
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stage_mult.v
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LTF cross-correlation window update: 16->32 complex samples
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2022-01-04 22:16:18 +01:00 |
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sync_long.v
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Add FFT window shift register
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2023-01-09 15:40:42 +01:00 |
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sync_short.v
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Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved)
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2023-01-09 14:48:34 +01:00 |
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viterbi.v
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verilog init
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2017-04-03 12:52:03 -04:00 |
