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37 lines
568 B
Verilog
37 lines
568 B
Verilog
module ht_sig_crc
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(
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input clock,
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input enable,
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input reset,
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input bit,
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input input_strobe,
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output [7:0] crc
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);
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reg [7:0] C;
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genvar i;
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generate
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for (i = 0; i < 8; i=i+1) begin: reverse
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assign crc[i] = ~C[7-i];
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end
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endgenerate
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always @(posedge clock) begin
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if (reset) begin
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C <= 8'hff;
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end else if (enable) begin
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if (input_strobe) begin
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C[0] <= bit ^ C[7];
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C[1] <= bit ^ C[7] ^ C[0];
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C[2] <= bit ^ C[7] ^ C[1];
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C[7:3] <= C[6:2];
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end
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end
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end
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endmodule
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