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29 lines
547 B
Verilog
29 lines
547 B
Verilog
module rand_gen
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(
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input clock,
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input enable,
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input reset,
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output reg [7:0] rnd
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);
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localparam LFSR_LEN = 128;
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reg [LFSR_LEN-1:0] random;
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wire feedback = random[127] ^ random[125] ^ random[100] ^ random[98];
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reg [2:0] bit_idx;
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always @(posedge clock) begin
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if (reset) begin
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random <= {LFSR_LEN{4'b0101}};
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bit_idx <= 0;
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rnd <= 0;
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end else if (enable) begin
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random <= {random[LFSR_LEN-2:0], feedback};
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rnd[bit_idx] <= feedback;
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bit_idx <= bit_idx + 1;
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end
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end
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endmodule
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