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bcee4f66a1
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fix packet detection
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2017-04-14 11:01:05 -04:00 |
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701cbb70c9
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variable name
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2017-04-14 11:00:46 -04:00 |
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0b0723899a
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rotate
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2017-04-14 11:00:33 -04:00 |
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47577f7099
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fix comment
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2017-04-14 11:00:12 -04:00 |
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191b197d5e
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fix polarity pattern
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2017-04-14 11:00:01 -04:00 |
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4f313f3ef9
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doc
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2017-04-14 10:59:40 -04:00 |
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4e3c57c5f3
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working on eq
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2017-04-12 15:49:17 -04:00 |
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297162af13
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working
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2017-04-07 16:51:06 -04:00 |
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c4c81b2766
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fix lts index
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2017-04-07 16:50:16 -04:00 |
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20279b42a4
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fix long preamble sample beginning index
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2017-04-07 16:49:41 -04:00 |
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652c8c1bb7
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working on sync_long
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2017-04-07 16:48:34 -04:00 |
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df46bc5309
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phase lut
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2017-04-07 11:37:11 -04:00 |
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779b3651a4
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remove unused verilog files
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2017-04-07 11:36:51 -04:00 |
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8375779a03
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refactor name
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2017-04-07 11:36:41 -04:00 |
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4dd053ebf8
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use delayT
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2017-04-07 11:36:21 -04:00 |
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28c57fc17f
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doc
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2017-04-05 16:06:23 -04:00 |
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63dd5a42f2
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working
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2017-04-03 15:48:37 -04:00 |
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cf42e1b7ae
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working
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2017-04-03 15:48:25 -04:00 |
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506472dec3
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add sim_out dir
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2017-04-03 15:25:48 -04:00 |
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23e1c270e0
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requirements.txt
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2017-04-03 14:42:56 -04:00 |
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8b4df2fcfe
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doc init
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2017-04-03 14:42:37 -04:00 |
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1ad9302fc3
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readme
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2017-04-03 14:31:25 -04:00 |
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d3ff9e7ce8
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makefile
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2017-04-03 14:05:07 -04:00 |
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bf4701fb39
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makefile
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2017-04-03 12:59:32 -04:00 |
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cf69020661
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init
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2017-04-03 12:52:37 -04:00 |
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379f20e652
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testing inputs init
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2017-04-03 12:52:31 -04:00 |
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20a33eb560
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scripts init
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2017-04-03 12:52:21 -04:00 |
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9edf1899bd
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verilog init
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2017-04-03 12:52:03 -04:00 |
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