Commit Graph

994 Commits

Author SHA1 Message Date
Martin Stein
693a2b5421 base-hw: get rid of cpu_pool() in platform.cc
The function was only still used for reading the execution time of idle threads
of CPUs. Certainly, it is technically fine and more performant to read these
values directly from the kernel objects without doing a syscall. However,
calling cpu_pool() for it provides read and write access to a lot more than
only the execution time values. The interface via which Core directly reads
state of the kernel should be as narrow and specific as possible.
Perspectively, we want to get rid of the cpu_pool() accessor anyway. Therefore
this commit introduces Kernel::read_idle_thread_execution_time(cpu_idx) as
replacement. The function is implemented in kernel code and called by Core in
platform.cc.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
277adcacb0 base-hw: make Trace_source in Platform() a class
Apparently, there is no need for exposing the data members of Trace_source, so,
we sould better make them private before someone gets the impression that they
are meant to be accessed directly.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
aa6a7db50a base-hw: communicate kernel irqs via boot info
Core used to read the kernel-reserved IRQs from the timer objects in the
kernel's CPU objects and the PIC class (inter-processor IRQ). Besides not
being "good style" to access a kernel object in Core, this becomes a problem
when trying to prevent CPU pool from being accessed via global functions.

As a solution, this commit extends the boot info to also carry an array of all
kernel-reserved IRQs.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
8b69bc96f9 base-hw: separate variants of Kernel_object(...)
For the constructor of Kernel_object<T> there are two variants. One for the
case that it is called from Core where the kernel object (type T) must be
created via a syscall and one when it is called from within the kernel and the
kernel object can be created directly. Selecting one of these variants was done
using a bool argument to the constructor. However, this implies that the
constructor of Kernel_object<T> and that of T have the same signature in the
variadic arguments, even in the syscall case, although technically it would
then not be necessary.

This becomes a problem as soon as kernel objects created by Core shall receive
additional arguments from the kernel, for instance a reference to the global
CPU pool, and therefore stands in the way when wanting to get rid of global
statics in the kernel. Therefore, this commit introduces two constructors that
are selected through enum arguments:

! Kernel_object(Called_from_kernel, ...);
! Kernel_object(Called_from_core, ...);

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
6e4ef43bf0 base-hw: always use 'unsigned' for priorities
At some points in the code, 'signed' was used instead of the more appropriate
'unsigned' type.

Ref #4217
2021-10-13 14:46:52 +02:00
Martin Stein
b922dc5c10 base-hw: fix self-include in kernel/types.h
That this header apparently used to include itself didn't cause any problems
so far but still remained bad style.

Ref #4217
2021-10-13 14:46:52 +02:00
Christian Helmuth
83c5648d33 depot: update recipe hashes 2021-08-30 15:00:39 +02:00
Christian Helmuth
7618c9410a depot: update recipe hashes 2021-08-18 15:06:12 +02:00
Christian Helmuth
fce525f122 depot: update recipe hashes 2021-07-28 11:27:05 +02:00
Stefan Kalkowski
f939b9ffb5 base-hw: print addr as hex value in cache warning
Ref #4207
2021-07-28 11:25:21 +02:00
Sebastian Sumpf
4b10aa94ec base-hw: save/restore fpcr register for ARM_V8
The floating-point (fpcr) control register is user land accessible and
controls, for example, rounding mode.

fixes #3723 and related to #4213
2021-07-28 11:25:20 +02:00
Christian Helmuth
ece33d37f8 depot: update recipe hashes 2021-06-25 11:46:37 +02:00
Stefan Kalkowski
e7067050be base: extend cache maintainance functionality
Introduce two new cache maintainance functions:
* cache_clean_invalidate_data
* cache_invalidate_data
used to flush or invalidate data-cache lines.

Both functions are typically empty, accept for the ARM architecture.
The commit provides implementations for the base-hw kernel, and Fiasco.OC.

Fixes #4207
2021-06-25 11:43:41 +02:00
Christian Helmuth
1d52bd017d depot: update recipe hashes 2021-05-28 14:16:46 +02:00
Stefan Kalkowski
9f099bd61c base-hw: use generalized util/array.h
Issue #4170
2021-05-28 14:16:45 +02:00
Alexander Boettcher
509e5aa776 platform(x86): report features via platform_info
Report via platform_info the capabilities of the kernel, e.g. ACPI and MSI.

With the commit the try-catch pattern on IRQ session creation by the platform
driver is avoided.

Issue #4016
2021-05-28 14:16:44 +02:00
Christian Helmuth
777923f9bd depot: update recipe hashes 2021-05-10 11:18:12 +02:00
Norman Feske
516a9a6925 depot: update recipe hashes 2021-05-05 11:35:31 +02:00
Christian Prochaska
c4e3d3dbc4 hw: fix build error with gcc 10
Fixes #4115
2021-05-05 11:35:30 +02:00
Norman Feske
efbed6f7bf depot: update recipe hashes 2021-04-20 12:10:58 +02:00
Norman Feske
dc89ebf978 core: kernel-agnostic 'Mapping' type
This patch unifies the core-internal 'Mapping' type across all base
platforms.

As one minor downside on seL4, the diagnostic error messages when
observing faults other than page faults no longer print the faulting
thread and PD names.

Issue #2243
2021-04-20 12:10:57 +02:00
Norman Feske
468e7a825c base/cache.h: rename Cache_attribute to Cache
The short name is better because the type will become prominently
visible at the API.

Issue #2243
2021-04-20 12:10:31 +02:00
Norman Feske
0f9cb72cfa depot: update recipe hashes 2021-03-29 13:46:49 +02:00
Jean-Adrien DOMAGE
32169cd137 add I2c driver for imx8q based platform
This commit introduces a new i2c driver for the imx8q_evk based platform.

Fixes #4052
2021-03-29 13:45:24 +02:00
Norman Feske
5c5b56d1e0 depot: update recipe hashes 2021-03-12 12:08:24 +01:00
Sebastian Sumpf
6223ae4413 riscv: Interrupt controller support
- Enable the "platform-level interrupt controller" PLIC on base-hw
- The RISC-V specification offers only a register description, but no
  layout for the register set. This implies the layout is platform
  dependent, and therefore, implemented separately for Qemu

issue #4042
2021-03-12 12:01:38 +01:00
Norman Feske
aa0a98bd43 base-foc/hw: avoid use of placement new operator
Fixes #2106
2021-03-12 12:01:38 +01:00
Norman Feske
c68443e2eb base-hw: support packaging of multi-arch boards
With this patch, the board/<name>/arch property file can have multiple
lines where each line denotes an instruction-set architecture supported
for the board.

Issue #4019
Fixes #4034
2021-03-12 12:01:36 +01:00
Sebastian Sumpf
d4b58b689c base-hw: fix RISC-V duration calculation
Simplify calculation of Timer::_duration, the old implementation caused
the time running backwards sometimes. This makes
'nic_router_dhcp_*' and 'event_filter' run scripts succeed.

issue #4021
2021-03-12 12:01:36 +01:00
Christian Helmuth
0afd3db894 depot: update recipe hashes 2021-02-25 11:24:23 +01:00
Sebastian Sumpf
f68e655312 mk: link core to library archive instead of .o file
Do not link base and core libraries into on large relocatable .o file,
which is linked later to core - causing long link times. Create an
independent library archive out of the base and core libraries that can
be linked faster.

issue #4027
2021-02-23 12:17:04 +01:00
Norman Feske
64165d829e depot: update recipe hashes 2021-02-23 12:07:18 +01:00
Christian Helmuth
219809ffed base: refactor VM/vCPU API
Issue #3554
2021-02-23 12:07:18 +01:00
Sebastian Sumpf
ca777fe93f riscv: add riscv_qemu base-hw recipe
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
ccd9ba4161 riscv: move CPU header from base-hw to base
issue #4021
2021-02-23 12:07:16 +01:00
Sebastian Sumpf
f5cd12dcf9 base/base-hw: unify startup library builds
- Use 'select_from_repositories' for crt0.s of startup library
- Move RISC-V crt0.s to base (where the other archs are located)

issue #4019
2021-02-23 12:07:15 +01:00
Norman Feske
db3f86d603 base-hw: avoid double slashes in path names 2021-02-23 12:02:45 +01:00
Norman Feske
fa68325a57 base-hw: streamline extraction of depot archives
This patch simplifies the packaging of the base-hw kernel for a given
board, in particular when the board support is hosted as an external
repository such as genode-world. Regardless of where the board-support
is hosted, the content.mk file becomes as simple as:

  include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

The board name is automatically inferred from the path of the src
recipe. The architecture is determined from board/<name>/arch files,
following the pattern of the image_link_address. The attempt to build a
base-hw-<board> binary archive for the wrong architecture is now
gracefully handled by skipping all targets (using the REQUIRES
mechanism).

Besides the improved convenience, the patch results in depot archives
that are much closer tailored to the actual board by omitting files for
architectures that are not used by the board. E.g., the src/base-hw-pc
archive does not contain any ARM-related content.

The patch also restores the package builds for core/bootstrap object
files as a follow-up fix of "base: remove SPEC variables of boards",
which happened to left 'BOARD' undefined in the src archives.

Fixes #4019
2021-02-23 12:02:45 +01:00
Sebastian Sumpf
fd0e6685fc riscv: Use Qemu and update to ISA v1.10
- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012
2021-02-23 12:02:44 +01:00
Norman Feske
493924a35e base-hw: coding style
Improve consistency with the other base repositories, in particular

- Indentation of class initializers
- Vertical whitespace around control-flow statements
- Preferably place control-flow statements (return, break, continue) at
  beginning of a line
- Placing the opening brace of a namespace at the end of line
- Placing the opening brace of a class at a new line
- Removing superfluous braces around single statements
- Two empty lines between methods/functions in implementation files
2021-02-23 12:02:41 +01:00
Norman Feske
8cc2662aac Remove support for the Muen separation kernel
Fixes #3995
Fixes #3994
2021-02-23 11:55:44 +01:00
Norman Feske
a981fb864c depot: update recipe hashes 2021-01-25 14:00:43 +01:00
Norman Feske
c4cf9b6e6d base-hw: introduce board-property directories
This patch moves the bootstrap-link-address information from the
tool/run/boot_dir/hw file to board-specific property files that can be
accessed by using the board as key. This eliminates the need to
customize boot_dir/hw when hosting board-support in an external
repository.

Fixes #3998
2021-01-25 14:00:43 +01:00
Piotr Tworek
8f6b934caa base-hw: Fully define _crt0_start_stack value on arm_64
The _crt0_start_stack label points to a memory location containing the
size of the bootstrap stack. On AArch64 this should be an 8 byte value,
but the code only only defines half of those using asm .long statement.
The other half is expected to be 0, which is true when using GNU as.
This is not the case when using clang's integrated as however. Since
_crt0_stack_size is defined inside .text section clang uses 0xd503201f
value (aarch64 nop instruction) to fill the extra 4 bytes.

Fix this minor incompatibility by explicitly defining both halfs of
this 8 byte quantity.

Fixes #3987
2021-01-25 14:00:43 +01:00
Norman Feske
1ccf8a280c base-hw: simplify board support in external repo
Avoid use of REP_DIR in *.mk files to simplify the use of these files as
templates for a board hosted in a separate repository.

Use REP_INC_DIR for searching headers, thereby considering headers
hosted in an external repository.

Issue #3168
2021-01-25 13:58:10 +01:00
Stefan Kalkowski
bdd923406f base: remove SPEC variables of boards (fix #3971)
* Remove SPEC declarations from mk/spec
* Remove all board-specific REQUIRE declaratiions left
* Replace [have_spec <board>] run-script declarations with have_board where necessary
* Remove addition of BOARD variable to SPECS in toplevel Makefile
* Move board-specific directories in base-hw out of specs
2021-01-25 13:58:09 +01:00
Pirmin Duss
a4d5687510 base-hw: allow out of tree imx8 platforms
Issue #3911
2021-01-25 13:58:09 +01:00
Alexander Boettcher
2b0170fb6a base-hw: ack thread capability on construction
Fixes #3982
2021-01-25 13:58:09 +01:00
Norman Feske
f57519397b Remove Pd_session::Native_pd definition from API
This type can be a forward declaration in the public API because its
definition is required only in kernel-specific code.

Fixes #3979
2021-01-25 12:51:54 +01:00
Tomasz Gajewski
98798f18b5 Fix minor inconsistencies in mk files
Fixes #3972
2021-01-25 12:50:54 +01:00
Christian Helmuth
1bef11accf depot: update recipe hashes 2020-12-18 09:10:52 +01:00
Christian Helmuth
f2e0c164c2 depot: update recipe hashes 2020-11-27 09:21:06 +01:00
Alexander Boettcher
774b1f4277 base: remove Thread_deprecated
Fixes #3954
2020-11-27 09:19:08 +01:00
Piotr Tworek
5db2971903 base-hw/arm_v7a: Mark r1 as out in Kernel::call64
In case of arm_v7a Kernel::call64 the syscall will use both r0 and r1 as
output registers. Unfortunately the inline asm does not reflect this and
only r0 is explicitly specified as output. GCC manages to produce output
which we'd like to see. Clang on the other hand takes adventage of the fact
r1 should not be touched by swi and produces fewer instructions which do
what the code describes, but not what we actually want.

Basically the code which we want and is generated by GCC is:
  svc     0
  mov     r2, r0
  mov     r0, r1
  mov     r1, r2
  bx      lr

Clang on the other hand generates correct assembly given the code, but
incorrect given what the function is supposed to do:
  svc     0
  mov     r1, r0
  mov     r0, #0
  bx      lr

Both GCC and clang generate the same, expected assembly output when r1
is marked as output register from the inline asm swi call.

Fixes #3951
2020-11-27 09:19:08 +01:00
Piotr Tworek
50ab86cd72 base-hw: Remove unused rdtsc function for x86_64
This function has no callers. Clang warns about this.

Issue #3950
2020-11-27 09:19:08 +01:00
Piotr Tworek
a892018926 base-hw: Define Entry function as noreturn.
Right now the code marks specific instance of this function as noreturn.
It then tries to initialize it using a value that has the same type,
except for the noreturn part. GCC does not care, but clang complains this
technically assigns the value of entry from incompatible pointer type.

Fix this by defining Entry function as no return.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
1643d623e4 base-hw: Fix warning about unused lambda capture
The lambda function passed to Board::Vm_page_table_array does not
actually use "this" for anything. GCC does not warn about this, but
clang does. Remove the extra capture to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Piotr Tworek
9b84a8a402 base-hw: Add semicolons after [[fallthrough]]
GCC doesn't care, but clang complains if [[fallthrough]] is not followed
by a semicolon. Existing code is also not consitent in this regard. Lets
just fix it to make clang happy.

Issue #3938
2020-11-23 12:02:59 +01:00
Stefan Kalkowski
7298b00013 base-hw: make ARMv7/v8 hypervisor smp ready
* Introduce hypervisor-stack per CPU
* Introduce host world context per CPU
* Mark EL2 translation table memory as inner shareable
* The VMID is not bound to a single VCPU, but to the Vm_session as a whole
* Set affinity of the VCPU accordingly
* Add VMPIDR to VM state

Ref #3926
2020-11-23 12:02:58 +01:00
Stefan Kalkowski
1d826a2c48 base-hw: do direct syscall when run/pause a VCPU
Instead of calling core to run/pause a VCPU, go directly to the kernel.
Apart from the performance win, it would otherwise involve a more complex
protocol, when a VCPU on another core has to be removed from the scheduler.
Core's entrypoint handling those request runs on the boot-cpu only.

Ref #3926
2020-11-23 12:02:58 +01:00
Stefan Kalkowski
40445d7011 base: extend vm_session API with native vcpu cap
To enable the interaction of a VMM with the kernel directly,
a hidden RPC gets introduced. It allows a kernel-specific
base-library implementation of the Vm_session::Client to request
a kernel-specific capability to address a VCPU, e.g., to
run/stop it.

Ref #3926
2020-11-23 12:02:58 +01:00
Christian Prochaska
798beab30e base: support process-local signal submission
Issue #3923
2020-11-23 12:02:53 +01:00
Christian Prochaska
50e0f3b977 base: don't throw exceptions in 'Signal_receiver::pending_signal()'
Issue #3922
2020-11-23 12:02:49 +01:00
Christian Helmuth
5be1c793a5 depot: update recipe hashes 2020-10-23 14:16:38 +02:00
Christian Helmuth
91f8281618 depot: update recipe hashes 2020-10-09 13:35:57 +02:00
Sebastian Sumpf
27f705bc48 bootstrap: iomux adaptions for i.MX8 MIPI
These settings were obtained with a JTAG debugger from a running Linux
system. They work for MIPI as well as for HDMI.

issue #3900
2020-10-09 13:35:56 +02:00
Martin Stein
7feea78991 timeout: rework timeout framework
* get rid of alarm abstraction
* get rid of Timeout::Time type
* get rid of pointer arguments
* get rid of _discard_timeout indirection
* get rid of 65th bit in stored time values
* get rid of Timeout_scheduler interface
* get rid of uninitialized deadlines
* get rid of default arguments
* get rid of Timeout::_periodic
* get rid of Timeout::Raw
* use list abstraction
* only one interface for timeout handlers
* rework locking scheme to be smp safe
* move all method definitions to CC file
* name mutexes more accurate
* fix when & how to set time-source timeout
* fix deadlocks

Fixes #3884
2020-10-09 13:35:56 +02:00
Stefan Kalkowski
bbb017dc24 muen: update to Community 2019 toolchain version
Fix #3903
2020-10-09 13:35:55 +02:00
Alexander Boettcher
90bea1499e core: store new affinity on successful migration
Adjust the base-* platforms to acknowledge new thread location solely if
migration is supported and succeeded. Otherwise the wrong thread
locations are observed via the trace session and utilization time calculation
get wrong.

Issue #3842
2020-10-09 13:33:36 +02:00
Martin Stein
1b41d9db90 base: remove alarm library from base
Ref #3884
2020-10-09 13:33:36 +02:00
Christian Helmuth
c59c266afc depot: update recipe hashes 2020-09-17 14:23:14 +02:00
Stefan Kalkowski
d7eb174c88 muen: fix building on modern devel distros
* Use python2 interpreter not available by default explicitely
* Update ada-bfd binding library to meet binutils-dev >= 2.34
2020-09-17 10:14:07 +02:00
Christian Helmuth
c649307720 depot: update recipe hashes 2020-08-28 08:29:12 +02:00
Norman Feske
7d0cb9620b depot: update recipe hashes 2020-08-25 11:50:41 +02:00
Stefan Kalkowski
5f5ad41ad3 hw: unify irq enumeration for Raspberri Pi
By now, the enumeration of peripheral interrupts on Raspberry Pi 1 was
different in between base-hw kernel and Fiasco.OC. Therefore, hacks were
needed in every driver to request the correct interrupt number dependent
on the kernel. Before reproducing the same in the platform driver for rpi,
we can more easily use the same enumeration with base-hw.

Ref #3864
2020-08-25 11:50:12 +02:00
Stefan Kalkowski
70f98fcc44 hw: implement Pd_session::managing_system for ATF
To access the ARM Trusted Firmware from the platform driver
fill the new `managing_system` call of the PD session with life resp.
do a SMC call on behalf of the client.

Fix #3816
2020-08-25 11:50:11 +02:00
Christian Prochaska
fd682cd470 hw: check descriptor validity in LPAE lookup
Fixes #3828
2020-07-30 08:49:23 +02:00
Alexander Boettcher
41380ff769 base: remove Cancelable_lock
- base/cancelable_lock.h becomes base/lock.h
- all members become private within base/lock.h
- solely Mutex and Blockade are friends to use base/lock.h

Fixes #3819
2020-07-30 08:49:23 +02:00
Norman Feske
de795b1a6e depot: update recipe hashes 2020-07-13 11:33:53 +02:00
Alexander Boettcher
f3efbe50bb base: remove deprecated cancel_blocking() support
for threads.

Fixes #3806
2020-07-13 11:33:12 +02:00
Norman Feske
4450b37ff5 depot: update recipe hashes 2020-06-29 14:25:28 +02:00
Stefan Kalkowski
1f91fd3f7d hw: scale imx8q_evk cpu to 1.5 GHz 2020-06-29 14:25:27 +02:00
Norman Feske
eb3a81a874 depot: update recipe hashes 2020-06-22 09:39:41 +02:00
Stefan Kalkowski
04d8c859d8 hw: enable branch predictor on rpi
* Z-bit was never enabled for rpi1
* Write buffer, and TCM bits are deprecated in this processor generation
  so do not use them

Ref #3247
2020-06-22 09:39:40 +02:00
Christian Helmuth
6006051fb9 depot: update recipe hashes 2020-05-27 11:56:47 +02:00
Norman Feske
0f27d139bd depot: update recipe hashes 2020-05-18 10:16:59 +02:00
Norman Feske
dd899fde29 depot: update recipe hashes 2020-04-24 14:37:57 +02:00
Norman Feske
b134867f31 Remove Rpc_entrypoint::Native_context
This patch largely reverts the commit "base: lay groundwork for
base-linux caps change" because the use of 'epoll' instead of 'select'
alleviated the need to allocate large FD sets, which motivated the
introduction of the 'Native_context' hook.

Related to issue #3581
2020-04-21 16:50:37 +02:00
Stefan Kalkowski
9f28f4f803 hw: avoid BASE_DIR relative path definitions
Fix #3728
2020-04-17 12:55:13 +02:00
Stefan Kalkowski
0e49336b96 Retire Exynos 5 support (fix #3725) 2020-04-17 12:53:57 +02:00
Stefan Kalkowski
941e918b46 vmm: unify armv7/v8 virtualization
Fix #3638
2020-04-17 12:52:02 +02:00
Stefan Kalkowski
74e75d7fbc hw: enable virtualization support for virt_qemu
Ref #3638
2020-04-17 12:51:53 +02:00
Stefan Kalkowski
58db6542f8 hw: check for security extension support in GICv2
Ref #3638
2020-04-17 12:51:44 +02:00
Christian Helmuth
b60b591d06 depot: update recipe hashes 2020-04-17 12:40:13 +02:00
Stefan Kalkowski
ff378a8c5b hw: cache maintainance on mapping removal too
Older ARM processors like ARMv6, or Cortex A8 need to write back changes
of the page-tables to physical ram because the MMU does not use the cache.
This naturally needs to be done not only when adding a mapping,
but on removal too.

Fix #3715
2020-04-17 12:40:13 +02:00
Alexander Boettcher
3956530634 base: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
Alexander Boettcher
e87d60ddf7 core: use Mutex/Blockade
Issue #3612
2020-04-17 12:40:12 +02:00
Stefan Kalkowski
f051065582 Retire OMAP4 support
Fix #2850
2020-04-17 12:39:32 +02:00
Piotr Tworek
585c4b8c69 hw: Add support for Qemu virt arm platforms.
This patch adds support for booting base-hw kernel on qemu-arm virt
machines. The arm_virt machine has 2GB of RAM, 2 Cortex A15 cores and
uses GICv2 interrupt controller. The arm_64_virt machine also has 2GB of
RAM, but has 4 Cortex A53 cores and uses GICv3. Both machines use PSCI
to boot additional CPU cores.

Fixes #3673
2020-04-17 12:39:32 +02:00
Piotr Tworek
dad1de1865 hw: Add interface for making basic ARM PSCI calls.
So far this only exposes two functions allowing the code to turn on
additional CPUs. There is much more functionality defined by PSCI spec
but so far its not needed by Genode.

Fixes #3672
2020-04-17 12:39:32 +02:00
Norman Feske
46fa8197a2 depot: update recipe hashes 2020-03-26 11:39:02 +01:00
Stefan Kalkowski
256b2fa3e1 hw: cortex a9 diagnostic register fixup
This is a follow-up fix for commit 202333c881.
It checks for the diagnostic registers being already setup correctly.
Otherwise on platforms with secure firmware, like Pandaboard it will stuck.

Ref #3639
2020-03-26 11:39:02 +01:00
Norman Feske
0f3ac4cb9f base-hw: let upgrade_cap_slab reflect Out_of_caps
This patch reflects the Out_of_caps exception from core to the client,
in addition to the already covered Out_of_ram exception. It thereby
eliminates a potential abort in core, which I observed with the
tool_chain_auto.run script:

  Kernel: RPC upgrade_cap_slab
  Error: Uncaught exception of type 'Genode::Quota_guard<Genode::Cap_quota>::Limit_exceeded'
  Warning: abort called - thread: entrypoint

In addition to propagating the exception, the patch add the client-side
exception-handling code to the base library.

Fixes #3703
2020-03-26 11:38:59 +01:00
Stefan Kalkowski
6d48b5484d hw: correct the ARM cache maintainance operations
This commit fixes the following issues regarding cache maintainance
under ARM:

* read out I-, and D-cache line size at runtime and use the correct one
* remove 'update_data_region' call from unprivileged syscalls
* rename 'update_instr_region' syscall to 'cache_coherent_region' to
  reflect what it doing, namely make I-, and D-cache coherent
* restrict 'cache_coherent_region' syscall to one page at a time
* lookup the region given in a 'cache_coherent_region' syscall in the
  page-table of the PD to prevent machine exceptions in the kernel
* only clean D-cache lines, do not invalidate them when pages where
  added on Cortex-A8 and ARMv6 (MMU sees phys. memory here)
* remove unused code relicts of cache maintainance

In addition it introduces per architecture memory clearance functions
used by core, when preparing new dataspaces. Thereby, it optimizes:

* on ARMv7 using per-word assignments
* on ARMv8 using cacheline zeroing
* on x86_64 using 'rept stosq' assembler instruction

Fix #3685
2020-03-26 11:38:55 +01:00
Alexander Boettcher
e096202b1f hw/x86: use PAT for write combining support
Fixes #3623
2020-03-26 11:38:54 +01:00
Alexander Boettcher
44ace04b95 hw/x86: add cpuid register macro
Issue #3623
2020-03-26 11:38:54 +01:00
Alexander Boettcher
507a34b3d0 hw/x86: implement wrmsr in macro
Issue #3623
2020-03-26 11:38:54 +01:00
Christian Helmuth
5affd51250 depot: update recipe hashes 2020-02-28 08:59:43 +01:00
Stefan Thöni
a7a9855493 base: lay groundwork for base-linux caps change
Include the necessary hooks to introduce file descriptor
based capabilities in base linux.

Issue #3581
2020-02-27 14:46:58 +01:00
Christian Helmuth
4cccf74664 depot: update recipe hashes 2020-02-20 12:11:23 +01:00
Stefan Kalkowski
8cc48d5688 hw: be more accurate in synchronizing ASID/Pages
Fix #3651
2020-02-20 12:11:23 +01:00
Alexander Boettcher
5440cd4b50 base: use blockade in thread
Issue #3612
2020-02-20 12:11:22 +01:00
Alexander Boettcher
00f69bc70d base: add mutex as derivate of lock
The mutex class is more restrictive in usage compared to
Genode::Lock.

- At initialiation time it is ever unlocked.
- No thread is permitted to lock twice. Warn about it
  in case it happens.
- Only the lock onwer is permitted to unlock the mutex.
  Warn about it and don't unlock the mutex in case it happens.

Issue #3612
2020-02-20 12:11:22 +01:00
Stefan Kalkowski
725d16e18e hw: optimize ipc capability allocation
In preparation of ipc receive, by now a bunch of capabilities got
allocated to be ready iin case of capability receiption. After that
unuse slots were freed again. This overhead of senseless (de-)allocations
is replaced in this commit by just restock capability slots that got
used by the last receive.

Fix #3640
2020-02-20 12:11:22 +01:00
Martin Stein
e42a205a51 base-hw: Ada-compliant scheduler method signatures
Ref #3308
2020-02-20 12:11:22 +01:00
Martin Stein
0d5f185267 base-hw: no pointers in scheduler interface
Ref #3308
2020-02-20 12:11:22 +01:00
Martin Stein
c146a215fb base-hw: cpu scheduler without inheritance
Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
eef7b5e168 base-hw: double list without inheritance
Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
a753b6ce46 base-hw: fix run scripts
Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
793e12f8f3 base-hw: no error return codes in signaling
Error return codes are used with non-const functions in the signaling modules.
This would have been impractical for the in-place translation of the module to
Ada in the context of the Spunky project. Besides, it is easy to get rid of
them and it makes the execution flow more clear.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
751e6430fa base-hw: obsolete Kernel::Thread::_signal_receiver
Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
9eb20c2be7 base-hw: no pointer arguments in signaling
Besides reducing the use of pointers in base-hw, this prepares for the in-place
translation of the signaling module to Ada in the context of the Spunky
project.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
5e460394d2 base-hw: do not inherit Kernel::Object
This prevents the use of Kernel::Object as base class for the specific kernel
objects and instead makes it a member of the kernel objects. Besides
simplifying inheritance hierarchies in base-hw, this prepares for the in-place
translation of the signaling module (and others) to Ada in the context of the
Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
88043e144a base-hw: no virtual functions in signaling
Besides simplifying the execution flow in the signaling module, this prepares
for the in-place translation of the signaling module to Ada in the context of
the Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
3cc7774fe4 base-hw: Ada/SPARK-friendly Ipc_node interface
This prevents the use of C++ features in the public method interface of the
synchronous-IPC module that would be impractical for the in-place
translation of the module into Ada in the context of the Spunky project.

* Get rid of thread accessor.
* Get rid of non-const functions with return values.
* Get rid of pointer return-values.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
a04243aaf4 base-hw: remove unused Ipc_node accessor methods
Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
5a95183c3e base-hw: avoid that Ipc_node inherits
Besides simplifying inheritance hierarchies in base-hw, this prepares for the
in-place translation of the synchronous-IPC module to Ada in the context of the
Spunky project.

Ref #3308
2020-02-20 12:11:21 +01:00
Martin Stein
6a5aa18a7b base-hw: no PD code / virt methods in Ipc_node
This is a simplication of the asyncronous-IPC module of the base-hw kernel.
Besides structuring the code in a cleaner way, it prepares for the in-place
translation of the module into Ada in the context of the Spunky project.

* Get rid of virtual methods in Ipc_node.
* Move all stuff related to protection domains, capabilities, and UTCBs to
  the Thread class. this code might later be moved to a dedicated module, but
  for now it's just fine to have it done by the thread module.

Ref #3308
2020-02-20 12:11:21 +01:00
Stefan Kalkowski
79fba6c2ac core: add kernel-specific UTCB quota bookkeeping
Fix #859
2020-02-20 12:11:21 +01:00
Tomasz Gajewski
4f217b19a9 hw: add CPU wake up code for rpi3
Moved code waking up processors for Cortex A53 before changing privilege
level because sending events to higher privilege levels is not allowed.

Fixed enable_mmu for Cortex A53 to properly return cpu id.

Fixed starting code for secondary cores to properly initialize stacks.

Added code to wake up secondary cores on rpi3.

Ref #3573
2020-02-20 12:08:17 +01:00
Stefan Kalkowski
202333c881 hw: cortex a9 diagnostic register initialization
We cannot count on the correct initialization of the diagnostic register
of the secondary cores. But the boot core gets initialized by the bootchain,
so we can copy over those values.

Fix #3639
2020-02-20 12:08:17 +01:00
Norman Feske
57ea1dbdd3 depot: update recipe hashes 2020-02-10 14:29:06 +01:00
Stefan Kalkowski
56ef7ca9e7 hw: enable ARMv8 performance counter
Fix #3618
2020-02-04 16:05:01 +01:00
Christian Helmuth
90535a1401 depot: update recipe hashes 2020-02-04 15:51:10 +01:00
Alexander Boettcher
7b964fa700 base: add affinity space info to platform info
Issue #3599
2020-02-04 15:51:10 +01:00
Sebastian Sumpf
1902d1a06b hw: do not map boot modules in bootstrap
This commit safes virtual address space.
2020-02-04 15:51:08 +01:00
Norman Feske
beb8bf498c base-hw: add explicit array-bounds check
This patch rules out out-of-bounds array accesses without inspecting the
caller. It is not a bug fix but adds clarity.
2020-02-04 15:51:08 +01:00
Norman Feske
de764d8490 base-hw/muen: add explicit array-bounds check 2020-02-04 15:51:08 +01:00
Norman Feske
5635c1318c base-hw: explicit bounds check in store_apic_id
Avoid relying on the caller regarding the CPU index argument to ease the
reasoning about the code.
2020-02-04 15:51:08 +01:00
Christian Helmuth
b931b67cba depot: update recipe hashes 2019-12-19 17:01:43 +01:00
Alexander Boettcher
e54ff599ca base-hw: trace execution time of core threads
Fixes #3572
2019-12-19 17:01:43 +01:00
Sebastian Sumpf
04969b6be0 base-hw: add trace execution time support
This enables the 'top' program on base-hw for debugging issue #3247 on
rpi.

Fixes #3572
2019-12-19 17:01:42 +01:00
Emery Hemingway
648382db74 Align after template expansion
Clang Cannot align template structs. Also, cannot cast void* to addr_t
in constexpr function.

Issue #3564
2019-12-19 16:59:03 +01:00
Emery Hemingway
2c510bb7f9 Remove unused lamba capture to fix clang warning
Issue #3564
2019-12-19 16:59:03 +01:00
Christian Helmuth
11ef8e1ff2 depot: update recipe hashes 2019-11-28 09:06:39 +01:00
Stefan Kalkowski
4800bcf5a0 hw: correct the i.MX6 Sabrelite timer settings
Fix #3561
2019-11-25 15:43:59 +01:00
Christian Prochaska
57d080d4f8 hw: use correct type on IRQ kernel object destruction
Fixes #3560
2019-11-25 14:15:39 +01:00
Stefan Kalkowski
af29dcf557 hw: introduce virtualization support for ARMv8
Ref #3553
2019-11-21 14:29:36 +01:00
Stefan Kalkowski
f82714f341 vm_session: return vcpu id when creating vcpu
Ref #3553
2019-11-21 14:29:36 +01:00
Stefan Kalkowski
02d68fdb97 hw: move arm virtualization to generic place
Ref #3553
2019-11-21 14:29:36 +01:00
Stefan Kalkowski
065b9fdb46 base-hw: extend syscalls to five arguments
Ref #3553
2019-11-21 14:29:36 +01:00
Christian Helmuth
7ed1d7f11d depot: update recipe hashes 2019-11-19 14:54:14 +01:00
Stefan Kalkowski
8a8aa85726 hw: initialize iomux, ccm and gpc for i.MX8 EVK
Fix #3534
2019-11-19 14:42:23 +01:00
Stefan Kalkowski
105b2c9b7a hw: fix gicv3 implementation of clear/set regs
In addition use uniformly enums for interupt count in register declarations.

Fix #3532
2019-11-19 14:42:23 +01:00
Stefan Kalkowski
f6435d91fc hw: turn Kernel_object into Genode::Constructible
Fix #3531
2019-11-19 14:42:23 +01:00
Stefan Kalkowski
3e3fb63863 hw: enable Genode::raw for bootstrap
Ref #3531
2019-11-19 14:42:23 +01:00
Stefan Kalkowski
87a6368ba1 hw: implement multi-processor support for rpi3
Fix #3522
2019-11-19 14:42:22 +01:00
Stefan Kalkowski
1cbd77c806 hw: implement multi-processor support for i.MX8
Fix #3520
2019-11-19 14:42:22 +01:00
Stefan Kalkowski
e3f82b09d7 hw: instantiate pic object per cpu
Ref #3520
2019-11-19 14:42:22 +01:00
Christian Helmuth
4a7b0e99a6 depot: update recipe hashes 2019-09-20 14:14:16 +02:00
Christian Helmuth
b2c59576ae depot: update recipe hashes 2019-08-28 14:36:56 +02:00
Christian Helmuth
312f801f8a depot: update recipe hashes 2019-08-21 13:25:26 +02:00
Sebastian Sumpf
e855638266 hw: add system call for irq mode setting
Core is not allowd to access the kernel's Pic implementation directly.

fixes #3474
2019-08-21 13:25:25 +02:00
Christian Helmuth
1c77ea2b03 base-hw: remove other board libs from recipes 2019-08-13 12:02:27 +02:00
Christian Prochaska
4c113182b0 depot: add recipe for base-hw-imx8q_evk
Issue #3426
2019-08-13 12:02:27 +02:00
Stefan Kalkowski
7ced122ddc hw: support for i.MX8M Quad EVK
Fix #3426
2019-08-13 12:02:27 +02:00
Stefan Kalkowski
6b09ac59f0 hw: enable performance counter for ARMv8
Ref #3426
2019-08-13 12:02:27 +02:00
Stefan Kalkowski
ee38504d81 hw: implement update_data_region for ARMv8
Ref #3426
2019-08-13 12:02:26 +02:00
Sebastian Sumpf
dd505edd19 hw: GICv3 implementation
* modern GICv3 implementation
* distributor
* redistributor
* MMIO cpu interface

Ref #3426
2019-08-13 12:02:26 +02:00
Stefan Kalkowski
fa1aa33f83 hw: sanitize arm trustzone/virtualization services
Those services are not SoC specific and have to reside at a generic place.

Fix #3445
2019-08-13 12:02:26 +02:00
Stefan Kalkowski
907de9d37f hw: move timer into board.h
Unify the generic timer implementation for ARMv7 and ARMv8.

Ref #3445
2019-08-13 12:02:26 +02:00
Stefan Kalkowski
5c7436bf10 hw: remove SMP variable from board.h
Whether an SoC has the multiprocessing extensions can be read out
from the identification registers, and does not need to be specified
in each board header.

Ref #3445
2019-08-13 12:02:26 +02:00
Stefan Kalkowski
0b77e8ea62 hw: consistently move cpu into board namespace
Ref #3445
2019-08-13 12:02:26 +02:00
Stefan Kalkowski
875858b2cc hw: integrate interrupt controllers into board.h
Additionally, unify more implementation details in between different
usage patterns of ARM's generic interrupt controller (v2)

Ref #3445
2019-08-13 12:02:26 +02:00
Martin Stein
b87e21a392 base-hw: EFI sys-table pointer in platform info
Ref #3430
2019-08-13 12:02:03 +02:00
Christian Helmuth
17d32b3e15 depot: update recipe hashes 2019-07-09 09:06:54 +02:00
Stefan Kalkowski
186c35bb09 depot: recipe for base-hw-rpi3
Ref #3407
2019-07-09 08:55:23 +02:00
Stefan Kalkowski
90d07741aa hw: support for ARM64 Raspberry Pi 3
Restriction: enables only cpu core 0 and the timer interrupt by now.

Fix #3405
2019-07-09 08:55:22 +02:00
Stefan Kalkowski
87015df66c hw: change update_pd to invalidate_tlb
In the past, the core-only privileged syscall `update_pd` was used only
to invalidate the TLB after removal of page-table entries.
By now, the whole TLB at least for one protection domain got invalidated,
but in preparation for optimization and upcomingARM v8 support,
it is necessary to deliver the virtual memory region that needs to get
invalidated. Moreover, the name of the call shall represent explicitely
that it is used to invalidate the TLB.

Ref #3405
2019-07-09 08:55:22 +02:00
Stefan Kalkowski
d9a0f76e7a hw: extend long-descriptor page table format
Ref #3405
2019-07-09 08:55:22 +02:00
Christian Helmuth
3c4c460f82 depot: update recipe hashes 2019-06-13 13:40:37 +02:00
Christian Helmuth
2b183f9497 depot: update recipe hashes 2019-05-29 10:20:52 +02:00
Sebastian Sumpf
cec050983a hw: [[fallthrough]] annotations for ARM/RISC-V
* double checked

issue #3377
2019-05-29 10:20:52 +02:00
Sebastian Sumpf
d417d26ce8 hw: fix calculation of CPU count on x86_64
On x86 the CPU count is determined through ACPI's MADT by counting the
local APICs reported there. Some platforms report more APICs
than there are actual CPUs. These might be physically disabled CPUs.
Therefore, a check if the LAPIC is actually physically enabled in
hardware fixes this issue.

Thanks to Alex Boettcher

fixes #3376
2019-05-29 10:20:52 +02:00
Sebastian Sumpf
5611020f33 hw: fix stack alignment in bootstrap for x86_64
Fix initial stack pointer alignment for x86_64 in crt0.s startup code of
bootstrap. SysV ABI states that upon function entry (rsp + 8) % 16 = 0.
There, we have to align the stack to 16 bytes before all 'call'
instruction not 8. Otherwise FPU (GP) exception might be raised later on
because of unaligned FPU accesses.

issue #3365
2019-05-29 10:20:52 +02:00
Sebastian Sumpf
da17f2cbd3 hw: eager FPU switching for x86_64
Since gcc 8.3.0 generates SSE instructions into kernel code, the
kernel itself may raise FPU exceptions and/or corrupt user level FPU
contexts thereby. Both things are not feasible, and therefore, lazy FPU
switching becomes a no go for base-hw because we cannot avoid FPU
instructions because of the entanglement of base-hw, base, and the tool
chain (libgcc_eh.a).

issue #3365
2019-05-27 14:53:32 +02:00
Stefan Kalkowski
6d8d6b5552 hw: disable alignment checking at earliest
Fix #3370
2019-05-27 14:52:52 +02:00
Sebastian Sumpf
f18285205c hw: enable FPU during CPU startup on x86
Also disable TS (task switch) flag in cr0 during kernel initialization,
so FPU faults are not raised. This became necessary since GCC lately
aggressively generates FPU instructions at arbitrary places and also at
early kernel-bootstrapping stages.

fixes #3365
2019-05-27 14:52:52 +02:00
Christian Prochaska
4fc3eca4aa base-hw: fix compile errors with GCC 8.3.0
Fixes #3326
2019-05-27 14:46:54 +02:00
Stefan Kalkowski
5c77ebb1fb hw: factor out x86 specific bootinfo
Ref #3326
2019-05-27 14:46:54 +02:00
Stefan Kalkowski
054df95ea4 hw: unify board definitions of bootstrap/core
Ref #3326
2019-05-27 14:46:54 +02:00
Adrian-Ken Rueegsegger
d131e537e9 Update Muen port
- Drop unnecessary patch
- Improved build speed/parallelization
- Increased log channel size
- Fix path in base-hw/Muen documentation
2019-05-27 14:46:53 +02:00
Stefan Kalkowski
a1e70b9ba4 kernel: differentiate board-specific components
Components like kernel, core, and bootstrap that are built for a
specific board need to reside inside the same architectural dependent
build directory. For instance there are sel4, foc, and hw kernel builds
for imx6q_sabrelite and imx7d_sabre, which have to reside inside the same
arm_v7 build directory.
This commit names those components explicitely, and adapts the run-tool to it.

Fix #3316
2019-05-27 14:46:52 +02:00
Stefan Kalkowski
c43267dbaa tool: deprecate board-specific build directories
* Introduces BOARD variable to determine actual board
* Removes formerly deprecated kernel-specific build directories

The following boards are available:

arm_v6: rpi
arm_v7a: arndale, imx53_qsb, imx53_qsb_tz, imx6q_sabrelite, imx7d_sabre,
         nit6_solox, odroid_x2, odroid_xu, panda, pbxa9, usb_armory,
         wand_quad, zynq_qemu
x86_64: pc, linux, muen
x86_32: pc, linux
riscv:  spike

Ref #3316
2019-05-27 14:46:29 +02:00
Stefan Kalkowski
13fb51eecf hw: remove implicit SoC-specific include path
Fix #3336
2019-05-16 13:11:02 +02:00
Christian Helmuth
ba51800b31 depot: update recipe hashes 2019-05-06 16:15:27 +02:00
Stefan Kalkowski
f42c21f16b platform_info: add kernel information (fix #3295) 2019-05-06 16:15:26 +02:00
Alexander Boettcher
05fa063068 vm_session: support to trace vCPU
Issue #3111
2019-05-06 16:15:26 +02:00
Martin Stein
181c78d482 timeout: use uint64_t for all plain time values
This enforces the use of unsigned 64-bit values for time in the duration type,
the timeout framework, the timer session, the userland timer-drivers, and the
alarm framework on all platforms. The commit also adapts the code that uses
these tools accross all basic repositories (base, base-*, os. gems, libports,
ports, dde_*) to use unsigned 64-bit values for time as well as far as this
does not imply profound modifications.

Fixes #3208
2019-05-06 16:15:26 +02:00
Stefan Kalkowski
e072ee480b depot: add recipe for base-hw-imx7d_sabre
Fix #3293
2019-05-06 16:15:26 +02:00