mirror of
https://github.com/genodelabs/genode.git
synced 2025-02-20 09:46:20 +00:00
riscv: Use Qemu and update to ISA v1.10
- remove Spike/BBL support in favour of Qemu (>=4.2.1) - add 'riscv_qemu' board, remove 'spike' board' - update to privileged ISA v1.10 (from v1.9.1) - use direct system calls for privileged core threads (they call into the kernel and don't use mode changing system calls, i.e. 'ecall', semantics) - use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of BBL issue #4012
This commit is contained in:
Sebastian Sumpf
Norman Feske
parent
18e282ab8a
commit
fd0e6685fc
@ -1 +0,0 @@
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0x81000000
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1
repos/base-hw/board/riscv_qemu/image_link_address
Normal file
1
repos/base-hw/board/riscv_qemu/image_link_address
Normal file
@ -0,0 +1 @@
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0x80200000
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@ -23,20 +23,23 @@ namespace Genode { struct Cpu_state; }
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struct Genode::Cpu_state
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{
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enum Cpu_exception {
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INSTRUCTION_UNALIGNED = 0,
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INSTRUCTION_PAGE_FAULT = 1,
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INSTRUCTION_ILLEGAL = 2,
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BREAKPOINT = 3,
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LOAD_UNALIGNED = 4,
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LOAD_PAGE_FAULT = 5,
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STORE_UNALIGNED = 6,
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STORE_PAGE_FAULT = 7,
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ECALL_FROM_USER = 8,
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ECALL_FROM_SUPERVISOR = 9,
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ECALL_FROM_HYPERVISOR = 10,
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ECALL_FROM_MACHINE = 11,
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RESET = 16,
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IRQ_FLAG = 1UL << 63,
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INSTRUCTION_UNALIGNED = 0,
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INSTRUCTION_ACCESS_FAULT = 1,
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INSTRUCTION_ILLEGAL = 2,
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BREAKPOINT = 3,
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LOAD_UNALIGNED = 4,
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LOAD_ACCESS_FAULT = 5,
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STORE_UNALIGNED = 6,
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STORE_ACCESS_FAULT = 7,
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ECALL_FROM_USER = 8,
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ECALL_FROM_SUPERVISOR = 9,
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ECALL_FROM_HYPERVISOR = 10,
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ECALL_FROM_MACHINE = 11,
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INSTRUCTION_PAGE_FAULT = 12,
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LOAD_PAGE_FAULT = 13,
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STORE_PAGE_FAULT = 15,
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RESET = 16,
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IRQ_FLAG = 1UL << 63,
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};
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addr_t ip = 0;
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@ -73,6 +76,12 @@ struct Genode::Cpu_state
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addr_t t5 = 0;
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addr_t t6 = 0;
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/*
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* Save last instruction fetch-fault needed for MIG-V stval quirk in
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* kernel/riscv/thread.cc
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*/
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addr_t last_fetch_fault = 0;
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bool is_irq() { return cpu_exception & IRQ_FLAG; }
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unsigned irq() { return cpu_exception ^ IRQ_FLAG; }
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};
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@ -7,8 +7,6 @@
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include $(BASE_DIR)/lib/mk/base-common.inc
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LIBS += syscall-hw
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SRC_CC += rpc_dispatch_loop.cc
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SRC_CC += thread.cc thread_myself.cc thread_bootstrap.cc
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SRC_CC += signal_transmitter.cc
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@ -9,4 +9,4 @@ SRC_CC += stack_area_addr.cc
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SRC_CC += native_utcb.cc
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SRC_CC += platform.cc
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LIBS += startup-hw base-hw-common cxx timeout-hw
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LIBS += startup-hw base-hw-common syscall-hw cxx timeout-hw
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@ -7,6 +7,8 @@
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# add include paths
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REP_INC_DIR += src/core/spec/arm
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LIBS += syscall-hw
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# add C++ sources
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SRC_CC += spec/32bit/memory_map.cc
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SRC_CC += spec/arm/kernel/cpu.cc
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@ -1,5 +1,7 @@
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REP_INC_DIR += src/core/spec/arm_v8
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LIBS += syscall-hw
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# add C++ sources
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SRC_CC += kernel/cpu_mp.cc
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SRC_CC += spec/64bit/memory_map.cc
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10
repos/base-hw/lib/mk/spec/riscv/bootstrap-hw-riscv_qemu.mk
Normal file
10
repos/base-hw/lib/mk/spec/riscv/bootstrap-hw-riscv_qemu.mk
Normal file
@ -0,0 +1,10 @@
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INC_DIR += $(REP_DIR)/src/bootstrap/board/riscv_qemu
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SRC_CC += bootstrap/spec/riscv/platform.cc
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SRC_S += bootstrap/spec/riscv/crt0.s
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SRC_CC += lib/base/riscv/kernel/interface.cc
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SRC_CC += spec/64bit/memory_map.cc
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vpath spec/64bit/memory_map.cc $(REP_DIR)/src/lib/hw
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include $(REP_DIR)/lib/mk/bootstrap-hw.inc
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@ -1,17 +0,0 @@
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#
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# evaluate bbl_dir immediately, otherwise it won't recognize
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# missing ports when checking library dependencies
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#
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REP_INC_DIR += src/bootstrap/spec/riscv
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INC_DIR += $(call select_from_ports,bbl)/src/lib/bbl
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SRC_CC += bootstrap/spec/riscv/platform.cc
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SRC_CC += lib/base/riscv/kernel/interface.cc
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SRC_CC += spec/64bit/memory_map.cc
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SRC_S += bootstrap/spec/riscv/crt0.s
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vpath spec/64bit/memory_map.cc $(call select_from_repositories,src/lib/hw)
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include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
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@ -1,11 +1,4 @@
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#
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# evaluate bbl_dir immediately, otherwise it won't recognize
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# missing ports when checking library dependencies
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#
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REP_INC_DIR += src/core/spec/riscv
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INC_DIR += $(call select_from_ports,bbl)/src/lib/bbl
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REP_INC_DIR += src/core/spec/riscv src/core/board/riscv_qemu
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CC_OPT += -fno-delete-null-pointer-checks
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@ -14,10 +7,11 @@ SRC_CC += platform_services.cc
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += kernel/cpu_up.cc
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SRC_CC += kernel/lock.cc
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SRC_CC += spec/riscv/cpu.cc
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SRC_CC += spec/riscv/kernel/thread.cc
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SRC_CC += spec/riscv/kernel/cpu.cc
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SRC_CC += spec/riscv/kernel/interface.cc
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SRC_CC += spec/riscv/kernel/pd.cc
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SRC_CC += spec/riscv/cpu.cc
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SRC_CC += spec/riscv/platform_support.cc
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SRC_CC += spec/riscv/timer.cc
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SRC_CC += spec/64bit/memory_map.cc
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@ -8,6 +8,8 @@
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# add include paths
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REP_INC_DIR += src/core/spec/x86_64
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LIBS += syscall-hw
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# add assembly sources
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SRC_S += spec/x86_64/crt0.s
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SRC_S += spec/x86_64/exception_vector.s
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@ -1 +0,0 @@
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b9358ccd68ac9fbb0ea49b22aa4dd08fdaae1978
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@ -1,8 +0,0 @@
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LICENSE := BSD-3-Clause
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VERSION := git
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DOWNLOADS := bbl.git
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URL(bbl) = https://github.com/skalk/bbl-lite.git
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REV(bbl) = 22300f2f0ea72b7f9228ca6743d4ebb12cf5a79b
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DIR(bbl) = src/lib/bbl
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@ -1,21 +0,0 @@
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/**
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* \brief Errno definitions
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* \author Sebastian Sumpf
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* \date 2017-08-24
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _ERRNO_H_
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#define _ERRNO_H_
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enum {
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ENOSYS = 38,
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};
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#endif /* _ERRNO_H_ */
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@ -1,22 +0,0 @@
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/**
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* \brief Placeholder for 'image.elf'
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* \author Sebastian Sumpf
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* \date 2017-08-24
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.section ".payload","a",@progbits
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.align 3
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.globl _payload_start, _payload_end
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_payload_start:
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#ifdef BBL_PAYLOAD
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.incbin BBL_PAYLOAD
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#endif
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_payload_end:
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@ -1,8 +0,0 @@
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#ifndef _LIMITS_H_
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#define _LIMITS_H_
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enum {
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ULONG_MAX = ~0UL
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};
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#endif /* _LIMITS_H_ */
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@ -1,7 +0,0 @@
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.section ".payload","a",@progbits
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.align 3
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.globl _payload_start, _payload_end
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_payload_start:
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.incbin BBL_PAYLOAD
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_payload_end:
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@ -1,28 +0,0 @@
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/**
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* \brief Base types
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* \author Sebastian Sumpf
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* \date 2017-08-24
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _STDINT_H_
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#define _STDINT_H_
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typedef unsigned long uintptr_t;
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned uint32_t;
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typedef unsigned long long uint64_t;
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typedef signed long long int64_t;
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typedef signed long ssize_t;
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typedef unsigned long size_t;
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#endif /* _STDINT_H_ */
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@ -1,24 +0,0 @@
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/**
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* \brief Stdio definitions
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* \author Sebastian Sumpf
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* \date 2017-08-24
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _STDIO_H_
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#define _STDIO_H_
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#include <stdarg.h>
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typedef unsigned long long uint64_t;
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int snprintf(char *, size_t, const char *, ...);
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int vsnprintf(char *, size_t, const char *, va_list);
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#endif /* _STDIO_H_ */
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@ -1,22 +0,0 @@
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/**
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* \brief String definitions
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* \author Sebastian Sumpf
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* \date 2017-08-24
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _STRING_H_
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#define _STRING_H_
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#include <stdint.h>
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void *memset(void *s, int c, size_t n);
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void *memcpy(void *dest, const void *src, size_t n);
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#endif /* _STRING_H_ */
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@ -1,33 +0,0 @@
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TARGET = bbl
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REQUIRES = riscv
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SRC_C = bbl.c \
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configstring.c \
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kernel_elf.c \
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logo.c \
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mtrap.c \
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minit.c \
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sbi_impl.c \
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snprintf.c \
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string.c \
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mentry.S \
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sbi_entry.S \
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sbi.S \
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image.S
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IMAGE_ELF ?= $(PRG_DIR)/dummy
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INC_DIR += $(PRG_DIR)
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CC_OPT_PIC =
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CC_C_OPT += -mcmodel=medany
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CC_OPT_image += -DBBL_PAYLOAD=\"$(IMAGE_ELF)\"
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LD_TEXT_ADDR = 0x80000000
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CONTRIB = $(call select_from_ports,bbl)/src/lib/bbl/bbl
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LD_SCRIPT_STATIC = $(CONTRIB)/bbl.lds
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vpath %.c $(CONTRIB)
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vpath %.S $(CONTRIB)
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@ -1,5 +1,5 @@
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/*
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* \brief Riscv spike specific board definitions
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* \brief RISC-V Qemu specific board definitions
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* \author Stefan Kalkowski
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* \date 2017-02-20
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*/
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@ -11,10 +11,10 @@
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
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#define _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
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#ifndef _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
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#define _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
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#include <hw/spec/riscv/board.h>
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#include <hw/spec/riscv/qemu_board.h>
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namespace Board { using namespace Hw::Riscv_board; }
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@ -22,4 +22,4 @@ template <typename E, unsigned B, unsigned S>
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void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
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{ }
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#endif /* _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_ */
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#endif /* _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_ */
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@ -19,15 +19,29 @@ using namespace Board;
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Bootstrap::Platform::Board::Board()
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:
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early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE } ),
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early_ram_regions(Memory_region { RAM_BASE, RAM_SIZE } ),
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core_mmio()
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{ }
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unsigned Bootstrap::Platform::enable_mmu()
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{
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using Sptbr = Hw::Riscv_cpu::Sptbr;
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Sptbr::write(Sptbr::Ppn::masked((addr_t)core_pd->table_base >> 12));
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using Satp = Hw::Riscv_cpu::Satp;
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using Sstatus = Hw::Riscv_cpu::Sstatus;
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/* disable supervisor interrupts */
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Sstatus::access_t sstatus = Sstatus::read();
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Sstatus::Sie::set(sstatus, 0);
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Sstatus::write(sstatus);
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/* set page table */
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Satp::access_t satp = 0;
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Satp::Ppn::set(satp, (addr_t)core_pd->table_base >> 12);
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/* SV39 mode */
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Satp::Mode::set(satp, 8);
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Satp::write(satp);
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asm volatile ("sfence.vma" : : : "memory");
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return 0;
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}
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@ -11,13 +11,16 @@
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__RISCV__BOARD_H_
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#define _CORE__SPEC__RISCV__BOARD_H_
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#ifndef _CORE__SPEC__RISCV_QEMU__BOARD_H_
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#define _CORE__SPEC__RISCV_QEMU__BOARD_H_
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#include <hw/spec/riscv/board.h>
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#include <hw/spec/riscv/qemu_board.h>
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#include <spec/riscv/pic.h>
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#include <spec/riscv/timer.h>
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namespace Board { using namespace Hw::Riscv_board; }
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#endif /* _CORE__SPEC__RISCV__BOARD_H_ */
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#include <spec/riscv/timer.h>
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||||
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||||
#endif /* _CORE__SPEC__RISCV_QEMU__BOARD_H_ */
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@ -1,11 +1,12 @@
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/*
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* \brief CPU driver
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* \brief CPU driver for RISC-V
|
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* \author Sebastian Sumpf
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* \author Stefan Kalkowski
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||||
* \date 2017-10-06
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*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2017 Genode Labs GmbH
|
||||
* Copyright (C) 2017-2021 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
@ -38,14 +39,15 @@ static Asid_allocator & alloc() {
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Mmu_context::Mmu_context(addr_t page_table_base)
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{
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Sptbr::Asid::set(sptbr, (Genode::uint8_t)alloc().alloc());
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Sptbr::Ppn::set(sptbr, page_table_base >> 12);
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Satp::Asid::set(satp, (Genode::uint8_t)alloc().alloc());
|
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Satp::Ppn::set(satp, page_table_base >> 12);
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Satp::Mode::set(satp, 8);
|
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}
|
||||
|
||||
|
||||
Mmu_context::~Mmu_context()
|
||||
{
|
||||
unsigned asid = Sptbr::Asid::get(sptbr);
|
||||
unsigned asid = Satp::Asid::get(satp);
|
||||
Cpu::invalidate_tlb_by_pid(asid);
|
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alloc().free(asid);
|
||||
}
|
||||
@ -57,21 +59,22 @@ void Genode::Cpu::switch_to(Mmu_context & context)
|
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* The sstatus register defines to which privilege level
|
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* the machin returns when doing an exception return
|
||||
*/
|
||||
bool user = Sptbr::Asid::get(context.sptbr);
|
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bool user = Satp::Asid::get(context.satp);
|
||||
Sstatus::access_t v = Sstatus::read();
|
||||
Sstatus::Spp::set(v, user ? 0 : 1);
|
||||
Sstatus::write(v);
|
||||
|
||||
/* change the translation table when necessary */
|
||||
//Sptbr::access_t sptbr = Sptbr::read();
|
||||
if (user /*&& sptbr != context.sptbr*/)
|
||||
Sptbr::write(context.sptbr);
|
||||
if (user) {
|
||||
Satp::write(context.satp);
|
||||
sfence();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Genode::Cpu::mmu_fault(Context &, Kernel::Thread_fault & f)
|
||||
{
|
||||
f.addr = Genode::Cpu::Sbadaddr::read();
|
||||
f.addr = Genode::Cpu::Stval::read();
|
||||
f.type = Kernel::Thread_fault::PAGE_MISSING;
|
||||
}
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@ class Genode::Cpu : public Hw::Riscv_cpu
|
||||
|
||||
struct Mmu_context
|
||||
{
|
||||
Sptbr::access_t sptbr = 0;
|
||||
Satp::access_t satp = 0;
|
||||
|
||||
Mmu_context(addr_t page_table_base);
|
||||
~Mmu_context();
|
||||
@ -75,7 +75,7 @@ class Genode::Cpu : public Hw::Riscv_cpu
|
||||
/*
|
||||
* Note: In core the address space id must be zero
|
||||
*/
|
||||
asm volatile ("sfence.vm\n");
|
||||
asm volatile ("sfence.vma\n");
|
||||
}
|
||||
|
||||
static void invalidate_tlb_by_pid(unsigned const /* pid */) { sfence(); }
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
j _kernel_entry
|
||||
|
||||
.p2align 8
|
||||
|
||||
.global _kernel_entry
|
||||
_kernel_entry:
|
||||
|
||||
# client context
|
||||
@ -63,4 +63,14 @@ _kernel_entry:
|
||||
.global idle_thread_main
|
||||
idle_thread_main:
|
||||
wfi
|
||||
|
||||
/*
|
||||
* MIG-V errata:
|
||||
* "Place 7 NOPs after WFI to ensure proper pipeline propagation"
|
||||
* Otherwise wfi will exit without an interrupt.
|
||||
*/
|
||||
.rept 7
|
||||
nop
|
||||
.endr
|
||||
|
||||
j idle_thread_main
|
||||
|
||||
140
repos/base-hw/src/core/spec/riscv/kernel/interface.cc
Normal file
140
repos/base-hw/src/core/spec/riscv/kernel/interface.cc
Normal file
@ -0,0 +1,140 @@
|
||||
/*
|
||||
* \brief Direct kernel interface for core
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2021-02-10
|
||||
*
|
||||
* System call bindings for privileged core threads. Core threads cannot use
|
||||
* hardware-system calls ('ecall') because machine mode (OpenSBI) will interpret
|
||||
* them as SBI calls from supvervisor mode (not system calls). Unknown SBI calls
|
||||
* will lead machine mode to either stopping the machine or doing the wrong thing.
|
||||
* In any case machine mode will not forward the 'ecall' to supervisor mode, it
|
||||
* does only so for 'ecall's from user land. Therefore, call the kernel
|
||||
* directly.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Genode includes */
|
||||
#include <kernel/interface.h>
|
||||
#include <base/log.h>
|
||||
#include <cpu/cpu_state.h>
|
||||
|
||||
using namespace Kernel;
|
||||
|
||||
|
||||
/************************************
|
||||
** Helper macros for kernel calls **
|
||||
************************************/
|
||||
|
||||
#define CALL_1_FILL_ARG_REGS \
|
||||
register Call_arg arg_0_reg asm("a0") = arg_0;
|
||||
|
||||
#define CALL_2_FILL_ARG_REGS \
|
||||
CALL_1_FILL_ARG_REGS \
|
||||
register Call_arg arg_1_reg asm("a1") = arg_1;
|
||||
|
||||
#define CALL_3_FILL_ARG_REGS \
|
||||
CALL_2_FILL_ARG_REGS \
|
||||
register Call_arg arg_2_reg asm("a2") = arg_2;
|
||||
|
||||
#define CALL_4_FILL_ARG_REGS \
|
||||
CALL_3_FILL_ARG_REGS \
|
||||
register Call_arg arg_3_reg asm("a3") = arg_3;
|
||||
|
||||
#define CALL_5_FILL_ARG_REGS \
|
||||
CALL_4_FILL_ARG_REGS \
|
||||
register Call_arg arg_4_reg asm("a4") = arg_4;
|
||||
|
||||
extern Genode::addr_t _kernel_entry;
|
||||
|
||||
/*
|
||||
* Emulate RISC-V hardware-system call using jump ('jalr') instead of
|
||||
* environment call ('ecall').
|
||||
*
|
||||
* - clear SIE in sstatus (supervisor interrupt enable)
|
||||
* - set scause to ECALL from supervisor mode
|
||||
* - set sepc to "1:"
|
||||
* - jump to '_kernel_entry
|
||||
*
|
||||
* After system call execution continues at "1:"
|
||||
*/
|
||||
#define CALL_1_SWI "li ra, 0x2 \n" \
|
||||
"csrc sstatus, ra\n" \
|
||||
"csrw scause, %2 \n" \
|
||||
"la %2, 1f \n" \
|
||||
"csrw sepc, %2 \n" \
|
||||
"jalr %1 \n" \
|
||||
"1: \n" \
|
||||
: "+r" (arg_0_reg) : "r" (&_kernel_entry), \
|
||||
"r" (Genode::Cpu_state::ECALL_FROM_SUPERVISOR)
|
||||
#define CALL_2_SWI CALL_1_SWI, "r" (arg_1_reg)
|
||||
#define CALL_3_SWI CALL_2_SWI, "r" (arg_2_reg)
|
||||
#define CALL_4_SWI CALL_3_SWI, "r" (arg_3_reg)
|
||||
#define CALL_5_SWI CALL_4_SWI, "r" (arg_4_reg)
|
||||
|
||||
|
||||
/******************
|
||||
** Kernel calls **
|
||||
******************/
|
||||
|
||||
Call_ret Kernel::call64(Call_arg arg_0)
|
||||
{
|
||||
CALL_1_FILL_ARG_REGS
|
||||
asm volatile(CALL_1_SWI : "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
|
||||
|
||||
Call_ret Kernel::call(Call_arg arg_0)
|
||||
{
|
||||
CALL_1_FILL_ARG_REGS
|
||||
asm volatile(CALL_1_SWI : "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
|
||||
|
||||
Call_ret Kernel::call(Call_arg arg_0,
|
||||
Call_arg arg_1)
|
||||
{
|
||||
CALL_2_FILL_ARG_REGS
|
||||
asm volatile(CALL_2_SWI: "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
|
||||
|
||||
Call_ret Kernel::call(Call_arg arg_0,
|
||||
Call_arg arg_1,
|
||||
Call_arg arg_2)
|
||||
{
|
||||
CALL_3_FILL_ARG_REGS
|
||||
asm volatile(CALL_3_SWI : "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
|
||||
|
||||
Call_ret Kernel::call(Call_arg arg_0,
|
||||
Call_arg arg_1,
|
||||
Call_arg arg_2,
|
||||
Call_arg arg_3)
|
||||
{
|
||||
CALL_4_FILL_ARG_REGS
|
||||
asm volatile(CALL_4_SWI : "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
|
||||
|
||||
Call_ret Kernel::call(Call_arg arg_0,
|
||||
Call_arg arg_1,
|
||||
Call_arg arg_2,
|
||||
Call_arg arg_3,
|
||||
Call_arg arg_4)
|
||||
{
|
||||
CALL_5_FILL_ARG_REGS
|
||||
asm volatile(CALL_5_SWI : "ra");
|
||||
return arg_0_reg;
|
||||
}
|
||||
@ -25,6 +25,7 @@ void Thread::Tlb_invalidation::execute() {}
|
||||
void Thread::exception(Cpu & cpu)
|
||||
{
|
||||
using Context = Genode::Cpu::Context;
|
||||
using Stval = Genode::Cpu::Stval;
|
||||
|
||||
if (regs->is_irq()) {
|
||||
/* there are only cpu-local timer interrupts right now */
|
||||
@ -33,20 +34,51 @@ void Thread::exception(Cpu & cpu)
|
||||
}
|
||||
|
||||
switch(regs->cpu_exception) {
|
||||
case Context::ECALL_FROM_USER:
|
||||
case Context::ECALL_FROM_SUPERVISOR:
|
||||
_call();
|
||||
break;
|
||||
case Context::ECALL_FROM_USER:
|
||||
_call();
|
||||
regs->ip += 4; /* set to next instruction */
|
||||
break;
|
||||
case Context::INSTRUCTION_PAGE_FAULT:
|
||||
|
||||
/*
|
||||
* Quirk for MIG-V:
|
||||
*
|
||||
* On MIG-V 'stval' does not report the correct address for instructions
|
||||
* that cross a page boundary.
|
||||
*
|
||||
* Spec 1.10: "For instruction-fetch access faults and page faults on RISC-V
|
||||
* systems with variable-length instructions, stval will point to the
|
||||
* portion of the instruction that caused the fault while sepc will point to
|
||||
* the beginning of the instruction."
|
||||
*
|
||||
* On MIG-V stval always points to the beginning of the instruction.
|
||||
*
|
||||
* Save the last instruction-fetch fault in 'last_fetch_fault', in case the
|
||||
* next fetch fault occurs at the same IP and is at a page border, set
|
||||
* page-fault address ('stval') to next page.
|
||||
*/
|
||||
if (regs->last_fetch_fault == regs->ip && (regs->ip & 0xfff) == 0xffe)
|
||||
Stval::write(Stval::read() + 4);
|
||||
|
||||
_mmu_exception();
|
||||
regs->last_fetch_fault = regs->ip;
|
||||
|
||||
break;
|
||||
|
||||
case Context::STORE_PAGE_FAULT:
|
||||
case Context::LOAD_PAGE_FAULT:
|
||||
case Context::INSTRUCTION_ACCESS_FAULT:
|
||||
case Context::LOAD_ACCESS_FAULT:
|
||||
case Context::STORE_ACCESS_FAULT:
|
||||
_mmu_exception();
|
||||
break;
|
||||
default:
|
||||
Genode::raw(*this, ": unhandled exception ", regs->cpu_exception,
|
||||
" at ip=", (void*)regs->ip,
|
||||
" addr=", Genode::Hex(Genode::Cpu::Sbadaddr::read()));
|
||||
" addr=", Genode::Hex(Genode::Cpu::Stval::read()));
|
||||
_die();
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \brief SBI-timer driver for RISC-V core
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2015-08-22
|
||||
* \date 2021-01-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
* Copyright (C) 2021 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
@ -13,7 +13,8 @@
|
||||
|
||||
/* Core includes */
|
||||
#include <kernel/timer.h>
|
||||
#include <hw/spec/riscv/machine_call.h>
|
||||
#include <platform.h>
|
||||
#include <hw/spec/riscv/sbi.h>
|
||||
|
||||
using namespace Genode;
|
||||
using namespace Kernel;
|
||||
@ -27,25 +28,32 @@ Board::Timer::Timer(unsigned)
|
||||
}
|
||||
|
||||
|
||||
time_t Board::Timer::stime() const { return Hw::get_sys_timer(); }
|
||||
time_t Board::Timer::stime() const
|
||||
{
|
||||
register time_t time asm("a0");
|
||||
asm volatile ("rdtime %0" : "=r"(time));
|
||||
|
||||
return time;
|
||||
}
|
||||
|
||||
|
||||
void Timer::_start_one_shot(time_t const ticks)
|
||||
{
|
||||
_device.timeout = _device.stime() + ticks;
|
||||
Hw::set_sys_timer(_device.timeout);
|
||||
Sbi::set_timer(_device.timeout);
|
||||
}
|
||||
|
||||
|
||||
time_t Timer::ticks_to_us(time_t const ticks) const {
|
||||
return ticks / Board::Timer::TICS_PER_US; }
|
||||
return (ticks / Board::Timer::TICKS_PER_US); }
|
||||
|
||||
|
||||
time_t Timer::us_to_ticks(time_t const us) const {
|
||||
return us * Board::Timer::TICS_PER_MS; }
|
||||
return us * Board::Timer::TICKS_PER_US; }
|
||||
|
||||
|
||||
time_t Timer::_max_value() const { return 0xffffffff; }
|
||||
time_t Timer::_max_value() const {
|
||||
return 0xffffffff; }
|
||||
|
||||
|
||||
time_t Timer::_duration() const
|
||||
|
||||
@ -27,9 +27,8 @@ namespace Board { class Timer; }
|
||||
struct Board::Timer
|
||||
{
|
||||
enum {
|
||||
SPIKE_TIMER_HZ = 1000000,
|
||||
TICS_PER_MS = SPIKE_TIMER_HZ / 1000,
|
||||
TICS_PER_US = TICS_PER_MS / 1000,
|
||||
TICKS_PER_MS = TIMER_HZ / 1000,
|
||||
TICKS_PER_US = TICKS_PER_MS / 1000,
|
||||
};
|
||||
|
||||
Kernel::time_t timeout = 0;
|
||||
|
||||
@ -27,19 +27,21 @@ struct Hw::Riscv_cpu
|
||||
|
||||
/* Supervisor-mode status Register */
|
||||
RISCV_SUPERVISOR_REGISTER(Sstatus, sstatus,
|
||||
struct Sie : Bitfield<1,1> { }; /* supervisor interrupt enable */
|
||||
struct Spp : Bitfield<8,1> { }; /* prior privilege level */
|
||||
);
|
||||
|
||||
/* Supervisor Trap Vector Base Address Register */
|
||||
RISCV_SUPERVISOR_REGISTER(Stvec, stvec);
|
||||
|
||||
/* Supervisor Bad Address Register */
|
||||
RISCV_SUPERVISOR_REGISTER(Sbadaddr, sbadaddr);
|
||||
/* Supervisor Trap Value (replaces Sbadaddr in ISA 1.10) */
|
||||
RISCV_SUPERVISOR_REGISTER(Stval, stval);
|
||||
|
||||
/* Supervisor Page-Table Base Register */
|
||||
RISCV_SUPERVISOR_REGISTER(Sptbr, sptbr,
|
||||
struct Ppn : Bitfield<0, 38> { };
|
||||
struct Asid : Bitfield<38, 26> { };
|
||||
/* Supervisor address translation an protection (replaces sptbr in ISA 1.10) */
|
||||
RISCV_SUPERVISOR_REGISTER(Satp, satp,
|
||||
struct Ppn : Bitfield<0, 44> { };
|
||||
struct Asid : Bitfield<44,16> { };
|
||||
struct Mode : Bitfield<60, 4> { };
|
||||
);
|
||||
};
|
||||
|
||||
|
||||
@ -1,47 +0,0 @@
|
||||
/**
|
||||
* \brief Calls supported by machine mode (or SBI interface in RISC-V)
|
||||
* \author Sebastian Sumpf
|
||||
* \author Martin Stein
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2015-06-14
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__LIB__HW__SPEC__RISCV__MACHINE_CALL_H_
|
||||
#define _SRC__LIB__HW__SPEC__RISCV__MACHINE_CALL_H_
|
||||
|
||||
using uintptr_t = unsigned long;
|
||||
#include <bbl/mcall.h>
|
||||
|
||||
namespace Hw {
|
||||
|
||||
inline unsigned long ecall(unsigned long id, unsigned long a0,
|
||||
unsigned long a1)
|
||||
{
|
||||
asm volatile ("mv a0, %0\n"
|
||||
"mv a1, %1\n"
|
||||
"mv a2, %2\n"
|
||||
"ecall \n"
|
||||
"mv %0, a0\n"
|
||||
: "+r"(id) : "r"(a0), "r"(a1)
|
||||
: "a0", "a1", "a2");
|
||||
return id;
|
||||
}
|
||||
|
||||
inline void put_char(unsigned long c) {
|
||||
ecall(MCALL_CONSOLE_PUTCHAR, c, /* unused arg */ 0); }
|
||||
|
||||
inline void set_sys_timer(unsigned long t) {
|
||||
ecall(MCALL_SET_TIMER, t, /* unused arg */ 0); }
|
||||
|
||||
inline unsigned long get_sys_timer() {
|
||||
return ecall(MCALL_GET_TIMER, /* unused args */ 0, 0); }
|
||||
}
|
||||
|
||||
#endif /* _SRC__LIB__HW__SPEC__RISCV__MACHINE_CALL_H_ */
|
||||
@ -60,6 +60,8 @@ struct Sv39::Descriptor : Register<64>
|
||||
struct X : Bitfield<3, 1> { }; /* executable */
|
||||
struct U : Bitfield<4, 1> { }; /* user */
|
||||
struct G : Bitfield<5, 1> { }; /* global */
|
||||
struct A : Bitfield<6, 1> { }; /* access bit */
|
||||
struct D : Bitfield<7, 1> { }; /* dirty bit */
|
||||
|
||||
struct Perm : Bitfield<0, 5> { };
|
||||
struct Type : Bitfield<1, 3>
|
||||
@ -130,6 +132,15 @@ struct Sv39::Block_descriptor : Descriptor
|
||||
|
||||
Ppn::set(desc, base);
|
||||
Perm::set(desc, permission_bits(f));
|
||||
|
||||
/*
|
||||
* Always set access and dirty bits because RISC-V may raise a page fault
|
||||
* (implementation dependend) in case it observes this bits being cleared.
|
||||
*/
|
||||
A::set(desc, 1);
|
||||
if (f.writeable)
|
||||
D::set(desc, 1);
|
||||
|
||||
V::set(desc, 1);
|
||||
|
||||
return desc;
|
||||
|
||||
@ -1,27 +1,31 @@
|
||||
/*
|
||||
* \brief Riscv spike specific board definitions
|
||||
* \brief RISC-V Qemu specific board definitions
|
||||
* \author Sebastian Sumpf
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-16
|
||||
* \date 2021-02-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
* Copyright (C) 2021 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
|
||||
|
||||
#include <hw/spec/riscv/boot_info.h>
|
||||
#include <hw/spec/riscv/page_table.h>
|
||||
#include <hw/spec/riscv/uart.h>
|
||||
#include <drivers/defs/riscv.h>
|
||||
#include <hw/spec/riscv/sbi.h>
|
||||
|
||||
namespace Hw::Riscv_board {
|
||||
|
||||
using namespace Riscv;
|
||||
enum {
|
||||
RAM_BASE = 0x80020000,
|
||||
RAM_SIZE = 0x7fe0000,
|
||||
TIMER_HZ = 10000000,
|
||||
};
|
||||
|
||||
enum { UART_BASE, UART_CLOCK };
|
||||
|
||||
@ -31,4 +35,4 @@ namespace Hw::Riscv_board {
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_ */
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_ */
|
||||
52
repos/base-hw/src/include/hw/spec/riscv/sbi.h
Normal file
52
repos/base-hw/src/include/hw/spec/riscv/sbi.h
Normal file
@ -0,0 +1,52 @@
|
||||
/**
|
||||
* \brief OpenSBI interface
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2021-01-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__LIB__HW__SPEC__RISCV__SBI_H_
|
||||
#define _SRC__LIB__HW__SPEC__RISCV__SBI_H_
|
||||
|
||||
namespace Sbi {
|
||||
|
||||
enum Eid {
|
||||
SET_TIMER = 0,
|
||||
PUT_CHAR = 1,
|
||||
};
|
||||
|
||||
inline unsigned long ecall(Eid eid, unsigned long arg0)
|
||||
{
|
||||
asm volatile ("mv a0, %0\n"
|
||||
"mv a7, %1\n"
|
||||
"ecall \n"
|
||||
"mv %0, a0\n"
|
||||
: "+r"(arg0) : "r"(eid)
|
||||
: "a0", "a7");
|
||||
return eid;
|
||||
}
|
||||
|
||||
inline void set_timer(unsigned long value) { ecall(SET_TIMER, value); }
|
||||
inline void console_put_char(unsigned long c) { ecall(PUT_CHAR, c); }
|
||||
}
|
||||
|
||||
namespace Hw { struct Riscv_uart; }
|
||||
|
||||
/**
|
||||
* SBI Uart
|
||||
*/
|
||||
struct Hw::Riscv_uart
|
||||
{
|
||||
void put_char(char const c)
|
||||
{
|
||||
Sbi::console_put_char(c);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__LIB__HW__SPEC__RISCV__SBI_H_ */
|
||||
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* \brief UART output driver for RISCV
|
||||
* \author Sebastian Sumpf
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2015-06-02
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__LIB__HW__SPEC__RISCV__UART_H_
|
||||
#define _SRC__LIB__HW__SPEC__RISCV__UART_H_
|
||||
|
||||
#include <hw/spec/riscv/machine_call.h>
|
||||
#include <util/register.h>
|
||||
|
||||
namespace Hw { struct Riscv_uart; }
|
||||
|
||||
|
||||
struct Hw::Riscv_uart
|
||||
{
|
||||
void put_char(char const c)
|
||||
{
|
||||
Hw::put_char(c);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__LIB__HW__SPEC__RISCV__UART_H_ */
|
||||
@ -1,25 +0,0 @@
|
||||
/*
|
||||
* \brief MMIO and IRQ definitions for RISC-V (1.9.1)
|
||||
* \author Sebastian Sumpf
|
||||
* \date 2017-05-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__DEFS__RISCV_H_
|
||||
#define _INCLUDE__DRIVERS__DEFS__RISCV_H_
|
||||
|
||||
namespace Riscv {
|
||||
enum {
|
||||
RAM_0_BASE = 0x81000000,
|
||||
RAM_0_SIZE = 0x6e00000,
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__DEFS__RISCV_H_ */
|
||||
|
||||
@ -1,9 +1,11 @@
|
||||
# local variable for run-tool arguments used for running scenarios in Qemu
|
||||
QEMU_RUN_OPT := --include power_on/qemu --include log/qemu
|
||||
|
||||
# kernel to use
|
||||
KERNEL ?= hw
|
||||
|
||||
# board to use
|
||||
BOARD ?= spike
|
||||
# board to use (riscv_qemu)
|
||||
BOARD ?= riscv_qemu
|
||||
|
||||
# local variable for run-tool arguments that depend on the used board
|
||||
BOARD_RUN_OPT(spike) = --include image/bbl --include power_on/spike --include log/spike
|
||||
|
||||
BOARD_RUN_OPT(riscv_qemu) = $(QEMU_RUN_OPT)
|
||||
|
||||
@ -1,6 +0,0 @@
|
||||
proc run_image {elf_img} {
|
||||
puts "using '$elf_img' as bbl image"
|
||||
|
||||
exec rm -f bbl/image.o
|
||||
exec -ignorestderr make IMAGE_ELF=[pwd]/$elf_img bbl
|
||||
}
|
||||
@ -1,34 +0,0 @@
|
||||
|
||||
source [genode_dir]/tool/run/log.inc
|
||||
source [genode_dir]/tool/run/spike.inc
|
||||
|
||||
|
||||
proc run_log { wait_for_re timeout_value } {
|
||||
global spike_spawn_id
|
||||
global output_spawn_id
|
||||
|
||||
set kernel_msg [run_boot_string]
|
||||
set output_spawn_id $spike_spawn_id
|
||||
|
||||
if {$wait_for_re == "forever"} {
|
||||
set timeout -1
|
||||
} else {
|
||||
set timeout $timeout_value
|
||||
}
|
||||
|
||||
expect {
|
||||
-i $output_spawn_id $kernel_msg { }
|
||||
eof {
|
||||
puts stderr "Aborting, received EOF"
|
||||
return false
|
||||
}
|
||||
timeout {
|
||||
puts stderr "Boot process timed out"
|
||||
close
|
||||
return false
|
||||
}
|
||||
}
|
||||
|
||||
wait_for_output $wait_for_re $timeout_value $spike_spawn_id
|
||||
return true
|
||||
}
|
||||
@ -52,6 +52,7 @@ proc run_power_on { } {
|
||||
if {[have_spec x86_64]} { set qemu "qemu-system-x86_64" }
|
||||
if {[have_spec arm]} { set qemu "qemu-system-arm" }
|
||||
if {[have_spec arm_64]} { set qemu "qemu-system-aarch64" }
|
||||
if {[have_spec riscv]} { set qemu "qemu-system-riscv64" }
|
||||
|
||||
#
|
||||
# Only the x86_64 variant of Qemu provides the emulation of hardware
|
||||
@ -155,8 +156,14 @@ proc run_power_on { } {
|
||||
append qemu_args " -machine q35 "
|
||||
}
|
||||
|
||||
# on ARM, we supply the boot image as kernel
|
||||
if {[have_spec arm] || [have_spec arm_v8]} { append qemu_args " -kernel [run_dir]/boot/image.elf " }
|
||||
if {[have_board riscv_qemu]} {
|
||||
append qemu_args " -m 128 -machine virt -cpu rv64,priv_spec=v1.10.0 "
|
||||
append qemu_args " -bios default "
|
||||
}
|
||||
|
||||
# on ARM/RISC-V, we supply the boot image as kernel
|
||||
if {[have_spec arm] || [have_spec arm_v8] || [have_spec riscv]} {
|
||||
append qemu_args " -kernel [run_dir]/boot/image.elf " }
|
||||
|
||||
eval spawn $qemu $qemu_args
|
||||
set qemu_spawn_id $spawn_id
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
##
|
||||
# Execute scenario using spike
|
||||
#
|
||||
source [genode_dir]/tool/run/spike.inc
|
||||
|
||||
proc is_spike_available { } {
|
||||
|
||||
if {[have_spec riscv]} { return true }
|
||||
|
||||
puts stderr "skipping execution because platform is not supported by spike"
|
||||
return false
|
||||
}
|
||||
|
||||
proc run_power_on { } {
|
||||
global spike_args
|
||||
global spike
|
||||
global spike_spawn_id
|
||||
|
||||
if {![is_spike_available]} { return 0 }
|
||||
|
||||
append spike_args "-m128 [pwd]/debug/bbl "
|
||||
|
||||
set spike "spike"
|
||||
eval spawn $spike $spike_args
|
||||
set spike_spawn_id $spawn_id
|
||||
|
||||
return true
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
set spike_spawn_id ""
|
||||
Loading…
x
Reference in New Issue
Block a user