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hw: [[fallthrough]] annotations for ARM/RISC-V
* double checked issue #3377
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@ -210,7 +210,7 @@ class Hw::Long_translation_table
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switch (f.cacheable) {
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case Genode::CACHED: return Attribute_index::bits(CACHED);
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case Genode::WRITE_COMBINED:
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case Genode::WRITE_COMBINED: [[fallthrough]];
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case Genode::UNCACHED: return Attribute_index::bits(UNCACHED);
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}
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return 0;
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@ -434,7 +434,7 @@ class Hw::Level_x_translation_table :
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E & table = alloc.construct<E>();
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desc = Table_descriptor::create((void*)alloc.phys_addr(table));
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}
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[[fallthrough]];
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case Descriptor::TABLE: /* table already available */
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{
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/* use allocator to retrieve virt address of table */
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@ -476,8 +476,8 @@ class Hw::Level_x_translation_table :
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size, alloc);
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if (!table.empty()) break;
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alloc.destruct<E>(table);
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}
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case Descriptor::BLOCK:
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} [[fallthrough]];
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case Descriptor::BLOCK: [[fallthrough]];
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case Descriptor::INVALID:
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desc = 0;
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}
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@ -64,7 +64,7 @@ class Hw::Page_table
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T::Tex::set(v, _device_tex());
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} else {
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switch (f.cacheable) {
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case CACHED: T::Tex::set(v, 5);
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case CACHED: T::Tex::set(v, 5); [[fallthrough]];
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case WRITE_COMBINED: T::B::set(v, 1); break;
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case UNCACHED: T::Tex::set(v, 1); break;
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}
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@ -434,6 +434,7 @@ class Hw::Page_table
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_entries[i] = Ptd::create(alloc.phys_addr(pt));
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_translation_added((addr_t)&_entries[i], sizeof(Ptd));
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}
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[[fallthrough]];
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case Descriptor::PAGE_TABLE:
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{
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@ -238,6 +238,7 @@ class Sv39::Level_x_translation_table
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E & table = alloc.construct<E>();
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desc = Td::create((void*)alloc.phys_addr(table));
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}
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[[fallthrough]];
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case Descriptor::TABLE: /* table already available */
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{
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@ -277,7 +278,8 @@ class Sv39::Level_x_translation_table
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if (!table.empty()) break;
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alloc.destruct<E>(table);
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}
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case Descriptor::BLOCK:
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[[fallthrough]];
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case Descriptor::BLOCK: [[fallthrough]];
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case Descriptor::INVALID:
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desc = 0;
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}
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