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https://github.com/genodelabs/genode.git
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hw: remove SMP variable from board.h
Whether an SoC has the multiprocessing extensions can be read out from the identification registers, and does not need to be specified in each board header. Ref #3445
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0b77e8ea62
commit
5c7436bf10
repos/base-hw/src
@ -26,13 +26,7 @@ void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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Ttbcr::write(1);
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Ttbr::access_t ttbr = Ttbr::Ba::masked(table);
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Ttbr::Rgn::set(ttbr, Ttbr::CACHEABLE);
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if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
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Ttbr::Irgn::set(ttbr, Ttbr::CACHEABLE);
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Ttbr::S::set(ttbr, 1);
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} else
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Ttbr::C::set(ttbr, 1);
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Ttbr::access_t ttbr = Ttbr::init(table);
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Ttbr0::write(ttbr);
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Ttbr1::write(ttbr);
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@ -78,9 +78,7 @@ unsigned Bootstrap::Platform::enable_mmu()
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Cpu::Ttbcr::write(1);
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Genode::addr_t table = (Genode::addr_t)core_pd->table_base;
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Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::Ba::masked(table);
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Cpu::Ttbr::Rgn::set(ttbr, Cpu::Ttbr::CACHEABLE);
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Cpu::Ttbr::C::set(ttbr, 1);
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Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::init(table);
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Cpu::Ttbr0::write(ttbr);
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Cpu::Ttbr1::write(ttbr);
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@ -41,7 +41,7 @@ static Asid_allocator &alloc() {
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Arm_cpu::Mmu_context::Mmu_context(addr_t table)
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: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr0::init(table)) { }
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: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr::init(table)) { }
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Genode::Arm_cpu::Mmu_context::~Mmu_context()
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@ -37,27 +37,6 @@ namespace Genode {
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struct Genode::Arm_cpu : public Hw::Arm_cpu
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{
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/**
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* Translation table base register 0
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*/
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struct Ttbr0 : Hw::Arm_cpu::Ttbr0
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{
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table)
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{
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access_t v = Ttbr::Ba::masked((addr_t)table);
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Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
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Ttbr::S::set(v, Board::SMP ? 1 : 0);
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if (Board::SMP) Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
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else Ttbr::C::set(v, 1);
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return v;
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}
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};
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struct Fpu_context
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{
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uint32_t fpscr { 1UL << 24 }; /* VFP/SIMD - status/control register */
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@ -21,8 +21,6 @@ namespace Board {
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using namespace Hw::Arndale_board;
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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}
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#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */
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@ -21,7 +21,6 @@
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namespace Board {
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using namespace Hw::Imx53_qsb_board;
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using Hw::Pic;
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static constexpr bool SMP = false;
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}
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#endif /* _CORE__SPEC__IMX53_QSB__BOARD_H_ */
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@ -24,8 +24,6 @@ namespace Board {
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using Pic = Hw::Gicv2;
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using L2_cache = Hw::Pl310;
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static constexpr bool SMP = true;
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L2_cache & l2_cache();
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}
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@ -21,8 +21,6 @@ namespace Board {
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using namespace Hw::Imx7d_sabre_board;
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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}
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#endif /* _CORE__SPEC__IMX7_SABRELITE__BOARD_H_ */
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@ -23,8 +23,6 @@ namespace Board {
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using Pic = Hw::Gicv2;
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using L2_cache = Hw::Pl310;
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static constexpr bool SMP = true;
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L2_cache & l2_cache();
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}
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@ -21,8 +21,6 @@ namespace Board {
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using namespace Hw::Odroid_xu_board;
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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}
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#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */
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@ -23,8 +23,6 @@ namespace Board {
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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class L2_cache : public Hw::Pl310
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{
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private:
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@ -22,8 +22,6 @@ namespace Board {
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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L2_cache & l2_cache();
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}
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@ -20,8 +20,6 @@
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namespace Board {
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using namespace Hw::Rpi_board;
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static constexpr bool SMP = false;
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};
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#endif /* _CORE__SPEC__RPI__BOARD_H_ */
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@ -19,8 +19,6 @@
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namespace Board {
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using namespace Hw::Rpi3_board;
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static constexpr bool SMP = true;
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};
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#endif /* _CORE__SPEC__RPI3__BOARD_H_ */
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@ -20,10 +20,7 @@
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namespace Board {
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using namespace Hw::Usb_armory_board;
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using Hw::Pic;
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static constexpr bool SMP = false;
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}
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#endif /* _CORE__SPEC__USB_ARMORY__BOARD_H_ */
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@ -24,8 +24,6 @@ namespace Board {
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using L2_cache = Hw::Pl310;
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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L2_cache & l2_cache();
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}
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@ -24,8 +24,6 @@ namespace Board {
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using Pic = Hw::Gicv2;
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static constexpr bool SMP = true;
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L2_cache & l2_cache();
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}
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@ -107,6 +107,18 @@ struct Hw::Arm_cpu
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struct Irgn_1 : Bitfield<0,1> { };
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struct Irgn_0 : Bitfield<6,1> { };
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struct Irgn : Genode::Bitset_2<Irgn_0, Irgn_1> { }; /* inner cache mode */
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static access_t init(Genode::addr_t table)
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{
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access_t v = Ttbr::Ba::masked(table);
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Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
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if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
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Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
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Ttbr::S::set(v, 1);
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} else
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Ttbr::C::set(v, 1);
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return v;
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};
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};
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struct Ttbr_64bit : Genode::Register<64>
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