hw: remove SMP variable from board.h

Whether an SoC has the multiprocessing extensions can be read out
from the identification registers, and does not need to be specified
in each board header.

Ref 
This commit is contained in:
Stefan Kalkowski 2019-07-10 15:36:41 +02:00 committed by Christian Helmuth
parent 0b77e8ea62
commit 5c7436bf10
18 changed files with 15 additions and 58 deletions
repos/base-hw/src
bootstrap/spec
core/spec
arm
arndale
imx53_qsb
imx6q_sabrelite
imx7d_sabre
nit6_solox
odroid_xu
panda
pbxa9
rpi
rpi3
usb_armory
wand_quad
zynq_qemu
include/hw/spec/arm

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@ -26,13 +26,7 @@ void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
Ttbcr::write(1);
Ttbr::access_t ttbr = Ttbr::Ba::masked(table);
Ttbr::Rgn::set(ttbr, Ttbr::CACHEABLE);
if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
Ttbr::Irgn::set(ttbr, Ttbr::CACHEABLE);
Ttbr::S::set(ttbr, 1);
} else
Ttbr::C::set(ttbr, 1);
Ttbr::access_t ttbr = Ttbr::init(table);
Ttbr0::write(ttbr);
Ttbr1::write(ttbr);

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@ -78,9 +78,7 @@ unsigned Bootstrap::Platform::enable_mmu()
Cpu::Ttbcr::write(1);
Genode::addr_t table = (Genode::addr_t)core_pd->table_base;
Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::Ba::masked(table);
Cpu::Ttbr::Rgn::set(ttbr, Cpu::Ttbr::CACHEABLE);
Cpu::Ttbr::C::set(ttbr, 1);
Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::init(table);
Cpu::Ttbr0::write(ttbr);
Cpu::Ttbr1::write(ttbr);

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@ -41,7 +41,7 @@ static Asid_allocator &alloc() {
Arm_cpu::Mmu_context::Mmu_context(addr_t table)
: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr0::init(table)) { }
: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr::init(table)) { }
Genode::Arm_cpu::Mmu_context::~Mmu_context()

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@ -37,27 +37,6 @@ namespace Genode {
struct Genode::Arm_cpu : public Hw::Arm_cpu
{
/**
* Translation table base register 0
*/
struct Ttbr0 : Hw::Arm_cpu::Ttbr0
{
/**
* Return initialized value
*
* \param table base of targeted translation table
*/
static access_t init(addr_t const table)
{
access_t v = Ttbr::Ba::masked((addr_t)table);
Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
Ttbr::S::set(v, Board::SMP ? 1 : 0);
if (Board::SMP) Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
else Ttbr::C::set(v, 1);
return v;
}
};
struct Fpu_context
{
uint32_t fpscr { 1UL << 24 }; /* VFP/SIMD - status/control register */

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@ -21,8 +21,6 @@ namespace Board {
using namespace Hw::Arndale_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */

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@ -21,7 +21,6 @@
namespace Board {
using namespace Hw::Imx53_qsb_board;
using Hw::Pic;
static constexpr bool SMP = false;
}
#endif /* _CORE__SPEC__IMX53_QSB__BOARD_H_ */

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@ -24,8 +24,6 @@ namespace Board {
using Pic = Hw::Gicv2;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}

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@ -21,8 +21,6 @@ namespace Board {
using namespace Hw::Imx7d_sabre_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__IMX7_SABRELITE__BOARD_H_ */

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@ -23,8 +23,6 @@ namespace Board {
using Pic = Hw::Gicv2;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}

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@ -21,8 +21,6 @@ namespace Board {
using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */

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@ -23,8 +23,6 @@ namespace Board {
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
class L2_cache : public Hw::Pl310
{
private:

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@ -22,8 +22,6 @@ namespace Board {
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}

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@ -20,8 +20,6 @@
namespace Board {
using namespace Hw::Rpi_board;
static constexpr bool SMP = false;
};
#endif /* _CORE__SPEC__RPI__BOARD_H_ */

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@ -19,8 +19,6 @@
namespace Board {
using namespace Hw::Rpi3_board;
static constexpr bool SMP = true;
};
#endif /* _CORE__SPEC__RPI3__BOARD_H_ */

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@ -20,10 +20,7 @@
namespace Board {
using namespace Hw::Usb_armory_board;
using Hw::Pic;
static constexpr bool SMP = false;
}
#endif /* _CORE__SPEC__USB_ARMORY__BOARD_H_ */

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@ -24,8 +24,6 @@ namespace Board {
using L2_cache = Hw::Pl310;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}

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@ -24,8 +24,6 @@ namespace Board {
using Pic = Hw::Gicv2;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}

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@ -107,6 +107,18 @@ struct Hw::Arm_cpu
struct Irgn_1 : Bitfield<0,1> { };
struct Irgn_0 : Bitfield<6,1> { };
struct Irgn : Genode::Bitset_2<Irgn_0, Irgn_1> { }; /* inner cache mode */
static access_t init(Genode::addr_t table)
{
access_t v = Ttbr::Ba::masked(table);
Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
Ttbr::S::set(v, 1);
} else
Ttbr::C::set(v, 1);
return v;
};
};
struct Ttbr_64bit : Genode::Register<64>