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hw: consistently move cpu into board namespace

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Ref #3445
This commit is contained in:
Stefan Kalkowski 2019-07-10 15:00:33 +02:00 committed by Christian Helmuth
parent 875858b2cc
commit 0b77e8ea62
25 changed files with 46 additions and 45 deletions
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2
repos/base-hw/lib/mk/spec/x86_64/bootstrap-hw-muen.mk
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@ -1,3 +1,5 @@
REQUIRES = muen
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
SRC_CC += bootstrap/spec/x86_64/platform_muen.cc

1
repos/base-hw/src/bootstrap/platform.h
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@ -123,7 +123,6 @@ class Bootstrap::Platform
};
Board board { };
Bootstrap::Cpu cpu { };
Ram_allocator ram_alloc { };
Memory_region const bootstrap_region;
Genode::Constructible<Pd> core_pd { };

4
repos/base-hw/src/bootstrap/spec/arm/arm_v6_cpu.cc
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@ -15,9 +15,9 @@
#include <spec/arm/cpu.h>
void Bootstrap::Cpu::invalidate_data_cache() {
void Board::Cpu::invalidate_data_cache() {
asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : ); }
void Bootstrap::Cpu::clean_invalidate_data_cache() {
void Board::Cpu::clean_invalidate_data_cache() {
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }

4
repos/base-hw/src/bootstrap/spec/arm/arm_v7_cpu.cc
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@ -128,7 +128,7 @@
::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
void Bootstrap::Cpu::invalidate_data_cache()
void Board::Cpu::invalidate_data_cache()
{
/**
* Data Cache Invalidate by Set/Way for all Set/Way
@ -139,7 +139,7 @@ void Bootstrap::Cpu::invalidate_data_cache()
}
void Bootstrap::Cpu::clean_invalidate_data_cache()
void Board::Cpu::clean_invalidate_data_cache()
{
/**
* Data Cache Clean by Set/Way for all Set/Way

2
repos/base-hw/src/bootstrap/spec/arm/cortex_a15_cpu.cc
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@ -14,7 +14,7 @@
#include <spec/arm/cpu.h>
void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
{
/* invalidate TLB */
Tlbiall::write(0);

4
repos/base-hw/src/bootstrap/spec/arm/cortex_a8_mmu.cc
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@ -15,8 +15,8 @@
unsigned Bootstrap::Platform::enable_mmu()
{
Cpu::Sctlr::init();
Cpu::enable_mmu_and_caches((addr_t)core_pd->table_base);
::Board::Cpu::Sctlr::init();
::Board::Cpu::enable_mmu_and_caches((addr_t)core_pd->table_base);
return 0;
}

2
repos/base-hw/src/bootstrap/spec/arm/cortex_a9_actlr.h
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@ -18,7 +18,7 @@
namespace Bootstrap { struct Actlr; }
struct Bootstrap::Actlr : Bootstrap::Cpu::Actlr
struct Bootstrap::Actlr : Board::Cpu::Actlr
{
struct Fw : Bitfield<0, 1> { };
struct L2_prefetch_enable : Bitfield<1, 1> { };

2
repos/base-hw/src/bootstrap/spec/arm/cortex_a9_mmu.cc
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@ -103,7 +103,7 @@ struct Scu : Genode::Mmio
*/
unsigned Bootstrap::Platform::enable_mmu()
{
using namespace Bootstrap;
using namespace Board;
static volatile bool primary_cpu = true;
static Cpu_counter data_cache_invalidated;

2
repos/base-hw/src/bootstrap/spec/arm/cpu.cc
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@ -13,7 +13,7 @@
#include <spec/arm/cpu.h>
void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
{
/* invalidate TLB */
Tlbiall::write(0);

4
repos/base-hw/src/bootstrap/spec/arm/cpu.h
View File

@ -16,9 +16,9 @@
#include <hw/spec/arm/cpu.h>
namespace Bootstrap { struct Cpu; }
namespace Board { struct Cpu; }
struct Bootstrap::Cpu : Hw::Arm_cpu
struct Board::Cpu : Hw::Arm_cpu
{
struct Sctlr : Hw::Arm_cpu::Sctlr
{

4
repos/base-hw/src/bootstrap/spec/arm/imx6_platform.cc
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@ -36,11 +36,11 @@ Bootstrap::Platform::Board::Board()
}
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
bool Board::Cpu::errata(Board::Cpu::Errata err) {
return (err == ARM_764369) ? true : false; }
void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
void Board::Cpu::wake_up_all_cpus(void * const entry)
{
struct Src : Genode::Mmio
{

10
repos/base-hw/src/bootstrap/spec/arndale/platform.cc
View File

@ -152,6 +152,8 @@ static inline void switch_to_supervisor_mode()
unsigned Bootstrap::Platform::enable_mmu()
{
using namespace ::Board;
static volatile bool primary_cpu = true;
board.pic.init_cpu_local();
@ -162,21 +164,21 @@ unsigned Bootstrap::Platform::enable_mmu()
Cpu::Sctlr::init();
Cpu::Cpsr::init();
cpu.invalidate_data_cache();
Cpu::invalidate_data_cache();
/* primary cpu wakes up all others */
if (primary_cpu && NR_OF_CPUS > 1) {
primary_cpu = false;
cpu.wake_up_all_cpus(&_start_setup_stack);
Cpu::wake_up_all_cpus(&_start_setup_stack);
}
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
}
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
*(void * volatile *)Board::IRAM_BASE = ip;
asm volatile("dsb; sev;");

8
repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc
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@ -298,18 +298,18 @@ unsigned Bootstrap::Platform::enable_mmu()
/* primary cpu wakes up all others */
if (primary_cpu && NR_OF_CPUS > 1) {
cpu.invalidate_data_cache();
Cpu::invalidate_data_cache();
primary_cpu = false;
cpu.wake_up_all_cpus(&_start_setup_stack);
Cpu::wake_up_all_cpus(&_start_setup_stack);
}
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
}
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
struct Src : Genode::Mmio
{

4
repos/base-hw/src/bootstrap/spec/odroid_xu/platform.cc
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@ -28,7 +28,7 @@ unsigned Bootstrap::Platform::enable_mmu()
board.pic.init_cpu_local();
Cpu::Sctlr::init();
Cpu::Cpsr::init();
cpu.invalidate_data_cache();
cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
Cpu::invalidate_data_cache();
Cpu::enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
return 0;
}

6
repos/base-hw/src/bootstrap/spec/panda/platform.cc
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@ -25,10 +25,10 @@ Bootstrap::Platform::Board::Board()
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) { return false; }
bool Board::Cpu::errata(Board::Cpu::Errata) { return false; }
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
struct Wakeup_generator : Genode::Mmio
{
@ -39,7 +39,7 @@ void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
Wakeup_generator(void * const ip) : Mmio(CORTEX_A9_WUGEN_MMIO_BASE)
{
write<Aux_core_boot_1>((addr_t)ip);
write<Aux_core_boot_1>((Genode::addr_t)ip);
write<Aux_core_boot_0::Cpu1_status>(1);
}
};

4
repos/base-hw/src/bootstrap/spec/pbxa9/platform.cc
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@ -27,10 +27,10 @@ Bootstrap::Platform::Board::Board()
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) { return false; }
bool Board::Cpu::errata(Board::Cpu::Errata) { return false; }
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
void Board::Cpu::wake_up_all_cpus(void * const ip)
{
/**
* set the entrypoint for the other CPUs via the flags register

2
repos/base-hw/src/bootstrap/spec/riscv/board.h
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@ -21,8 +21,6 @@ namespace Board {
struct Pic {};
}
namespace Bootstrap { struct Cpu {}; }
template <typename E, unsigned B, unsigned S>
void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
{ }

2
repos/base-hw/src/bootstrap/spec/rpi/board.h
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@ -33,6 +33,6 @@ constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
void Hw::Page_table::_translation_added(unsigned long, unsigned long) {
Bootstrap::Cpu::clean_invalidate_data_cache(); }
Board::Cpu::clean_invalidate_data_cache(); }
#endif /* _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_ */

2
repos/base-hw/src/bootstrap/spec/rpi/platform.cc
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@ -37,6 +37,8 @@ Bootstrap::Platform::Board::Board()
unsigned Bootstrap::Platform::enable_mmu()
{
using ::Board::Cpu;
struct Sctlr : Cpu::Sctlr
{
struct W : Bitfield<3,1> { }; /* enable write buffer */

5
repos/base-hw/src/bootstrap/spec/rpi3/board.h
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@ -18,12 +18,9 @@
#include <hw/spec/arm_64/cpu.h>
#include <hw/spec/arm/lpae.h>
namespace Bootstrap {
using Cpu = Hw::Arm_64_cpu;
};
namespace Board {
using namespace Hw::Rpi3_board;
using Cpu = Hw::Arm_64_cpu;
struct Pic {};
};

2
repos/base-hw/src/bootstrap/spec/rpi3/platform.cc
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@ -13,7 +13,7 @@
#include <platform.h>
using Bootstrap::Cpu;
using Board::Cpu;
/**

5
repos/base-hw/src/bootstrap/spec/x86_64/board.h
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@ -19,12 +19,9 @@
#include <hw/spec/x86_64/cpu.h>
#include <hw/spec/x86_64/x86_64.h>
namespace Bootstrap {
using Cpu = Hw::X86_64_cpu;
}
namespace Board {
using namespace Hw::Pc_board;
using Cpu = Hw::X86_64_cpu;
struct Pic {};
}

2
repos/base-hw/src/bootstrap/spec/x86_64/platform.cc
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@ -277,6 +277,8 @@ static inline void ipi_to_all(Lapic &lapic, unsigned const boot_frame,
unsigned Bootstrap::Platform::enable_mmu()
{
using ::Board::Cpu;
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
addr_t const stack_base = reinterpret_cast<addr_t>(&__bootstrap_stack);

2
repos/base-hw/src/bootstrap/spec/x86_64/platform_muen.cc
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@ -46,6 +46,8 @@ Bootstrap::Platform::Board::Board()
unsigned Bootstrap::Platform::enable_mmu()
{
using ::Board::Cpu;
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
return 0;
}

6
repos/base-hw/src/bootstrap/spec/zynq/platform.cc
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@ -29,17 +29,17 @@ Bootstrap::Platform::Board::Board()
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) {
bool Cpu::errata(Board::Cpu::Errata) {
return false; }
void Bootstrap::Cpu::wake_up_all_cpus(void* ip) {
void Cpu::wake_up_all_cpus(void* ip) {
struct Wakeup_generator : Genode::Mmio
{
struct Core1_boot_addr : Register<0x0, 32> { };
Wakeup_generator(void * const ip) : Mmio(CORE1_ENTRY)
{
write<Core1_boot_addr>((addr_t)ip);
write<Core1_boot_addr>((Genode::addr_t)ip);
}
};