hw: correct the i.MX6 Sabrelite timer settings

Fix #3561
This commit is contained in:
Stefan Kalkowski 2019-11-25 14:46:29 +01:00 committed by Christian Helmuth
parent 4c74f4792c
commit 4800bcf5a0
4 changed files with 15 additions and 2 deletions

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@ -26,6 +26,11 @@ namespace Board {
using L2_cache = Hw::Pl310;
L2_cache & l2_cache();
enum {
CORTEX_A9_PRIVATE_TIMER_CLK = 396000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

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@ -25,6 +25,11 @@ namespace Board {
using L2_cache = Hw::Pl310;
L2_cache & l2_cache();
enum {
CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */

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@ -26,6 +26,11 @@ namespace Board {
using Pic = Hw::Gicv2;
L2_cache & l2_cache();
enum {
CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

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@ -44,8 +44,6 @@ namespace Imx6 {
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,