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parent
b76bd57ed1
commit
8cc48d5688
repos/base-hw
lib/mk/spec/arm
src
bootstrap/spec/arm
core/spec
include/hw/spec/arm
@ -17,7 +17,7 @@ SRC_CC += spec/arm/platform_support.cc
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# add assembly sources
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SRC_S += spec/arm/crt0.s
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SRC_S += spec/arm/exception_vector.s
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SRC_S += spec/arm/exception_vector.S
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vpath spec/32bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw
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@ -175,6 +175,7 @@ unsigned Bootstrap::Platform::enable_mmu()
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/* wait for other cores' coherency activation */
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smp_coherency_enabled.wait_for(NR_OF_CPUS);
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Cpu::synchronization_barrier();
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asm volatile("dsb sy\n"
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"isb sy\n" ::: "memory");
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return Cpu::Mpidr::Aff_0::get(Cpu::Mpidr::read());
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}
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@ -83,3 +83,24 @@ void Arm_cpu::mmu_fault_status(Fsr::access_t fsr, Thread_fault & fault)
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default: fault.type = Thread_fault::UNKNOWN;
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};
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}
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void Arm_cpu::switch_to(Arm_cpu::Context&, Arm_cpu::Mmu_context & o)
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{
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if (o.cidr == 0) return;
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Cidr::access_t cidr = Cidr::read();
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if (cidr != o.cidr) {
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/**
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* First switch to global mappings only to prevent
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* that wrong branch predicts result due to ASID
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* and Page-Table not being in sync (see ARM RM B 3.10.4)
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*/
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Cidr::write(0);
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Cpu::synchronization_barrier();
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Ttbr0::write(o.ttbr0);
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Cpu::synchronization_barrier();
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Cidr::write(o.cidr);
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Cpu::synchronization_barrier();
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}
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}
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@ -110,16 +110,7 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
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else Tlbiall::write(0);
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}
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void switch_to(Context&, Mmu_context & o)
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{
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if (o.cidr == 0) return;
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Cidr::access_t cidr = Cidr::read();
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if (cidr != o.cidr) {
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Cidr::write(o.cidr);
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Ttbr0::write(o.ttbr0);
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}
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}
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void switch_to(Context&, Mmu_context & o);
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static void mmu_fault(Context & c, Kernel::Thread_fault & fault);
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static void mmu_fault_status(Fsr::access_t fsr,
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@ -12,6 +12,7 @@
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <synchronize.s>
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/*********************
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** Constant values **
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@ -123,6 +124,8 @@
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ldr r1, [r1]
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blx r1
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SYSTEM_REGISTER_SYNC_BARRIER /* synchronize after the context switch */
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/*
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* Go to kernel entry code
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*/
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@ -164,4 +167,5 @@
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ldr r1, [sp, #16*4]
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msr spsr_cxsf, r1
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ldm sp, {r0-r14}^
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SYSTEM_REGISTER_SYNC_BARRIER /* synchronize after the context switch */
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subs pc, lr, #0
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@ -18,6 +18,11 @@
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/* core includes */
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#include <spec/arm/cpu_support.h>
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namespace Genode { using Cpu = Arm_cpu; }
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namespace Genode { struct Cpu; }
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struct Genode::Cpu : Arm_cpu
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{
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static inline void synchronization_barrier() {}
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};
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#endif /* _CORE__SPEC__ARM_V6__CPU_H_ */
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15
repos/base-hw/src/core/spec/arm_v6/synchronize.s
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15
repos/base-hw/src/core/spec/arm_v6/synchronize.s
Normal file
@ -0,0 +1,15 @@
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/*
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* \brief Assembler macros for ARMv6
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* \author Stefan Kalkowski
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* \date 2020-02-16
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*/
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/*
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* Copyright (C) 2020 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.macro SYSTEM_REGISTER_SYNC_BARRIER
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.endm
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@ -41,6 +41,12 @@ struct Genode::Arm_v7_cpu : Arm_cpu
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else Tlbiallis::write(0);
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} else Arm_cpu::invalidate_tlb(asid);
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}
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static inline void synchronization_barrier()
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{
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asm volatile("dsb sy\n"
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"isb sy\n" ::: "memory");
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}
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};
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#endif /* _CORE__SPEC__ARM_V7__CPU_SUPPORT_H_ */
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17
repos/base-hw/src/core/spec/arm_v7/synchronize.s
Normal file
17
repos/base-hw/src/core/spec/arm_v7/synchronize.s
Normal file
@ -0,0 +1,17 @@
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/*
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* \brief Assembler macros for ARMv7
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* \author Stefan Kalkowski
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* \date 2020-02-16
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*/
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/*
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* Copyright (C) 2020 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.macro SYSTEM_REGISTER_SYNC_BARRIER
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dsb sy
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isb sy
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.endm
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@ -286,12 +286,6 @@ struct Hw::Arm_cpu
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** Cache maintainance functions **
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**********************************/
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static inline void synchronization_barrier()
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{
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asm volatile("dsb\n"
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"isb\n");
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}
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static inline void wait_for_xchg(volatile void * addr,
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unsigned long new_value,
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unsigned long expected_value)
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