Commit Graph

116 Commits

Author SHA1 Message Date
Xianjun Jiao
f455472288 Feed data to ofdm decoder earlier in case a data is missed (arrive too early for ofdm decoder) 2023-01-09 14:50:22 +01:00
Xianjun Jiao
71c9b42d78 Reset internally equalizer after it is disabled to prepare for next round enable 2023-01-09 14:49:31 +01:00
Xianjun Jiao
8e59685c65 Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved) 2023-01-09 14:48:34 +01:00
Xianjun Jiao
e65ee43101 Make some basic block simpler and its delay more deterministic 2023-01-09 14:47:34 +01:00
Xianjun Jiao
a1e1e0090b Add threshold_scale and enable it by default:
sync short works at low SNR and the receiver sensitivity is better
2023-01-09 14:43:34 +01:00
Xianjun Jiao
6a8818fe5f extend the status_code to more formated style 2023-01-09 14:40:46 +01:00
Wei Liu
2747d431f9 fix viterbi decoder logging issue 2023-01-05 16:47:07 +01:00
Wei Liu
fe93170efc log all header bits, also when error occors 2023-01-05 16:45:43 +01:00
Wei Liu
c9f3d280a3 clean up log file, prolong simulation at the end by 300 sp 2023-01-05 16:38:51 +01:00
black_pigeon
f3bf82a05b add support for antsdr e200 2022-10-21 20:47:56 +02:00
Xianjun Jiao
3d0a40958c Add neptunesdr 2022-10-16 22:09:17 +02:00
HexSDR
76986e99d3 Update parse_board_name.tcl 2022-08-15 09:12:08 +02:00
HexSDR
8a74580ad1 Update create_vivado_proj.sh
add sdrpi
2022-08-15 09:12:08 +02:00
Xianjun Jiao
707cb99a90 Remove the huge logging thing in dot11_tb.v 2022-07-15 12:10:03 +02:00
Xianjun Jiao
064bbe4250 Auto stop the simulation at the end of iq sample file 2022-05-16 09:53:07 +02:00
Xianjun Jiao
f6fd0a2a85 Minor cleaning 2022-05-16 09:52:24 +02:00
Xianjun Jiao
7622d7aaa0 Disable signal watch dog for normal simulation in the tb 2022-05-16 09:51:30 +02:00
Xianjun Jiao
55f77bb16b Connect pkt_len from dot11 to signal watch dog in the tb 2022-05-16 09:51:01 +02:00
thavinga
cb6b566d5f Move all signal logging to dot11_tb.v 2022-05-16 09:33:19 +02:00
Xianjun Jiao
1659c01ac7 Add conditional compiling framework 2022-05-13 13:24:41 +02:00
Xianjun Jiao
a7b95b492c Workaround to supress the error message when the 1st time run simulation 2022-05-13 13:21:19 +02:00
Jiao Xianjun
ac1a75e55a
Change the device/board to 7020 for low-end device friendly (Avoid the license issue in the default case) 2022-05-11 10:30:18 +02:00
Jiao Xianjun
5d4e72f66e
Merge pull request #1 from open-sdr/pre-release
openwifi-1.3.0-wilsele
2022-04-01 11:07:17 +02:00
Xianjun Jiao
4168aa8c7a Add slv_reg1[4] for option of disabling all smoothing 2022-03-29 12:50:31 +02:00
Xianjun Jiao
39911461ef Fix the issue of adrv9364z7020: demod_is_ongoing always high. dot11 stuck at state 3
Seems new viter decoder IP core does not need this complicated CE signal vit_ce in ofdm_decoder.v
    Setting the vit-ce to always 1 fixed the issue
2022-03-23 14:26:41 +01:00
Xianjun Jiao
44c8846072 Add more test vectors into testing_inputs/simulated 2022-03-16 15:07:48 +01:00
Xianjun Jiao
f08c76ca3d Add signal_watchdog module to prevent fake demod in early phase:
1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset
2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
2022-03-15 16:03:40 +01:00
Xianjun Jiao
e77f1ba70b Add git rev tracking to reg 31 2022-03-15 15:57:57 +01:00
Xianjun Jiao
954bae4e77 Add a test vector fake-demod-0.txt that could cause fake demodulation 2022-03-15 15:53:36 +01:00
Xianjun Jiao
40b3e59958 remove unnecessary atan_lut files 2022-03-15 15:52:05 +01:00
Xianjun Jiao
566e82f43e Add more clock cases into dot11_tb.v 2022-01-28 12:17:16 +01:00
Xianjun Jiao
030cdb34ca Add force ht smoothing option:
> 1. Leave the module always enabled, so the slv_reg1 is free
> 2. Use the slv_reg1 to force ht smoothing
> 3. By default, the smoothing option of the receiver is still controlled by the received ht packet
2022-01-28 12:15:49 +01:00
mmehari
23e61e6a29 Avoid equalizer module processing HT_STF symbol 2022-01-04 22:45:47 +01:00
mmehari
0c75a8e8f2 bug fix: remaining packet length calculation 2022-01-04 22:44:31 +01:00
mmehari
8730912d6f feature update: sampling frequency offset (SFO) compensation 2022-01-04 22:26:57 +01:00
mmehari
b40c221e67 Advance phase correction value by guard interval size 2022-01-04 22:25:38 +01:00
mmehari
85b1adbec7 bug fix: increase phase calculation delay by 1 CLK 2022-01-04 22:22:00 +01:00
mmehari
e257d3373b storage update: A-MPDU decoding 2022-01-04 22:20:44 +01:00
mmehari
af855d8c10 Save channel gain information of HT-LTF 2022-01-04 22:19:40 +01:00
mmehari
48aade0190 provide demod_soft_bits and demod_soft_bits_pos signals out 2022-01-04 22:18:23 +01:00
mmehari
84039d7368 Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude 2022-01-04 22:17:12 +01:00
mmehari
d2d5494f57 LTF cross-correlation window update: 16->32 complex samples 2022-01-04 22:16:18 +01:00
mmehari
36c738fe98 phase estimation update: quadrant quantization from 256 slices -> 512 slices 2022-01-04 22:15:16 +01:00
mmehari
53679a107f integer division rounding fix during phase offset calculation 2022-01-04 22:12:45 +01:00
mmehari
82d2d456e5 keep significant bits while performing division during phase calculation 2022-01-04 22:11:50 +01:00
mmehari
d9649eb614 phase register size reduction: 32bit -> 16bit 2022-01-04 22:10:36 +01:00
mmehari
f3e95eaa92 long preamble detection method update: cross-correlation inter-peak gap distance -> 1st peak detection 2022-01-04 22:07:54 +01:00
mmehari
aaa8ef3ce5 HT/non_HT detection requires at most 9 clocks 2022-01-04 22:05:38 +01:00
mmehari
8bc2d7f0a4 channel smoothing update based on HT-SIG field 2022-01-04 22:03:03 +01:00
mmehari
171ef8b27a A-MPDU decoding support 2022-01-04 22:01:58 +01:00