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079744bec1
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fix dot11 port pinout
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2017-04-21 13:42:09 -04:00 |
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b7361b2feb
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fix port pinout
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2017-04-21 13:41:49 -04:00 |
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c0ad55abb6
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remve unused variable in descramble.v
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2017-04-21 13:41:28 -04:00 |
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556794ae2e
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add coregen files
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2017-04-14 16:29:33 -04:00 |
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e5d4dc7cfc
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enlarge num_sample
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2017-04-14 11:01:18 -04:00 |
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701cbb70c9
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variable name
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2017-04-14 11:00:46 -04:00 |
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0b0723899a
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rotate
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2017-04-14 11:00:33 -04:00 |
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47577f7099
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fix comment
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2017-04-14 11:00:12 -04:00 |
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191b197d5e
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fix polarity pattern
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2017-04-14 11:00:01 -04:00 |
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297162af13
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working
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2017-04-07 16:51:06 -04:00 |
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20279b42a4
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fix long preamble sample beginning index
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2017-04-07 16:49:41 -04:00 |
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779b3651a4
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remove unused verilog files
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2017-04-07 11:36:51 -04:00 |
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8375779a03
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refactor name
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2017-04-07 11:36:41 -04:00 |
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4dd053ebf8
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use delayT
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2017-04-07 11:36:21 -04:00 |
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cf42e1b7ae
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working
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2017-04-03 15:48:25 -04:00 |
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506472dec3
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add sim_out dir
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2017-04-03 15:25:48 -04:00 |
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1ad9302fc3
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readme
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2017-04-03 14:31:25 -04:00 |
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d3ff9e7ce8
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makefile
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2017-04-03 14:05:07 -04:00 |
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bf4701fb39
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makefile
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2017-04-03 12:59:32 -04:00 |
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9edf1899bd
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verilog init
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2017-04-03 12:52:03 -04:00 |
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