Xianjun Jiao
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539133f453
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make the code more testbench friendly
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2020-09-02 21:59:37 +02:00 |
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Xianjun Jiao
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2b3a043e8c
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turn on soft_decoding in dot11_tb.v
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2020-09-02 17:15:11 +02:00 |
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Xianjun Jiao
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6d60fceed2
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fix the project_name and script_file in openofdm_rx_ultra_scale.tcl
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2020-09-02 17:05:18 +02:00 |
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Xianjun Jiao
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bf043af712
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change the latency of divider from automatic 60 clocks to the original 36 clock
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2020-09-02 16:49:59 +02:00 |
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mmehari
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b86951097c
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802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz)
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2020-08-30 15:23:07 +02:00 |
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Xianjun Jiao
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d7f5806790
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fix the atan_addr overflow issue (phase.v)
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2020-08-29 14:48:38 +02:00 |
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mmehari
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8c59d3a8dd
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channel estimation update: frequency domain averaging
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2020-08-29 11:41:32 +02:00 |
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mmehari
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77e201cfa8
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course CFO bug fix
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2020-08-29 11:38:06 +02:00 |
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Xianjun Jiao
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702b0c084f
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fix the simulation input file format of dot11_tb.v
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2020-06-17 16:06:49 +02:00 |
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Xianjun Jiao
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6a0073ee58
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remove debug
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2020-06-12 10:24:59 +02:00 |
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Xianjun Jiao
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abbe9ecde9
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extend support to zcu102/Zynq MPSoC ultra_scale
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2020-04-27 15:46:16 +02:00 |
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Jiao Xianjun
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03b2591cef
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revert to original index
according to test: https://github.com/open-sdr/openwifi-hw/issues/8
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2020-04-17 17:10:23 +02:00 |
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Xianjun Jiao
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60677384b9
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change the long preamble correlator first 4 sample indexes from 1 2 3 4 to 0 1 2 3
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2020-03-28 21:18:33 +01:00 |
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mmehari
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66aef6310f
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xjiao update: add soft decoding register switch
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2019-12-10 13:48:38 +01:00 |
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mmehari
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1f8bb83587
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soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM
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2019-12-10 13:45:43 +01:00 |
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Xianjun Jiao
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2643844f2f
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necessary bug fixes and improvements for openwifi
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2019-12-10 13:31:16 +01:00 |
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weiliu
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10ff8da3d7
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port dot11 to zynq
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2019-12-10 14:09:31 +01:00 |
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Jinghao Shi
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2f0e0ba953
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faq
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2017-12-09 19:05:26 -05:00 |
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Jinghao Shi
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549a7de059
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readme
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2017-04-26 14:49:53 -04:00 |
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Jinghao Shi
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31d35e91e8
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license
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2017-04-26 14:47:59 -04:00 |
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Jinghao Shi
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ae5246395b
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doc url
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2017-04-26 14:36:17 -04:00 |
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Jinghao Shi
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126c1037f5
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readme
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2017-04-25 15:24:48 -04:00 |
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Jinghao Shi
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cceefb6c77
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usrp
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2017-04-25 15:19:32 -04:00 |
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Jinghao Shi
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39b6115360
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docs
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2017-04-21 13:42:20 -04:00 |
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Jinghao Shi
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079744bec1
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fix dot11 port pinout
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2017-04-21 13:42:09 -04:00 |
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Jinghao Shi
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b7361b2feb
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fix port pinout
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2017-04-21 13:41:49 -04:00 |
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Jinghao Shi
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c0ad55abb6
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remve unused variable in descramble.v
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2017-04-21 13:41:28 -04:00 |
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Jinghao Shi
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436aa53ea1
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rewrite test.py
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2017-04-21 13:41:03 -04:00 |
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Jinghao Shi
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2315d0fc74
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fix window size
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2017-04-21 13:40:46 -04:00 |
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Jinghao Shi
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cc5effe283
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ht-sig
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2017-04-17 15:55:36 -04:00 |
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Jinghao Shi
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25c5d67904
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descrabmle
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2017-04-17 12:53:44 -04:00 |
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Jinghao Shi
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556794ae2e
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add coregen files
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2017-04-14 16:29:33 -04:00 |
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Jinghao Shi
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a827623ab5
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doc
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2017-04-14 16:29:19 -04:00 |
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Jinghao Shi
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e5d4dc7cfc
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enlarge num_sample
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2017-04-14 11:01:18 -04:00 |
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Jinghao Shi
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bcee4f66a1
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fix packet detection
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2017-04-14 11:01:05 -04:00 |
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Jinghao Shi
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701cbb70c9
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variable name
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2017-04-14 11:00:46 -04:00 |
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Jinghao Shi
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0b0723899a
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rotate
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2017-04-14 11:00:33 -04:00 |
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Jinghao Shi
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47577f7099
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fix comment
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2017-04-14 11:00:12 -04:00 |
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Jinghao Shi
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191b197d5e
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fix polarity pattern
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2017-04-14 11:00:01 -04:00 |
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Jinghao Shi
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4f313f3ef9
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doc
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2017-04-14 10:59:40 -04:00 |
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Jinghao Shi
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4e3c57c5f3
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working on eq
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2017-04-12 15:49:17 -04:00 |
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Jinghao Shi
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297162af13
|
working
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2017-04-07 16:51:06 -04:00 |
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Jinghao Shi
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c4c81b2766
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fix lts index
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2017-04-07 16:50:16 -04:00 |
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Jinghao Shi
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20279b42a4
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fix long preamble sample beginning index
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2017-04-07 16:49:41 -04:00 |
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Jinghao Shi
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652c8c1bb7
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working on sync_long
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2017-04-07 16:48:34 -04:00 |
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Jinghao Shi
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df46bc5309
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phase lut
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2017-04-07 11:37:11 -04:00 |
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Jinghao Shi
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779b3651a4
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remove unused verilog files
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2017-04-07 11:36:51 -04:00 |
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Jinghao Shi
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8375779a03
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refactor name
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2017-04-07 11:36:41 -04:00 |
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Jinghao Shi
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4dd053ebf8
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use delayT
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2017-04-07 11:36:21 -04:00 |
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Jinghao Shi
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28c57fc17f
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doc
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2017-04-05 16:06:23 -04:00 |
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