28 Commits

Author	SHA1	Message	Date
Xianjun Jiao	6a0073ee58	remove debug	2020-06-12 10:24:59 +02:00
Xianjun Jiao	abbe9ecde9	extend support to zcu102/Zynq MPSoC ultra_scale	2020-04-27 15:46:16 +02:00
Jiao Xianjun	03b2591cef	revert to original index ... according to test: https://github.com/open-sdr/openwifi-hw/issues/8	2020-04-17 17:10:23 +02:00
Xianjun Jiao	60677384b9	change the long preamble correlator first 4 sample indexes from 1 2 3 4 to 0 1 2 3	2020-03-28 21:18:33 +01:00
mmehari	66aef6310f	xjiao update: add soft decoding register switch	2019-12-10 13:48:38 +01:00
mmehari	1f8bb83587	soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM	2019-12-10 13:45:43 +01:00
Xianjun Jiao	2643844f2f	necessary bug fixes and improvements for openwifi	2019-12-10 13:31:16 +01:00
weiliu	10ff8da3d7	port dot11 to zynq	2019-12-10 14:09:31 +01:00
Jinghao Shi	079744bec1	fix dot11 port pinout	2017-04-21 13:42:09 -04:00
Jinghao Shi	b7361b2feb	fix port pinout	2017-04-21 13:41:49 -04:00
Jinghao Shi	c0ad55abb6	remve unused variable in descramble.v	2017-04-21 13:41:28 -04:00
Jinghao Shi	556794ae2e	add coregen files	2017-04-14 16:29:33 -04:00
Jinghao Shi	e5d4dc7cfc	enlarge num_sample	2017-04-14 11:01:18 -04:00
Jinghao Shi	701cbb70c9	variable name	2017-04-14 11:00:46 -04:00
Jinghao Shi	0b0723899a	rotate	2017-04-14 11:00:33 -04:00
Jinghao Shi	47577f7099	fix comment	2017-04-14 11:00:12 -04:00
Jinghao Shi	191b197d5e	fix polarity pattern	2017-04-14 11:00:01 -04:00
Jinghao Shi	297162af13	working	2017-04-07 16:51:06 -04:00
Jinghao Shi	20279b42a4	fix long preamble sample beginning index	2017-04-07 16:49:41 -04:00
Jinghao Shi	779b3651a4	remove unused verilog files	2017-04-07 11:36:51 -04:00
Jinghao Shi	8375779a03	refactor name	2017-04-07 11:36:41 -04:00
Jinghao Shi	4dd053ebf8	use delayT	2017-04-07 11:36:21 -04:00
Jinghao Shi	cf42e1b7ae	working	2017-04-03 15:48:25 -04:00
Jinghao Shi	506472dec3	add sim_out dir	2017-04-03 15:25:48 -04:00
Jinghao Shi	1ad9302fc3	readme	2017-04-03 14:31:25 -04:00
Jinghao Shi	d3ff9e7ce8	makefile	2017-04-03 14:05:07 -04:00
Jinghao Shi	bf4701fb39	makefile	2017-04-03 12:59:32 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00