Xianjun Jiao
441850b113
NO code change. Formating
2023-02-09 16:14:10 +01:00
Xianjun Jiao
a097294415
Change the initial sensitivity th from -95 to -85:
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-85 is a good tradeoff between sensitivity and false alarm
-95 will result in lots of non necessary decoding action (false alarm), and sometimes it leads to abnormal receiver state (stuck, etc)
-95 should be set manually while doing conductive test with wifi tester
2023-02-03 16:27:51 +01:00
Xianjun Jiao
2a5da37c58
Add driver support for euqalizer monitor:
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When the equalizer out is too small (48 out of 52/56) for SIGNAL decoding, watchdoc will reset the receiver
2023-02-03 16:26:58 +01:00
Xianjun Jiao
e273351b99
Add/Set the default fft_win_shift of new openofdm_rx to 1, which gives better throughput while receiving udp traffic
2023-01-17 13:51:25 +01:00
Xianjun Jiao
6c6cf95190
Refactor according to ...
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Some xpu registers are removed
2023-01-17 13:31:10 +01:00
Xianjun Jiao
26825b8b77
Add OPENWIFI_MIN_SIGNAL_LEN_TH 14 to set min pkt length threshold for FPGA signal watchdog
2023-01-17 13:14:59 +01:00
Xianjun Jiao
7f48aacad4
Change default OPENOFDM_RX_RSSI_DBM_TH_DEFAULT to a value that will not affect sensitivity
2023-01-17 13:12:55 +01:00
thavinga
bc98f5bb6c
Driver changes for FPGA SPI Tx LO control
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- Manually issue Tx Quadrature calibration if frequency change is more than 100MHz
- Disable FPGA SPI module before calibration
- Add xpu reg 13 to disable control manually
2022-03-29 09:56:20 +02:00
Xianjun Jiao
f6ba34deac
Add/adjust missing register modification in tx_intf
2022-03-28 20:49:37 +02:00
Xianjun Jiao
585a56016e
openofdm_rx initialization with the help of macro definition in hw_def.h:
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Now changing the macro in hw_def.h will change the related initialization part in all related drivers (rx_intf/xpu/openofdm_rx)
2022-03-28 20:48:36 +02:00
Xianjun Jiao
12b235cd18
Remove the unnecessary variable and code from openofdm_rx interface
2022-03-28 20:44:42 +02:00
Xianjun Jiao
469b96d342
Remove/modify the tx_intf register API according to the new FPGA:
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1. mixer/duc is not needed because we will not use offset tuning after the ad9361 tx lo control via FPGA is supported.
2. source selection register is not needed as well.
3. arbitrary IQ register is added.
2022-03-28 20:35:17 +02:00
Xianjun Jiao
4d39160b06
Add the missing TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH into tx_intf_mode
2022-03-28 20:29:26 +02:00
Xianjun Jiao
a7396dd938
Some minor unused comments
2022-03-28 20:27:36 +02:00
mmehari
0c0d5d827e
use FPGA fifo count registers instead of software queue_cnt
2022-01-06 15:07:50 +01:00
mmehari
2d12c07d4d
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type
2022-01-06 14:43:32 +01:00
mmehari
f738aefa50
A-MPDU tx aggregation support
2022-01-06 14:42:01 +01:00
mmehari
261bb9eef7
A-MPDU rx aggregation support
2022-01-06 14:13:24 +01:00
Xianjun Jiao
d14d06e508
CSI fuzzer feature -- document to be finished
2021-05-13 17:45:39 +02:00
Xianjun Jiao
913a9e947c
add ack disable register in xpu in case ack needs to be disabled in monitor mode
2021-04-05 21:51:47 +02:00
Xianjun Jiao
aed16d0502
add missing soft decoding api in hw_def.h
2021-04-05 21:50:40 +02:00
Xianjun Jiao
bb0a2c5897
in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).
2021-04-05 21:49:59 +02:00
Jiao Xianjun
55c2866f7c
Merge pull request #54 from lnceballosz/master
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NGI0 - Updating licensing aspects according REUSE
2021-02-03 16:14:49 +01:00
Jiao Xianjun
d5f8d0d664
Update hw_def.h
2021-02-03 15:36:30 +01:00
Lina Ceballos
a6085186d9
adding license and copyright headers
2021-01-20 13:30:12 +01:00
mmehari
6e3730c0c1
Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information
2020-12-29 21:33:36 +01:00
Xianjun Jiao
5deb8d18f6
sync internal
2020-12-14 13:32:15 +01:00
Xianjun Jiao
838a9007cf
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
2020-06-12 10:50:34 +02:00
Xianjun Jiao
febc5adf73
prepare upgrade
2020-04-27 09:37:04 +02:00
Xianjun Jiao
b73660ad79
prepare for release
2020-03-04 19:39:12 +01:00
Xianjun Jiao
2ee6717882
initial commit
2019-12-10 14:03:47 +01:00
