mirror of
https://github.com/open-sdr/openwifi.git
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469b96d342
1. mixer/duc is not needed because we will not use offset tuning after the ad9361 tx lo control via FPGA is supported. 2. source selection register is not needed as well. 3. arbitrary IQ register is added.
428 lines
16 KiB
C
428 lines
16 KiB
C
// Author: Xianjun jiao, Michael Mehari, Wei Liu
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// SPDX-FileCopyrightText: 2019 UGent
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// SPDX-License-Identifier: AGPL-3.0-or-later
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// #ifndef __HW_DEF_H_FILE__
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// #define __HW_DEF_H_FILE__
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const char *sdr_compatible_str = "sdr,sdr";
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enum openwifi_fpga_type {
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SMALL_FPGA = 0,
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LARGE_FPGA = 1,
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};
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enum openwifi_band {
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BAND_900M = 0,
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BAND_2_4GHZ,
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BAND_3_65GHZ,
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BAND_5_0GHZ,
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BAND_5_8GHZ,
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BAND_5_9GHZ,
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BAND_60GHZ,
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};
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// ------------------------------------tx interface----------------------------------------
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const char *tx_intf_compatible_str = "sdr,tx_intf";
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#define TX_INTF_REG_MULTI_RST_ADDR (0*4)
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#define TX_INTF_REG_MIXER_CFG_ADDR (1*4)
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#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4)
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#define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
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#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4)
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#define TX_INTF_REG_CSI_FUZZER_ADDR (5*4)
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#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4)
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#define TX_INTF_REG_MISC_SEL_ADDR (7*4)
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#define TX_INTF_REG_TX_CONFIG_ADDR (8*4)
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#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
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#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
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#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4)
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#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4)
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#define TX_INTF_REG_BB_GAIN_ADDR (13*4)
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#define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4)
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#define TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR (15*4)
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#define TX_INTF_REG_ANT_SEL_ADDR (16*4)
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#define TX_INTF_REG_PHY_HDR_CONFIG_ADDR (17*4)
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#define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4)
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#define TX_INTF_REG_PKT_INFO1_ADDR (22*4)
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#define TX_INTF_REG_PKT_INFO2_ADDR (23*4)
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#define TX_INTF_REG_PKT_INFO3_ADDR (24*4)
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#define TX_INTF_REG_PKT_INFO4_ADDR (25*4)
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#define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (26*4)
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#define TX_INTF_NUM_ANTENNA 2
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#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
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#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
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enum tx_intf_mode {
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TX_INTF_AXIS_LOOP_BACK = 0,
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TX_INTF_BYPASS,
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TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
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TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
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TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH,
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TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
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TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
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TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
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TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
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};
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const int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10};
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const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
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struct tx_intf_driver_api {
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u32 (*hw_init)(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
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u32 (*reg_read)(u32 reg);
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void (*reg_write)(u32 reg, u32 value);
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u32 (*TX_INTF_REG_MULTI_RST_read)(void);
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u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void);
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u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
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u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
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u32 (*TX_INTF_REG_CSI_FUZZER_read)(void);
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u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
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u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void);
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u32 (*TX_INTF_REG_TX_CONFIG_read)(void);
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u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
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u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
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u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void);
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u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
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u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
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u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void);
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u32 (*TX_INTF_REG_BB_GAIN_read)(void);
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u32 (*TX_INTF_REG_ANT_SEL_read)(void);
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u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void);
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u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void);
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u32 (*TX_INTF_REG_PKT_INFO1_read)(void);
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u32 (*TX_INTF_REG_PKT_INFO2_read)(void);
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u32 (*TX_INTF_REG_PKT_INFO3_read)(void);
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u32 (*TX_INTF_REG_PKT_INFO4_read)(void);
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u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
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void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
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void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value);
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void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
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void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
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void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value);
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void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
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void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value);
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void (*TX_INTF_REG_TX_CONFIG_write)(u32 value);
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void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
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void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
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void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value);
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void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
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void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
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void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value);
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void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
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void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
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void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value);
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void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value);
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void (*TX_INTF_REG_PKT_INFO1_write)(u32 value);
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void (*TX_INTF_REG_PKT_INFO2_write)(u32 value);
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void (*TX_INTF_REG_PKT_INFO3_write)(u32 value);
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void (*TX_INTF_REG_PKT_INFO4_write)(u32 value);
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};
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// ------------------------------------rx interface----------------------------------------
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const char *rx_intf_compatible_str = "sdr,rx_intf";
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#define RX_INTF_REG_MULTI_RST_ADDR (0*4)
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#define RX_INTF_REG_MIXER_CFG_ADDR (1*4)
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#define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4)
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#define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
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#define RX_INTF_REG_IQ_CTRL_ADDR (4*4)
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#define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4)
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#define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4)
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#define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)
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#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
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#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
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#define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
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#define RX_INTF_REG_BB_GAIN_ADDR (11*4)
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#define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4)
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#define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4)
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#define RX_INTF_REG_ANT_SEL_ADDR (16*4)
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#define RX_INTF_NUM_ANTENNA 2
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#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
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#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
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enum rx_intf_mode {
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RX_INTF_AXIS_LOOP_BACK = 0,
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RX_INTF_BYPASS,
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RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
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RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
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RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
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RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
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RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
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RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
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};
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const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};
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struct rx_intf_driver_api {
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u32 io_start;
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u32 base_addr;
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u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
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u32 (*reg_read)(u32 reg);
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void (*reg_write)(u32 reg, u32 value);
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u32 (*RX_INTF_REG_MULTI_RST_read)(void);
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u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
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u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
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u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
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u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
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u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
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u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
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u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
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u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
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u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
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u32 (*RX_INTF_REG_ANT_SEL_read)(void);
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u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
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void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
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void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
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void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
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void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
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void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
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void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
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void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
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void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
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void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
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void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
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void (*RX_INTF_REG_BB_GAIN_write)(u32 value);
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void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
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void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
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void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
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void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
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void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);
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};
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// ----------------------------------openofdm rx-------------------------------
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const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
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#define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4)
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#define OPENOFDM_RX_REG_ENABLE_ADDR (1*4)
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#define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4)
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#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4)
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#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)
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#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
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enum openofdm_rx_mode {
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OPENOFDM_RX_TEST = 0,
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OPENOFDM_RX_NORMAL,
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};
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struct openofdm_rx_driver_api {
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u32 power_thres;
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u32 min_plateau;
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u32 (*hw_init)(enum openofdm_rx_mode mode);
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u32 (*reg_read)(u32 reg);
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void (*reg_write)(u32 reg, u32 value);
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u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);
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void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);
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void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
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void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
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void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
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void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);
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};
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// ---------------------------------------openofdm tx-------------------------------
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const char *openofdm_tx_compatible_str = "sdr,openofdm_tx";
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#define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4)
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#define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4)
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#define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4)
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enum openofdm_tx_mode {
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OPENOFDM_TX_TEST = 0,
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OPENOFDM_TX_NORMAL,
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};
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struct openofdm_tx_driver_api {
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u32 (*hw_init)(enum openofdm_tx_mode mode);
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u32 (*reg_read)(u32 reg);
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void (*reg_write)(u32 reg, u32 value);
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void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);
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void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);
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void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);
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};
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// ---------------------------------------xpu low MAC controller-------------------------------
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// extra filter flag together with enum ieee80211_filter_flags in mac80211.h
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#define UNICAST_FOR_US (1<<9)
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#define BROADCAST_ALL_ONE (1<<10)
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#define BROADCAST_ALL_ZERO (1<<11)
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#define MY_BEACON (1<<12)
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#define MONITOR_ALL (1<<13)
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const char *xpu_compatible_str = "sdr,xpu";
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#define XPU_REG_MULTI_RST_ADDR (0*4)
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#define XPU_REG_SRC_SEL_ADDR (1*4)
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#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
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#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
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#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
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#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
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#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4)
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#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
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#define XPU_REG_LBT_TH_ADDR (8*4)
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#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
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#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
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#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4)
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#define XPU_REG_AMPDU_ACTION_ADDR (12*4)
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#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
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#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
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#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
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#define XPU_REG_CSMA_CFG_ADDR (19*4)
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#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4)
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#define XPU_REG_SLICE_COUNT_START_ADDR (21*4)
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#define XPU_REG_SLICE_COUNT_END_ADDR (22*4)
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#define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4)
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#define XPU_REG_FILTER_FLAG_ADDR (27*4)
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#define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4)
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#define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4)
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#define XPU_REG_MAC_ADDR_LOW_ADDR (30*4)
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#define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4)
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#define XPU_REG_FC_DI_ADDR (34*4)
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#define XPU_REG_ADDR1_LOW_ADDR (35*4)
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#define XPU_REG_ADDR1_HIGH_ADDR (36*4)
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#define XPU_REG_ADDR2_LOW_ADDR (37*4)
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#define XPU_REG_ADDR2_HIGH_ADDR (38*4)
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#define XPU_REG_ADDR3_LOW_ADDR (39*4)
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#define XPU_REG_ADDR3_HIGH_ADDR (40*4)
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#define XPU_REG_SC_LOW_ADDR (41*4)
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#define XPU_REG_ADDR4_HIGH_ADDR (42*4)
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#define XPU_REG_ADDR4_LOW_ADDR (43*4)
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#define XPU_REG_TRX_STATUS_ADDR (50*4)
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#define XPU_REG_TX_RESULT_ADDR (51*4)
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#define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4)
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#define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
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#define XPU_REG_RSSI_HALF_DB_ADDR (60*4)
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#define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4)
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enum xpu_mode {
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XPU_TEST = 0,
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XPU_NORMAL,
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};
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struct xpu_driver_api {
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u32 (*hw_init)(enum xpu_mode mode);
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u32 (*reg_read)(u32 reg);
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void (*reg_write)(u32 reg, u32 value);
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void (*XPU_REG_MULTI_RST_write)(u32 value);
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u32 (*XPU_REG_MULTI_RST_read)(void);
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void (*XPU_REG_SRC_SEL_write)(u32 value);
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u32 (*XPU_REG_SRC_SEL_read)(void);
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void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);
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u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);
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void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);
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u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);
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void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);
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u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);
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void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);
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u32 (*XPU_REG_ACK_FC_FILTER_read)(void);
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void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);
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u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);
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void (*XPU_REG_FILTER_FLAG_write)(u32 value);
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u32 (*XPU_REG_FILTER_FLAG_read)(void);
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void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);
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u32 (*XPU_REG_MAC_ADDR_LOW_read)(void);
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void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);
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u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void);
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void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);
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u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void);
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void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);
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u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void);
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void (*XPU_REG_BAND_CHANNEL_write)(u32 value);
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u32 (*XPU_REG_BAND_CHANNEL_read)(void);
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void (*XPU_REG_DIFS_ADVANCE_write)(u32 value);
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u32 (*XPU_REG_DIFS_ADVANCE_read)(void);
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void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value);
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u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void);
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u32 (*XPU_REG_TRX_STATUS_read)(void);
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u32 (*XPU_REG_TX_RESULT_read)(void);
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u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);
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u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);
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void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);
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void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);
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void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);
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u32 (*XPU_REG_FC_DI_read)(void);
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u32 (*XPU_REG_ADDR1_LOW_read)(void);
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u32 (*XPU_REG_ADDR1_HIGH_read)(void);
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u32 (*XPU_REG_ADDR2_LOW_read)(void);
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u32 (*XPU_REG_ADDR2_HIGH_read)(void);
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void (*XPU_REG_LBT_TH_write)(u32 value);
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u32 (*XPU_REG_LBT_TH_read)(void);
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void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);
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u32 (*XPU_REG_RSSI_DB_CFG_read)(void);
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void (*XPU_REG_CSMA_DEBUG_write)(u32 value);
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u32 (*XPU_REG_CSMA_DEBUG_read)(void);
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void (*XPU_REG_CSMA_CFG_write)(u32 value);
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u32 (*XPU_REG_CSMA_CFG_read)(void);
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void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_START_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_END_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
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u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_START_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_END_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
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void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
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void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value);
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u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void);
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void (*XPU_REG_AMPDU_ACTION_write)(u32 value);
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u32 (*XPU_REG_AMPDU_ACTION_read)(void);
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void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
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};
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// #endif
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