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Author	SHA1	Message	Date
Jinghao Shi	4f313f3ef9	doc	2017-04-14 10:59:40 -04:00
Jinghao Shi	4e3c57c5f3	working on eq	2017-04-12 15:49:17 -04:00
Jinghao Shi	297162af13	working	2017-04-07 16:51:06 -04:00
Jinghao Shi	c4c81b2766	fix lts index	2017-04-07 16:50:16 -04:00
Jinghao Shi	20279b42a4	fix long preamble sample beginning index	2017-04-07 16:49:41 -04:00
Jinghao Shi	652c8c1bb7	working on sync_long	2017-04-07 16:48:34 -04:00
Jinghao Shi	df46bc5309	phase lut	2017-04-07 11:37:11 -04:00
Jinghao Shi	779b3651a4	remove unused verilog files	2017-04-07 11:36:51 -04:00
Jinghao Shi	8375779a03	refactor name	2017-04-07 11:36:41 -04:00
Jinghao Shi	4dd053ebf8	use delayT	2017-04-07 11:36:21 -04:00
Jinghao Shi	28c57fc17f	doc	2017-04-05 16:06:23 -04:00
Jinghao Shi	63dd5a42f2	working	2017-04-03 15:48:37 -04:00
Jinghao Shi	cf42e1b7ae	working	2017-04-03 15:48:25 -04:00
Jinghao Shi	506472dec3	add sim_out dir	2017-04-03 15:25:48 -04:00
Jinghao Shi	23e1c270e0	requirements.txt	2017-04-03 14:42:56 -04:00
Jinghao Shi	8b4df2fcfe	doc init	2017-04-03 14:42:37 -04:00
Jinghao Shi	1ad9302fc3	readme	2017-04-03 14:31:25 -04:00
Jinghao Shi	d3ff9e7ce8	makefile	2017-04-03 14:05:07 -04:00
Jinghao Shi	bf4701fb39	makefile	2017-04-03 12:59:32 -04:00
Jinghao Shi	cf69020661	init	2017-04-03 12:52:37 -04:00
Jinghao Shi	379f20e652	testing inputs init	2017-04-03 12:52:31 -04:00
Jinghao Shi	20a33eb560	scripts init	2017-04-03 12:52:21 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00