Xianjun Jiao
4bdc210e86
Open the 4 queue gates all the time during xpu initialization
2022-03-29 10:13:16 +02:00
Xianjun Jiao
b597510ce3
Relax the ACK waiting condition for non block ACK case:
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If the packet type/sub-type is ACK and the length field is 14, we believe it is ACK. No matter the fcs is valid or not
2022-03-29 10:11:14 +02:00
Xianjun Jiao
066dd1bba2
fine tuning of ack tx wait time for new design
2022-03-29 10:06:27 +02:00
Xianjun Jiao
e3fb22a4b3
gpio gain delay and rssi:
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Fine tune the rssi calculation sync with gpio gain (add the same gpio gain smoothing like iq_rssi in FPGA)
2022-03-29 10:05:33 +02:00
thavinga
bc98f5bb6c
Driver changes for FPGA SPI Tx LO control
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- Manually issue Tx Quadrature calibration if frequency change is more than 100MHz
- Disable FPGA SPI module before calibration
- Add xpu reg 13 to disable control manually
2022-03-29 09:56:20 +02:00
Xianjun Jiao
585a56016e
openofdm_rx initialization with the help of macro definition in hw_def.h:
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Now changing the macro in hw_def.h will change the related initialization part in all related drivers (rx_intf/xpu/openofdm_rx)
2022-03-28 20:48:36 +02:00
mmehari
261bb9eef7
A-MPDU rx aggregation support
2022-01-06 14:13:24 +01:00
Xianjun Jiao
913a9e947c
add ack disable register in xpu in case ack needs to be disabled in monitor mode
2021-04-05 21:51:47 +02:00
Xianjun Jiao
bb0a2c5897
in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).
2021-04-05 21:49:59 +02:00
Jiao Xianjun
55c2866f7c
Merge pull request #54 from lnceballosz/master
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NGI0 - Updating licensing aspects according REUSE
2021-02-03 16:14:49 +01:00
Jiao Xianjun
9e7be83fb0
Update xpu.c
2021-02-03 15:45:09 +01:00
weiliu
2238b42bb8
improve csma state machine, force ch_idle high after decode, log cw and num_slot_random in the last attempt
2021-01-28 14:15:29 +01:00
Lina Ceballos
a6085186d9
adding license and copyright headers
2021-01-20 13:30:12 +01:00
weiliu
5680efab70
enable dynamic cw
2020-12-28 16:03:51 +01:00
Xianjun Jiao
5deb8d18f6
sync internal
2020-12-14 13:32:15 +01:00
Xianjun Jiao
838a9007cf
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
2020-06-12 10:50:34 +02:00
Xianjun Jiao
febc5adf73
prepare upgrade
2020-04-27 09:37:04 +02:00
Xianjun Jiao
2a1e074623
fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz
2020-01-07 14:17:08 +01:00
Xianjun Jiao
2ee6717882
initial commit
2019-12-10 14:03:47 +01:00
