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Open the 4 queue gates all the time during xpu initialization
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@ -440,6 +440,36 @@ static inline u32 hw_init(enum xpu_mode mode){
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xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold
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// setup time schedule of 4 slices
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// slice 0
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xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms
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xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms
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xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms
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// slice 1
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xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms
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xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms
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//xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms
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xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms
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// slice 2
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xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms
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//xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms
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xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms
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//xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms
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xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms
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// slice 3
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xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms
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//xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms
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xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms
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//xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
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xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
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// all slice sync rest
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xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
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xpu_api->XPU_REG_MULTI_RST_write(0<<7);
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printk("%s hw_init err %d\n", xpu_compatible_str, err);
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return(err);
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}
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