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Author	SHA1	Message	Date
Xianjun Jiao	6c538ca928	Add comprehensive info at the beginning of .ftr files to reproduce ad9361 ftr files. ... Also add a narrower band fir example	2023-01-17 13:53:23 +01:00
Xianjun Jiao	9f9b6708c9	Add number of read as parameter of rssi_ad9361_show.sh	2023-01-17 13:52:10 +01:00
Xianjun Jiao	e273351b99	Add/Set the default fft_win_shift of new openofdm_rx to 1, which gives better throughput while receiving udp traffic	2023-01-17 13:51:25 +01:00
Xianjun Jiao	75d924e0e8	Remove unnecessary reg code in tx_intf.c	2023-01-17 13:49:50 +01:00
Xianjun Jiao	a7af994b09	Set addr3 to addr1 for data/mgmt frame in inject_80211.c	2023-01-17 13:49:01 +01:00
Xianjun Jiao	1265742e17	Refactor initial all open slice setup in xpu.c	2023-01-17 13:48:08 +01:00
Xianjun Jiao	ec5a505373	Remove unnecessary code in xpu.c	2023-01-17 13:32:27 +01:00
Xianjun Jiao	1fa7cac08e	Format sdr.h	2023-01-17 13:31:10 +01:00
Xianjun Jiao	342bd25a0b	Refactor a bit RING_ROOM_THRESHOLD/MAX_NUM_HW_QUEUE/MAX_NUM_SW_QUEUE	2023-01-17 13:31:10 +01:00
Xianjun Jiao	6c6cf95190	Refactor according to ... ... Some xpu registers are removed	2023-01-17 13:31:10 +01:00
Xianjun Jiao	d4c3d8108e	Though the SIFS definition in 2.4GHz is 10us, the actual gap is still 16us: ... 1. Confirmed by CMW270 in OFDM mode (10us is for 11b where viterbi decoder is not needed) 2. See Signal Extension in 18.3.2.4 ERP-OFDM PPDU format of 802.11-2020	2023-01-17 13:30:58 +01:00
Xianjun Jiao	26825b8b77	Add OPENWIFI_MIN_SIGNAL_LEN_TH 14 to set min pkt length threshold for FPGA signal watchdog	2023-01-17 13:14:59 +01:00
Xianjun Jiao	7f48aacad4	Change default OPENOFDM_RX_RSSI_DBM_TH_DEFAULT to a value that will not affect sensitivity	2023-01-17 13:12:55 +01:00
Xianjun Jiao	20d92b40f5	Change the cca threshold to -62dBm. Seems help a lot in 2.4GHz	2023-01-17 13:11:59 +01:00
Xianjun Jiao	189290a596	Add channel info into rssi_show.sh and rename it	2023-01-17 13:05:14 +01:00
Xianjun Jiao	1f03c61acc	Update iq.md	2023-01-17 13:03:05 +01:00
Xianjun Jiao	0410b1af1a	Add neptunesdr files	2023-01-16 09:57:34 +01:00
thavinga	c0371e3594	Add script to read RSSI from AD9361	2023-01-10 16:16:08 +01:00
Xianjun Jiao	efa47b29f6	Update document and script for antsdr_e200	2023-01-10 16:05:33 +01:00
Jiao Xianjun	9d2c75f1e1	Update publications.md	2022-12-16 13:10:38 +01:00
Jiao Xianjun	eaf0cb68bb	Update publications.md	2022-12-08 15:58:43 +01:00
Jiao Xianjun	b147dfd152	Update publications.md	2022-11-26 10:17:20 +01:00
Jiao Xianjun	31955e7fc8	Update publications.md	2022-11-12 08:50:47 +01:00
MicroPhase	0dc81d985e	add support for antsdr_e200 (#237) ... Co-authored-by: black_pigeon <1530604142@qq.com>	2022-10-25 20:30:45 +02:00
Jiao Xianjun	3153d9640e	Update publications.md	2022-10-25 08:15:33 +02:00
Jiao Xianjun	873e4e6e84	Update publications.md	2022-10-18 16:44:10 +02:00
hexsdr	9594dc72b7	update sdrpi	2022-10-09 08:43:12 +02:00
Jiao Xianjun	39ab677c00	Update publications.md	2022-09-24 13:21:43 +02:00
Jiao Xianjun	a4e76cf696	Update publications.md	2022-09-22 10:16:00 +02:00
Jiao Xianjun	a870945492	Update publications.md	2022-09-15 11:07:56 +02:00
Xianjun Jiao	0e94d49d86	Update img to include sdrpi	2022-09-04 00:51:30 +02:00
Xianjun Jiao	38e452ce23	Rename rootfs/root/openwifi/system_top.bit.bin to other while building sd card img, in case afterwards the wgd.sh load the wrong fpga img onboard	2022-09-03 23:18:05 +02:00
Xianjun Jiao	2bbf19e8a8	update re-generate .dtb during verifying sdrpi	2022-09-03 22:57:33 +02:00
Xianjun Jiao	e3155ac1e8	Avoid cf_axi_dds reconnection in load_fpga_img.sh (otherwise crash)	2022-09-03 21:54:22 +02:00
Wei.Li	a066622e35	Sdrpi (#211) ... Add sdrpi support	2022-09-02 16:36:38 +02:00
Jiao Xianjun	f3b2e60927	Merge pull request #195 from open-sdr/master ... Sync master	2022-08-02 10:57:33 +02:00
Jiao Xianjun	c6dd9e71e5	Update packet-iq-self-loopback-test.md	2022-06-29 08:28:27 +02:00
Jiao Xianjun	7668cd233c	Merge pull request #183 from redfast00/iq-self-loopback-docs ... Fix instructions for self-loopback	2022-06-29 08:23:26 +02:00
redfast00	b6f9140315	Fix instructions for self-loopback	2022-06-24 16:43:27 +02:00
Jiao Xianjun	05506cbaa0	pre trigger length 0 (wh11d0) goes into some coner case. ... Change it to more safe value > 0. (At least 1!)	2022-06-21 11:26:04 +02:00
Jiao Xianjun	7fd216edc2	Update publications.md	2022-06-13 15:53:37 +02:00
Jiao Xianjun	46f8b19637	Update publications.md	2022-06-02 21:58:01 +02:00
Xianjun Jiao	88cef6e242	Add make clean into drv_and_fpga_package_gen.sh	2022-05-31 12:47:09 +02:00
Jiao Xianjun	d625adef57	Update videos.md	2022-05-18 21:35:53 +02:00
Jiao Xianjun	cff2d60ed5	Update README.md	2022-05-16 15:19:05 +02:00
Jiao Xianjun	e41746cb07	Update drv_fpga_dynamic_loading.md	2022-05-16 15:07:12 +02:00
Thijs Havinga	33d13ba8b4	Check for check_calib_inf.pid file ... And kill only when it exists. Avoids error message on first call of wgd.sh	2022-05-16 13:43:31 +02:00
Xianjun Jiao	e60c3d1541	120316e70c704a006b8991b121336e145da34303	2022-05-16 12:23:01 +02:00
Xianjun Jiao	55a868b0af	Remove unnecessary sync/sleep in rf_init_11n.sh	2022-05-16 12:22:28 +02:00
Jiao Xianjun	fe92f91563	Update README.md	2022-05-16 10:29:18 +02:00