Xianjun Jiao
ce26cc15c7
Userspace tool/example for arbitrary IQ generation via tx_intf
2022-03-28 11:02:59 +02:00
Xianjun Jiao
17cfeb0bf7
Add more app notes:
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1. Packet/event statistics in FPGA
2. Packet/event statistics in driver
3. Some frequent/usual trick for openwifi configuration/fine-tuning/special-setting/etc
2022-03-28 11:02:00 +02:00
weiliu
7e3e6749ba
change xilinx dma and ad9361 drv location to avoid booting problem
2022-03-26 21:03:08 +01:00
Xianjun Jiao
8dc97f7f08
Avoid the git_rev.h issue:
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When user download the repo instead of clone it.
2022-03-26 20:47:02 +01:00
Xianjun Jiao
ce40e055d2
Add modified ad9361_conv.c of our own:
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Sometimes the unstable hardware can not pass the 61.44Msps self-test/calibration. Override it to 40Msps
2022-03-26 20:34:55 +01:00
Jiao Xianjun
e9d2be2efd
Update radar-self-csi.md
2022-03-25 21:09:22 +01:00
Xianjun Jiao
38796372a8
Update the devicetree and kernel config preparing for new release:
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1. Devicetree needs to be simplified due to that we remove/disable lots of unnecessary adi FPGA blocks/functionalities
2. Add more Linux kernel modules/functionalities to easy more powerful/flexible network setup/features
2022-03-25 15:34:48 +01:00
Xianjun Jiao
b075baec2e
Merge branch 'master' into pre-release
2022-03-25 14:29:47 +01:00
Jiao Xianjun
97873317cc
Update publications.md
2022-03-23 20:09:12 +01:00
Jiao Xianjun
c20da22486
Add files via upload
2022-03-22 16:36:53 +01:00
Jiao Xianjun
dbcf06d18f
Update packet-iq-self-loopback-test.md
2022-03-22 16:24:20 +01:00
Jiao Xianjun
d16022c7a2
Update README.md
2022-03-22 15:54:02 +01:00
Jiao Xianjun
529690b6c1
Create packet-iq-self-loopback-test.md
2022-03-22 15:52:35 +01:00
Jiao Xianjun
20dd837968
Update README.md
2022-03-16 15:00:47 +01:00
Xianjun Jiao
e9a08f26b4
Add more packet type and sub-type support into inject_80211.c
2022-03-15 13:01:26 +01:00
Jiao Xianjun
1f288d27e9
Update README.md
2022-03-14 18:56:20 +01:00
Jiao Xianjun
705130a120
Update README.md
2022-03-14 18:54:23 +01:00
Jiao Xianjun
abac655ded
Update iq_2ant.md
2022-03-08 10:17:25 +01:00
Jiao Xianjun
57b28bf209
Update iq.md
2022-03-08 10:17:03 +01:00
Xianjun Jiao
981758c008
fix the link in README
2022-02-24 11:16:31 +01:00
Jiao Xianjun
56ab2d850e
Update radar-self-csi.md
2022-02-23 12:33:34 +01:00
Jiao Xianjun
4369f38ae0
Update radar-self-csi.md
2022-02-23 12:31:22 +01:00
Xianjun Jiao
a4eb20013d
Add openwifi CSI radar app note
2022-02-23 12:29:59 +01:00
Jiao Xianjun
d692cb8dcc
Add fosdem2022 presentation video
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and correct the fosdem2021 video link
2022-02-09 15:41:44 +01:00
Xianjun Jiao
46eebcc32f
Merge branch 'master' into pre-release
2022-01-28 12:22:04 +01:00
Jiao Xianjun
496966b2d7
Update publications.md
2022-01-22 12:02:36 +01:00
mmehari
9cd584f8de
Missing aggregation rules
2022-01-06 15:12:03 +01:00
mmehari
385339ab4b
tx_interrupt if/else optimization
2022-01-06 15:11:05 +01:00
mmehari
0c0d5d827e
use FPGA fifo count registers instead of software queue_cnt
2022-01-06 15:07:50 +01:00
mmehari
c098112487
bug fixes:
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1) update start_idx and blk_ack_ssn variables,
2) revert printing switch
3) update use_short_gi type (bool -> u8),
4) advance skb->tail by num_byte_pad for non aggregation flow
2022-01-06 14:53:39 +01:00
mmehari
2d12c07d4d
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type
2022-01-06 14:43:32 +01:00
mmehari
f738aefa50
A-MPDU tx aggregation support
2022-01-06 14:42:01 +01:00
mmehari
261bb9eef7
A-MPDU rx aggregation support
2022-01-06 14:13:24 +01:00
Jiao Xianjun
e9377ce537
Merge pull request #133 from open-sdr/master
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prepare for new release
2022-01-04 15:15:21 +01:00
Daniel Bovensiepen Li
0a9ca3b0a6
Minor spelling fix in the README ( #128 )
2021-12-10 19:20:42 +01:00
Jiao Xianjun
151574ece8
Update README.md
2021-11-10 23:32:42 +01:00
Jiao Xianjun
1b33d5a962
Update publications.md
2021-10-29 10:41:35 +02:00
Jiao Xianjun
f8b819e340
Update publications.md
2021-10-29 10:04:27 +02:00
Xianjun Jiao
c63537c4fb
delete unnecessary openwifi-hw submodule
2021-10-21 09:52:49 +02:00
Jiao Xianjun
abdb610f56
Scripts are adapted for SW HW decouple
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To avoid openwifi-hw github submodule in openwifi. More flexible now.
2021-10-20 22:50:30 +02:00
Jiao Xianjun
b1d5889fb5
Update skywater-130-pdk-and-asic-considerations.md
2021-10-18 13:23:06 +02:00
Xianjun Jiao
3656fa92e6
initial commit of the asic considerations
2021-10-18 13:17:53 +02:00
Jiao Xianjun
0b2b6089c6
Update publications.md
2021-10-16 08:44:13 +02:00
Jiao Xianjun
ed343c37f8
Update publications.md
2021-10-15 15:24:48 +02:00
Jiao Xianjun
1682b23bf4
Clarify the command in csi.md
2021-10-14 15:36:06 +02:00
Jiao Xianjun
72c90e5e32
Merge pull request #104 from open-sdr/fix_large_ping_delay_igent
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Fix the issue of iGent env related big ping delay:
2021-10-13 09:32:21 +02:00
Jiao Xianjun
bab95fd73b
Merge pull request #102 from open-sdr/sdrctl_lbt_th
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Use drv_xpu register 0 for LBT threshold setting.
2021-10-04 16:39:11 +02:00
Xianjun Jiao
b60e485eb5
Fix the possible wrong last_auto_fpga_lbt_th saving:
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1. Remove the last_auto_fpga_lbt_th saving from sdrctl set reg command. Otherwise, repeated sdrctl set reg will save wrong value into last_auto_fpga_lbt_th
2. The last_auto_fpga_lbt_th is only set in ad9361_rf_set_channel, which is called at least once by Linux after NIC is up
2021-10-04 09:59:43 +02:00
Xianjun Jiao
109b1cfd3a
Fix the issue of iGent env related big ping delay:
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1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard
2. The issue does not happen when zcu102 is client and zedboard is AP
3. The issue (most likely) does not happen in places other than iGent (like Pablo home)
4. Sometimes it does happen at my home when I test zcu102 as AP together with COTS WiFi
5. Indeed seems like the environment related. Guess some quick small packets in the environment quickly flush/round-up/mess-up the rx dma cyclic buffer, and the rx interrupt internal static variable target_buf_idx_old loses track of the background automatic rx dma cyclic buffer
6. The fix is for all board types (zcu102, zedboard, 7035, etc)
7. The driver compiling make_all.sh script generates USE_NEW_RX_INTERRUPT macro to pre_def.h to enable the new code (while keeping the old code). You can use the script as before.
8. The logic of the fix is that exhaustive search all the rx dma cyclic buffer in rx interrupt to get packet to Linux in the first place.
2021-09-29 16:52:45 +02:00
Xianjun Jiao
8598d2949d
Use drv_xpu register 0 for LBT threshold setting. 0 will enable FPGA threshold auto setting by ad9361_rf_set_channel() in sdr.c. Other value will set static threshold (that value) to FPGA
2021-09-28 21:52:31 +02:00
