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Merge pull request #133 from open-sdr/master

Browse Source 
prepare for new release
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Jiao Xianjun 2022-01-04 15:15:21 +01:00 committed by GitHub
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.github/ISSUE_TEMPLATE/issue-description.md vendored Normal file
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---
name: Issue description
about: Please report issue by this template
title: ''
labels: ''
assignees: ''
---
0. Could you send email to xianjun.jiao@ugent.be to introduce your self?
1. Our image is used directly or you build your own image?
2. What is your own modification?
3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
4. Board/hardware type
5. WiFi channel number
6. Steps to reproduce the issue, and the related error message, screenshot, etc
7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"
8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods
9. Any other thing we need to know for helping you better?

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.gitmodules vendored
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[submodule "adi-linux-64"]
path = adi-linux-64
url = https://github.com/analogdevicesinc/linux.git
[submodule "openwifi-hw"]
path = openwifi-hw
url = https://github.com/open-sdr/openwifi-hw.git

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CONTRIBUTING.md
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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
CLA([Individual](https://users.ugent.be/~xjiao/openwifi-Individual.pdf), [Entity](https://users.ugent.be/~xjiao/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing.
CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html).

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LICENSE
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@ -659,39 +659,3 @@ specific requirements.
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
<http://www.gnu.org/licenses/>.
The license terms used for the scard class (in pcsc_usim) derived from wpa_supplicant
-------------------------------------------------------------------------------------
Modified BSD license (no advertisement clause):
Copyright (c) 2002-2017, Jouni Malinen <j@w1.fi> and contributors
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
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OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Affero General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Affero General Public License for more details.
You should have received a copy of the GNU Affero General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If your software can interact with users remotely through a computer
network, you should also make sure that it provides a way for users to
get its source. For example, if your program is a web application, its
interface could display a "Source" link that leads users to an archive
of the code. There are many ways you could offer source, and different
solutions will be better for different programs; see section 13 for the
specific requirements.
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
<http://www.gnu.org/licenses/>.

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Modified BSD license (no advertisement clause):
Copyright (c) 2002-2017, Jouni Malinen <j@w1.fi> and contributors
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name(s) of the above-listed copyright holder(s) nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too.
When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.
We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.
Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and modification follow.
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.
You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.
c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.
In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.
3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.
If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.
5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.
7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.
It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.
This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.
10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and an idea of what it does.>
Copyright (C) <yyyy> <name of author>
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989 Ty Coon, President of Vice
This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License.
Standard License Header
<one line to give the program's name and an idea of what it does.>
Copyright (C) <yyyy> <name of author>
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

5
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Copyright <YEAR> <OWNER>
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

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<!--
Author: Xianjun jiao, Michael Mehari, Wei Liu
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
# openwifi
<img src="./openwifi-arch.jpg" width="900">
**openwifi:** Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio).
This repository includes Linux driver and software. [openwifi-hw](https://github.com/open-sdr/openwifi-hw) repository has the FPGA design.
This repository includes Linux driver and software. [openwifi-hw](https://github.com/open-sdr/openwifi-hw) repository has the FPGA design. It is **YOUR RESPONSIBILITY** to follow your **LOCAL SPECTRUM REGULATION** or use **CABLE** to avoid potential interference over the air.
[[Project document](doc)], [[Quick start](#Quick-start)], [[Application notes](doc/app_notes)]
[[Quick start](#Quick-start)]
[[Project document](doc/README.md)]
[[Application notes](doc/app_notes/README.md)]
[[Videos](doc/videos.md)]
[[Publications and How to Cite](doc/publications.md)]
[[maillist](https://lists.ugent.be/wws/subscribe/openwifi)]
[[Videos](#Videos)] [[Papers](#Papers)] [openwifi [maillist](https://lists.ugent.be/wws/subscribe/openwifi)] [[Cite openwifi project](#Cite-openwifi-project)]
Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opensource license, please contact Filip.Louagie@UGent.be. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md).
Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/blob/master/LICENSE) is the opensource license. For non-opensource and advanced feature license, please contact Filip.Louagie@UGent.be. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md).
**Features:**
@ -17,16 +26,18 @@ Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opens
- 20MHz bandwidth; 70 MHz to 6 GHz frequency range
- Mode tested: Ad-hoc; Station; AP, Monitor
- DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
- [802.11 packet injection and fuzzing](doc/app_notes/inject_80211.md)
- [CSI](doc/app_notes/csi.md): Channel State Information, freq offset, equalizer to computer
- [CSI fuzzer](doc/app_notes/csi_fuzzer.md): Create artificial channel response in WiFi transmitter
- [[IQ capture](doc/app_notes/iq.md)]: real-time AGC, RSSI, IQ sample to computer. [[Dual antenna version](doc/app_notes/iq_2ant.md)]
- Configurable channel access priority parameters:
- duration of RTS/CTS, CTS-to-self
- SIFS/DIFS/xIFS/slot-time/CW/etc
- Time slicing based on MAC address
- Time slicing based on MAC address (time gated/scheduled FPGA queues)
- Easy to change bandwidth and frequency:
- 2MHz for 802.11ah in sub-GHz
- 10MHz for 802.11p/vehicle in 5.9GHz
- CSI (Channel State Information, freq offset, equalizer to computer) [[CSI notes](doc/app_notes/csi.md)]
- IQ capture (real-time AGC, RSSI, IQ sample to computer) [[IQ notes](doc/app_notes/iq.md)][[IQ notes for dual antenna](doc/app_notes/iq_2ant.md)]
- On roadmap: **802.11ax**
- **802.11ax** under development
**Performance (AP: openwifi at channel 44, client: TL-WDN4200 N900 USB Dongle):**
- AP --> client: 30.6Mbps(TCP), 38.8Mbps(UDP)
@ -34,15 +45,16 @@ Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opens
**Supported SDR platforms:** (Check [Porting guide](#Porting-guide) for your new board if it isn't in the list)
board_name|board combination|status|SD card img
-------|-------|----|----
zc706_fmcs2|Xilinx ZC706 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz)
zed_fmcs2|Xilinx zed board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz)
adrv9364z7020|ADRV9364-Z7020 + ADRV1CRR-BOB|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz)
adrv9361z7035|ADRV9361-Z7035 + ADRV1CRR-BOB/FMC|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz)
zc702_fmcs2|Xilinx ZC702 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz)
zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-64bit.img.xz)
zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future
board_name|board combination|status|SD card img|Vivado license
-------|-------|----|----|-----
zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|Need
zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need
adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need
adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|Need
zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need
antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need
zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.2.0-leuven-2-64bit.img.xz)|Need
zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need
- board_name is used to identify FPGA design in openwifi-hw/boards/
- Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial.
@ -57,14 +69,13 @@ zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future
[[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)]
[[Special note for 11b](#Special-note-for-11b)]
[[Porting guide](#Porting-guide)]
[[Project document](doc)]
[[Application notes](doc/app_notes)]
[[Project document](doc/README.md)]
[[Application notes](doc/app_notes/README.md)]
## Quick start
- Burn openwifi board specific img file (from the table) into a SD card ("Open With Disk Image Writer". Or "dd" command after unzip). The SD card has two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer:
- Copy files in **openwifi/board_name** to the base directory of BOOT partiton.
- Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partiton
- Copy files in **openwifi/board_name** to the base directory of BOOT partition.
- Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partition
- Connect two antennas to RXA/TXA ports. Config the board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on.
- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**.
```
@ -72,18 +83,19 @@ zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future
```
- On board, run openwifi AP and the on board webserver
```
~/openwifi/fosdem.sh
~/openwifi/fosdem-11ag.sh
```
- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your deivce, you should see the webpage hosted by the webserver on board.
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board.
- Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh.
- Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts)
- To give the Wi-Fii client internet access, configure routing/NAT **on the PC**:
- To give the Wi-Fi client internet access, configure routing/NAT **on the PC**:
```
sudo sysctl -w net.ipv4.ip_forward=1
sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE
sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
```
**ethX** is the PC NIC name connecting the board. **ethY** is the PC NIC name connecting internet.
**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
- To monitor **real-time CSI (Chip State Information)**, such as timestamp, frequency offset, channel state, equalizer, please refer to [[CSI notes](doc/app_notes/csi.md)].
@ -108,26 +120,25 @@ The board actually is an Linux/Ubuntu computer which is running **hostapd** to o
## Update FPGA
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to udpate the fpga bitstream on board.
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the fpga bitstream on board.
- Install Vivado/SDK 2018.3 (If you don't need to generate new FPGA bitstream, WebPack version without license is enough)
- Setup environment variables (use absolute path):
```
export XILINX_DIR=your_Xilinx_directory
export OPENWIFI_DIR=your_openwifi_directory
export OPENWIFI_HW_DIR=your_openwifi-hw_directory
export BOARD_NAME=your_board_name
```
- Get the latest FPGA bitstream from openwifi-hw, generate BOOT.BIN and transfer it on board via ssh channel:
- Pick the FPGA bitstream from openwifi-hw, and generate BOOT.BIN and transfer it on board via ssh channel:
```
$OPENWIFI_DIR/user_space/get_fpga.sh $OPENWIFI_DIR
For Zynq 7000:
$OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME
cd openwifi/user_space; ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME
For Zynq MPSoC (like zcu102 board):
$OPENWIFI_DIR/user_space/boot_bin_gen_zynqmp.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME
cd openwifi/user_space; ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME
scp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN root@192.168.10.122:
cd openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin; scp ./BOOT.BIN root@192.168.10.122:
```
- On board: Put the BOOT.BIN into the BOOT partition.
```
@ -139,27 +150,29 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
## Update Driver
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to udpate the driver on board.
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the driver on board.
- Prepare Analog Devices Linux kernel source code (only need to run once):
```
$OPENWIFI_DIR/user_space/prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT build
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
```
**Note**: In Ubuntu, gcc-10 might have issue ('yylloc' error), so use gcc-9 if you encounter error.
- Compile the latest openwifi driver
```
$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
```
- Copy the driver files to the board via ssh channel
```
scp `find $OPENWIFI_DIR/driver/ -name \*.ko` root@192.168.10.122:openwifi/
cd openwifi/driver; scp `find ./ -name \*.ko` root@192.168.10.122:openwifi/
```
Now you can use **wgd.sh** on board to load the new openwifi driver.
**Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need to follow [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to generate your new SD card image.
## Update sdrctl
- Copy the sdrctl source files to the board via ssh channel
```
scp `find $OPENWIFI_DIR/user_space/sdrctl_src/ -name \*` root@192.168.10.122:openwifi/sdrctl_src/
cd openwifi/user_space/sdrctl_src; scp `find ./ -name \*` root@192.168.10.122:openwifi/sdrctl_src/
```
- Compile the sdrctl **on board**:
```
@ -168,7 +181,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
## Easy Access and etc
- FPGA and driver on board update scripts
- Setup [ftp server](https://help.ubuntu.com/lts/serverguide/ftp-server.html) on PC, allow anonymous and change ftp root directory to $OPENWIFI_DIR.
- Setup [ftp server](https://help.ubuntu.com/lts/serverguide/ftp-server.html) on PC, allow anonymous and change ftp root directory to the openwifi directory.
- On board:
```
./sdcard_boot_update.sh $BOARD_NAME
@ -186,12 +199,12 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
```
export SDCARD_DIR=sdcard_mount_point
export XILINX_DIR=your_Xilinx_directory
export OPENWIFI_DIR=your_openwifi_directory
export OPENWIFI_HW_DIR=your_openwifi-hw_directory
export BOARD_NAME=your_board_name
```
- Run script to update SD card:
```
$OPENWIFI_DIR/user_space/update_sdcard.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR
cd openwifi/user_space; ./update_sdcard.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR
```
- Config your board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on.
- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with one time password **analog**.
@ -201,10 +214,10 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
- Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config.
```
sudo sysctl -w net.ipv4.ip_forward=1
sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE
sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
```
**ethX** is the PC NIC name connecting the board. **ethY** is the PC NIC name connecting internet.
**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
- Run **one time** script on board to complete post installation/config (After this, password becomes **openwifi**)
@ -224,43 +237,18 @@ For hostapd program, 802.11b rates can be suppressed using configuration command
On the other hand, the wpa_supplicant program on the client side (commercial Wi-Fi dongle/board) cannot suppress 802.11b rates out of the box in 2.4GHz band, so there will be an issue when connecting openwifi (OFDM only). A patched wpa_supplicant should be used at the client side.
```
sudo apt-get install libssl1.0-dev
$OPENWIFI_DIR/user_space/build_wpa_supplicant_wo11b.sh $OPENWIFI_DIR
cd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh
```
## Porting guide
This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 4fea7c5 (2019 r1) of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2019_R1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
- Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help)
- Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository)
- "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor".
- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached deivce (FPGA blocks in our case).
- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case).
- We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design.
- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN and Linux kernel uImage and put them together to build the full SD card image.
## Videos
## License
Demo [[youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)]
FOSDEM2020 [[youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)]
Low latency for gaming and introduction [[youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)]
CSI (Channel State Information) [[twitter](https://twitter.com/i/status/1314207380561780738)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)]
## Papers
- [openwifi: a free and open-source IEEE802.11 SDR implementation on SoC](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf)
- [csi murder](https://ans.unibs.it/projects/csi-murder/)
Openwifi was born in [ORCA project](https://www.orca-project.eu/) (EU's Horizon2020 programme under agreement number 732174).
## Cite openwifi project
Any use of openwifi project which results in a publication should include a citation via (bibtex example):
```
@electronic{openwifigithub,
author = {Xianjun, Jiao and Wei, Liu and Michael, Mehari},
title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design},
url = {https://github.com/open-sdr/openwifi},
year = {2019},
}
```
This project is available as open source under the terms of the AGPL 3.0 Or later. However, some elements are being licensed under GPL 2-0 or later and BSD 3 license . For accurate information, please check individual files.

2
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@ -1 +1 @@
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@ -1 +1 @@
Subproject commit 4fea7c58ad92283acb90f182821b51d72b6afefa
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doc/README.md
View File

@ -1,3 +1,10 @@
<!--
Author: Xianjun jiao, Michael Mehari, Wei Liu
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
# Openwifi document
<img src="./openwifi-detail.jpg" width="1100">
@ -10,7 +17,7 @@ Above figure shows software and hardware/FPGA modules that compose the openwifi
- [Regulation and channel config](#Regulation-and-channel-config)
- [Analog and digital frequency design](#Analog-and-digital-frequency-design)
- [Debug methods](#Debug-methods)
- [Application notes](app_notes)
- [Application notes](app_notes/README.md)
## Driver and software overall principle
@ -53,7 +60,7 @@ sdrctl dev sdr0 set para_name value
```
para_name|meaning|comment
---------|-------|----
slice_idx|the slice that will be set/get|0~3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwize the start/end of different slices have different actual time
slice_idx|the slice that will be set/get|0 to 3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwise the start/end of different slices have different actual time
addr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
slice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999
slice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000
@ -65,11 +72,13 @@ tsf| sets TSF value| it requires two values "high_TSF low_TSF". Decimal
sdrctl dev sdr0 get reg module_name reg_idx
sdrctl dev sdr0 set reg module_name reg_idx reg_value
```
module_name refers to the name of driver functionality, can be drv_rx/drv_tx/drv_xpu. Related registers are defined in sdr.h (drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val)
module_name drv_rx/drv_tx/drv_xpu refers to the corresponding driver functionality. Related registers are defined in sdr.h. Search drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val in sdr.c to see their functionalities.
module_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h.
module_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h and mapped to slv_regX in .v file (X is the register index). Check rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu.c and .v files to see their functionalities.
module_name: **drv_rx**
Please be aware that some registers are set by sdr.c in real-time (instructed by Linux mac80211), so be careful when set them manually.
module_name: **drv_rx** (for full list, search drv_rx_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
@ -78,7 +87,7 @@ reg_idx|meaning|comment
(In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command)
module_name: **drv_tx**
module_name: **drv_tx** (for full list, search drv_tx_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
@ -86,11 +95,11 @@ reg_idx|meaning|comment
1|tx antenna selection|0:tx1, 1:tx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh
7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON)
module_name: **drv_xpu**
module_name: **drv_xpu** (for full list, search drv_xpu_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
7|git revision when build the driver|example: return value 0071bc74 means git revision is 071bc74 (the 1st 0 must be removed!)
7|git revision when build the driver|example: return value 0071bc74 means git revision is 071bc74 (the 1st 0 is always 0!)
module_name: **rf**
@ -98,58 +107,83 @@ reg_idx|meaning|comment
-------|-------|----
x|x|to be defined
module_name: **rx_intf**
module_name: **rx_intf** (for full list, check rx_intf.c and **slv_reg** in rx_intf.v)
reg_idx|meaning|comment
-------|-------|----
1|trigger for ILA debug|bit4 and bit0. Please check slv_reg1 in rx_intf.v
2|enable/disable rx interrupt|256(0x100):disable, 0:enable
3|get loopback I/Q from tx_intf|256(0x100):from tx_intf, 0:from ad9361 ADC
11|rx digital I/Q gain|number of bit shift to left. default 4 in rx_intf.c: rx_intf_api->RX_INTF_REG_BB_GAIN_write(4)
13|delay from RX DMA complete to RX packet interrupt|unit 0.1us
16|rx antenna selection|0:ant0, 1:ant1. default 0 in rx_intf.c: rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel)
module_name: **tx_intf**
module_name: **tx_intf** (for full list, check tx_intf.c and **slv_reg** in tx_intf.v)
reg_idx|meaning|comment
-------|-------|----
1|DUC config|tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg) in tx_intf.c and openwifi-hw/ip/mixer_duc/src/mixer_duc.cpp
4|CTS to Self config|auto set by cts_reg in openwifi_tx of sdr.c. bit31: enable/disable, bit30: rate selection: 1: use traffic rate, 0: manual rate in bit7-4, bit23-8: duration
6|CTS to Self sending delay (for SIFS)|unit 0.1us. bit13-0 for 2.4GHz, bit29-16 for 5GHz
11|threshold for FPGA fifo almost full|driver(sdr.c) read 1bit flag in slv_reg21 (4bit in total for 4 queue) to know the FPGA fifo/queue is almost full.
12|threshold to pause openofdm_tx|back pressure flow control for I/Q generation speed of openofdm_tx
13|tx I/Q digital gain before DUC|current optimal value: 100
14|enable/disable tx interrupt|196672(0x30040):disable, 64(0x40):enable
14|enable/disable tx interrupt|196612(0x30004):disable, 4:enable
16|tx antenna selection|1:ant0, 2:ant1. default 1 in tx_intf.c: tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel)
21|queue almost full flag|4bit for 4 queue. criteria is the threshold in slv_reg11. check by tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read() in sdr.c
module_name: **rx**
module_name: **rx** (for full list, check openofdm_rx.c and **slv_reg** in openofdm_rx.v)
reg_idx|meaning|comment
-------|-------|----
2|power trigger threshold|default 0. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0)
3|minimum plateau used for short preamble detection|default 100. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100)
4|soft or hard decision for viterbi decoder|0:hard, 1:soft. default 1. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write(1)
20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working
module_name: **tx**
module_name: **tx** (for full list, check openofdm_tx.c and **slv_reg** in openofdm_tx.v)
reg_idx|meaning|comment
-------|-------|----
1|pilot scrambler initial state|lowest 7 bits are used. 0x7E by default in openofdm_tx.c
2|data scrambler initial state|lowest 7 bits are used. 0x7F by default in openofdm_tx.c
module_name: **xpu**
module_name: **xpu** (for full list, check xpu.c and **slv_reg** in xpu.v)
reg_idx|meaning|comment
-------|-------|----
1|mute rx I/Q when tx|0:mute (default), 1:unmute, which means rx baseband will receive our own tx signal. Rx packet and tx packet (such as ACK) can be monitored in FPGA for timing analysis
2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 32bit
3|TSF timer high 32bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB
4|band and channel number setting|see enum openwifi_band in hw_def.h. it will be set automatically by Linux. normally you shouldn't set it
11|max number of retransmission in FPGA|normally number of retransmissions controlled by Linux in real-time. If you write non-zeros value to this register, it will override Linux real-time setting
19|CSMA enable/disable|3758096384(0xe0000000): disable, 3:enable
1|mute rx I/Q when tx|0:mute when tx, 1:unmute, which means rx baseband will receive tx signal from its own. Rx packet and tx packet (such as ACK) can be monitored in FPGA for timing analysis
2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 31bit
3|TSF timer high 31bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB
4|band, channel and ERP short slot setting|see enum/define in hw_def.h. set automatically by Linux. manual set will be overrided unless you change sdr.c
5|DIFS and backoff advance (us)|advance (us) for tx preparation before the end of DIFS/backoff. bit7-0:DIFS advance, bit15-8: backoff advance
6|forced idle, CSMA settings|bit7-0: forced channel idle (us) after decoding done to avoid false alarm caused by strong "AGC tail" signal. bit31: NAV enable, bit30: DIFS enable, bit29: EIFS enable, bit28: dynamic CW enable (when disable, CW is taken from bit3-0 of register 19)
7|some RSSI and delay setting|please check xpu.v (search slv_reg7)
8|RSSI threshold for channel idle/busy|set by ad9361_rf_set_channel --> xpu_api->XPU_REG_LBT_TH_write
9|some time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9)
10|BB RF delay setting|bit7-0: BB RF delay (0.1us), bit11-8: RF end extended time (0.1us). check xpu.v (search slv_reg10)
11|ACK control and max num retransmission|bit4: 0:normal ACK, 1:disable auto ACK reply in FPGA. bit3-0: 0: the number of retransmission is decided by Linux, non-zero: Linux auto setting about num of retransmission will be replaced by this value
16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet
17|setting when wait for ACK in 5GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet
18|setting for sending ACK|unit 0.1us. bit14-0: ACK sending delay in 2.4GHz, bit30-16: ACK sending delay in 5GHz
19|CW min and max setting for 4 FPGA queues|bit3-0: CW min for queue 0, bit7-4: CW max for queue 0, bit11-8: CW min for queue 1, bit15-12: CW max for queue 1, bit19-16: CW min for queue 2, bit23-20: CW max for queue 2, bit27-24: CW min for queue 3, bit31-28: CW max for queue 3. automatically set by openwifi_conf_tx of sdr.c
26|CTS to RTS setting|bit15-0: extra duration, bit20-16: rate/MCS, bit31: 0:enable CTStoRTS 1:disable CTStoRTS
27|FPGA packet filter config|check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)
28|BSSID address low 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
29|BSSID address high 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
30|openwifi MAC address low 32bit|
31|openwifi MAC address high 32bit|check XPU_REG_MAC_ADDR_write in sdr.c to see how we set MAC address to FPGA when NIC start
28|BSSID address low 32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_LOW_write in openwifi_bss_info_changed of sdr.c
29|BSSID address high 32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c
30|MAC address low 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
31|MAC address high 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
58|TSF runtime value low 32bit|read only
59|TSF runtime value high 32bit|read only
63|git revision when build the FPGA|example: return value 065272ac means git revision is 65272ac (the 1st 0 must be removed!)
63|git revision when build the FPGA|example: return value 065272ac means git revision is 65272ac (the 1st 0 is always 0)
## Rx packet flow and filtering config
After FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c will be triggered to do necessary operation and give the information to upper layer (Linux mac80211 subsystem).
After FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c serves the interrupt and gives the necessary information to upper layer (Linux mac80211 subsystem) via ieee80211_rx_irqsafe.
- frame filtering
The FPGA frame filtering configuration is done in real-time by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is bad. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, openwifi_configure_filter() will set **MONITOR_ALL** to the frame filtering module pkt_filter_ctl.v in FPGA. This makes sure transfer all received packets to Linux mac80211 via rx interrupt.
The FPGA frame filtering configuration is done in real-time by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is bad. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, all received packets (including ACK) will be given to Linux mac80211.
- main rx interrupt operations in openwifi_rx_interrupt()
- get raw content from DMA buffer. When Linux receives interrupt from FPGA rx_intf module, the content has been ready in Linux DMA buffer
@ -165,16 +199,16 @@ The FPGA frame filtering configuration is done in real-time by function openwifi
Linux mac80211 subsystem calls openwifi_tx() to initiate a packet sending.
- main operations in openwifi_tx()
- get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration use
- get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration
- packet length and MCS
- unicast or broadcast? does it need ACK? how many retransmissions at most are allowed to be tried by FPGA in case ACK is not received in time?
- which time slice in FPGA the packet should go?
- which queue (time slice) in FPGA the packet should go?
- should RTS-CTS be used? (Send RTS and wait for CTS before actually send the data packet)
- should CTS-to-self be used? (Send CTS-to-self packet before sending the data packet. You can force this on by force_use_cts_protect = true;)
- should a sequence number be set for this packet?
- should a sequence number be inserted?
- generate SIGNAL field according to length and MCS information. Insert it before the packet for the future openofdm_tx FPGA module use
- generate FPGA/PHY sequence number (priv->phy_tx_sn) for internal use (cross check between Linux and FPGA)
- config FPGA register according to the above information to make sure FPGA do correct actions according to the packet specific requirement.
- maintain sequence number (ring->bd_wr_idx) for internal use (cross check between Linux and FPGA)
- config FPGA register according to the above information to help FPGA do correct actions according to the packet specific requirement.
- fire DMA transmission from Linux to one of FPGA tx queues. The packet may not be sent immediately if there are still some packets in FPGA tx queue (FPGA does the queue packet transmission according to channel and low MAC state)
Each time when FPGA sends a packet, an interrupt will be raised to Linux reporting the packet sending result. This interrupt handler is openwifi_tx_interrupt().
@ -182,12 +216,12 @@ Each time when FPGA sends a packet, an interrupt will be raised to Linux reporti
- main operations in openwifi_tx_interrupt()
- get necessary information/status of the packet just sent by FPGA
- packet length and sequence number to capture abnormal situation (cross checking between Linux and FPGA)
- packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions are used for the packet sending (in case FPGA doesn't receive ACK in time, FPGA will do retransmission immediately)
- packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions have been done (in case FPGA doesn't receive ACK in time, FPGA will do retransmission according to CSMA/CA low MAC state)
- send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe()
## Regulation and channel config
SDR is a powerful tool for research. It is the user's duty to align with local spectrum regulation.
SDR is a powerful tool for research. It is the user's responsibility to align with local spectrum regulation.
This section explains how openwifi config the frequency/channel range and change it in real-time. After knowing the mechanism, you can try to extend frequency/channel by yourself.
@ -199,7 +233,7 @@ dev->wiphy->regulatory_flags = xxx
wiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd);
```
sdr_regd is the predefined variable in sdr.h. You can search the definition/meaning of its type: struct ieee80211_regdomain.
Then not difficult to find out how to change the frequency range in SDR_2GHZ_CH01_14 and SDR_5GHZ_CH36_64.
Then it is not difficult to find out how to change the frequency range in SDR_2GHZ_CH01_14 and SDR_5GHZ_CH36_64.
### Supported channel
@ -220,72 +254,89 @@ Linux mac80211 (struct ieee80211_ops openwifi_ops in sdr.c) uses the "config" AP
## Analog and digital frequency design
Following figure shows the current openwifi analog and digital frequency design strategy. The Tx RF center frequency is tuned with 10MHz offset deliberately to ease Tx Lo leakage suppressed by Rx filter. This RF offset is pre-compensated by Tx DUC (Digital Up Converter) in FPGA (duc_bank_core.bd used by tx_intf.v). It combines AD9361's bandwidth, frequency, sampling rate and FPGA's digital down/up converter (ddc_bank_core.bd/duc_bank_core.bd) setting to achieve this example spectrum arrangement. Values in the figure are configurable in the openwifi design. Please be noticed that **ddc_bank_core.bd is not used anymore**. Because the digital and analog RX Lo is the same, mixer is not needed. Decimation by 2 is implemented in adc_intv.v.
Following figure shows the current openwifi analog and digital frequency design strategy. The Tx RF center frequency is tuned with 10MHz offset deliberately to ease Tx Lo leakage suppressed by Rx filter. This RF offset is pre-compensated by Tx DUC (Digital Up Converter) in FPGA (duc_bank_core.bd used by tx_intf.v). It combines AD9361's bandwidth, frequency, sampling rate and FPGA's digital up converter (duc_bank_core.bd) setting to achieve this example spectrum arrangement. Values in the figure are configurable in the openwifi design.
![](./rf-digital-if-chain-spectrum.jpg)
Above spectrum setting has two benefits:
- The Tx Lo leakage is suppressed by Rx filter
- The centered Rx Lo and single channel Rx analog filter leads to more easy/accurate RSSI estimation in FPGA (together with real-time AD9361 AGC gain value accessed via FPGA GPIO)
- The centered Rx Lo leads to more easy/accurate RSSI estimation in FPGA (together with real-time AD9361 AGC gain value accessed via FPGA GPIO)
Following figure shows the detailed configuration point in AD9361, driver (sdr.c/tx_intf.c/rx_intf.c/ad9361.c/etc) and related FPGA modules.
Following figure shows the detailed configuration point in AD9361, driver (.c file) and related FPGA modules (.v file).
![](./rf-digital-if-chain-config.jpg)
## Debug methods
### dmesg
To debug/see the basic driver behaviour, you could turn on message printing by
To debug/see the basic driver behaviour, you could turn on **dmesg** message printing by
```
See all printing:
./sdrctl dev sdr0 set reg drv_tx 7 X
./sdrctl dev sdr0 set reg drv_rx 7 X
The bit in value X controls what type of information will be printed to the dmesg (0--no print; 1--print).
bit0: error message
bit1: regular message for unicast packet (openwifi_tx/openwifi_tx_interrupt/openwifi_rx_interrupt)
bit2: regular message for broadcast packet
For example, regular message for unicast packet and error message
./sdrctl dev sdr0 set reg drv_tx 7 3
./sdrctl dev sdr0 set reg drv_rx 7 3
See only error printing:
For example, error message only:
./sdrctl dev sdr0 set reg drv_tx 7 1
./sdrctl dev sdr0 set reg drv_rx 7 1
See only regular printing:
./sdrctl dev sdr0 set reg drv_tx 7 2
./sdrctl dev sdr0 set reg drv_rx 7 2
Turn off printing:
./sdrctl dev sdr0 set reg drv_tx 7 0
./sdrctl dev sdr0 set reg drv_rx 7 0
```
and use dmesg command in Linux to see those messages. openwifi driver prints normal tx/rx packet information when a packet is sent or received. The driver also prints WARNING information if it feels something abnormal happens. You can search "printk" in sdr.c to see all the printing points.
and use **dmesg** command in Linux to see those messages. Regular printing includes tx/rx packet information when a packet is sent or received. Error printing has WARNING information if something abnormal happens. You can search "printk" in sdr.c to see all the printing points.
- tx printing example
sdr,sdr openwifi_tx: 84bytes 48M FC0208 DI002c addr1/2/3:b0481ada2ef2/66554433222a/66554433222a SC2100 flag40000012 retr6 ack1 prio2 q2 wr4 rd3
- printing from sdr driver, openwifi_tx function.
- 84bytes: packet size (length field in SIGNAL)
- 48M: MCS (rate field in SIGNAL)
- FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client).
- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK).
- addr1/2/3: address fields. Target MAC address b0481ada2ef2, source MAC address 66554433222a (openwifi).
- SC2100: Sequence Control field 0x2100, which means that the driver inserts sequence number 0x2100 to the packet under request of upper layer.
- flag40000012: flags field from upper layer struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.). Here is 0x40000012.
- retry6: upper layer tells us the maximum number of retransmissions for this packet is 6.
- ack1: upper layer tells us this packet needs ACK.
- prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background)
- q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c)
- wr4 rd3: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt).
### tx printing example
```
sdr,sdr openwifi_tx: 1410bytes ht0 540M FC0208 DI002c addr1/2/3:2ec08902fdb2/6655443322ad/6655443322ad SC2100 flag40000012 retr6 ack1 prio2 q2 wr44 rd31
```
- printing from sdr driver, openwifi_tx function
- 1410bytes: packet size (length field in SIGNAL)
- ht0: non-ht means 11a/g; ht1 means 11n
- 54M: MCS (rate field in SIGNAL)
- FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client)
- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK)
- addr1/2/3: address fields. Target MAC address 2ec08902fdb2, source MAC address 6655443322ad (openwifi)
- SC2100: Sequence Control, which means that the driver inserts sequence number 0x2100 to the packet under request of Linux mac80211
- flag40000012: flags field from Linux mac80211 struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.)
- retry6: Linux mac80211 tells driver the maximum number of transmissions for this packet is 6
- ack1: Linux mac80211 tells driver this packet needs ACK
- prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background)
- q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c)
- wr44 rd31: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt/FPGA)
- rx printing example
sdr,sdr openwifi_rx_interrupt: 28bytes 24M FC0108 DI002c addr1/2/3:66554433222a/b0481ada2ef2/66554433222a SC4760 fcs1 buf_idx13 -30dBm
- printing from sdr driver, openwifi_rx_interrupt function.
- 28bytes: packet size (length field in SIGNAL)
- 24M: MCS (rate field in SIGNAL)
- FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP).
- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK).
- addr1/2/3: address fields. Target MAC address 66554433222a (openwifi), source MAC address b0481ada2ef2.
- SC4760: Sequence Control field 0x4760, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer).
- fcs1: FCS/CRC is OK. (fcs0 means bad CRC)
- buf_idx13: current rx packet DMA buffer index 13.
- -30dBm: signal strength of this received packet.
### tx interrupt printing example
```
sdr,sdr openwifi_tx_interrupt: tx_result 02 prio2 wr28 rd25 num_rand_slot 21 cw 6
```
- printing from sdr driver, openwifi_tx_interrupt function
- tx_result: 5bit, bit3~0 tells how many tx attempts are made on this packet, and bit4 indicates NO ACK (1) or an ACK (0) is received
- prio, wr, rd: these fields can be interpreted the same way as the print in openwifi_tx function
- num_rand_slot: tells how many slots the CSMA/CA state machine waited until the packet is sent in the last tx attempt
- cw: the exponent of the Contention Window for this packet. 6 means the CW size 64. If the contention phase is never entered, CW is 0
### rx printing example
```
sdr,sdr openwifi_rx_interrupt: 796bytes ht0 120M FC0108 DI0030 addr1/2/3:6655443322f4/2ec08902fdb2/6655443322f4 SC4760 fcs1 buf_idx13 -50dBm
```
- printing from sdr driver, openwifi_rx_interrupt function
- 796bytes: packet size (length field in SIGNAL)
- ht0: non-ht means 11a/g; ht1 means 11n
- 12M: MCS (rate field in SIGNAL)
- FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP)
- DI0030: Duration/ID field 0x0030. How many us this packet will occupy the channel (including waiting for ACK)
- addr1/2/3: address fields. Target MAC address 6655443322f4 (openwifi), source MAC address 2ec08902fdb2
- SC4760: Sequence Control, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer)
- fcs1: FCS/CRC is OK. (fcs0 means bad CRC)
- buf_idx13: current rx packet DMA buffer index 13
- -50dBm: signal strength of this received packet (after calibration)
### Native Linux tools
For protocol, many native Linux tools you still could rely on. Such as tcpdump.
For analysis/debug, many native Linux tools you still could rely on. Such as tcpdump, tshark, etc.
### FPGA
For FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals. Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level funtionalities.
For FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals. Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level functionalities.

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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@ -1,3 +1,9 @@
<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
Application notes collect many small topics about using openwifi in different scenarios/modes.
- [Use openwifi on the w-iLab.t testbed remotely](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html)
@ -5,6 +11,8 @@ Application notes collect many small topics about using openwifi in different sc
- [Communication between two SDR boards under ad-hoc mode](ad-hoc-two-sdr.md)
- [From CSI (Channel State Information) to CSI (Chip State Information)](csi.md)
- [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md)
- [Capture dual antenna IQ for multi-purpose (capture collision)](iq_2ant.md)
- [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)
- [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md)
- [802.11 packet injection](inject_80211.md)
- [802.11 packet injection and fuzzing](inject_80211.md)
- [CSI fuzzer](csi_fuzzer.md)
- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/E7mer/Owfuzz)

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@ -1,3 +1,13 @@
<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- Power on two SDR boards. Call one board "adhoc1" and the other "adhoc2". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.
- Connect a computer to the adhoc1 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
@ -12,7 +22,7 @@
(Above command setup ad-hoc network at channel 44 with static IP assigned to sdr0 NIC)
iwconfig sdr0
```
- You shold see output like:
- You should see output like:
```
sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc"
Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0
@ -31,10 +41,10 @@
cd openwifi
./wgd.sh
ifconfig sdr0 up
./sdr-ad-hoc-up.sh sdr0 44 192.168.13.1
./sdr-ad-hoc-up.sh sdr0 44 192.168.13.2
iwconfig sdr0
```
- You shold see output like:
- You should see output like:
```
sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc"
Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0

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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- Power on two SDR boards. Call one board "AP board" and the other "client board". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.
- Connect a computer to the AP board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
@ -22,23 +32,36 @@
ifconfig sdr0 up
iwlist sdr0 scan
(The "openwifi" AP should be listed in the scanning results)
iwconfig sdr0 essid openwifi
wpa_supplicant -i sdr0 -c wpa-openwifi.conf
("iwconfig sdr0 essid openwifi" could also work. Less info compared to wpa_supplicant)
```
- Now the client is trying to associate with the AP. The AP board terminal should print like:
If wpa-openwifi.conf is not on board, please create it with [this content](https://github.com/open-sdr/openwifi/blob/master/user_space/wpa-openwifi.conf).
- Now the client is trying to associate with the AP. You should see like:
```
root@analog:~/openwifi# wpa_supplicant -i sdr0 -c wpa-openwifi.conf
Successfully initialized wpa_supplicant
sdr0: CTRL-EVENT-SCAN-STARTED
sdr0: SME: Trying to authenticate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)
sdr0: Trying to associate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)
sdr0: Associated with 66:55:44:33:22:8c
sdr0: CTRL-EVENT-CONNECTED - Connection to 66:55:44:33:22:8c completed [id=0 id_str=]
```
The AP board terminal should print like:
```
...
sdr0: AP-STA-CONNECTED 66:55:44:33:22:58
sdr0: STA 66:55:44:33:22:58 RADIUS: starting accounting session 1FF1C1B4-00000001
sdr0: STA 66:55:44:33:22:4c IEEE 802.11: authenticated
sdr0: STA 66:55:44:33:22:4c IEEE 802.11: associated (aid 1)
sdr0: AP-STA-CONNECTED 66:55:44:33:22:4c
sdr0: STA 66:55:44:33:22:4c RADIUS: starting accounting session 613E16DE-00000000
```
If not, please adjust antenna/distance and re-run the commands on the client side.
- After association is done, in the terminal of client:
- After association is done, in another terminal of client (**DO NOT** terminate wpa_supplicant in the original client terminal!):
```
dhclient sdr0
(Wait for it completed)
ifconfig sdr0
(Now you should see the IP address like 192.168.13.x allocated by AP)
./set_csma_normal.sh
ping 192.168.13.1
(Ping the AP)
```

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
We extend the **CSI** (Channel State Information) to **CSI** (Chip State Information)!
## Quick start
@ -22,14 +29,15 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa
```
If the second number (61, 99, ...) is not zero and keeps increasing, that means the CSI (Chip State Information) is going to the computer smoothly.
- Open another terminal on the computer, and run:
- On your computer (NOT in ssh!), run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 side_info_display.py
```
The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see 3 figures showing run-time **frequency offset**, **channel state/response** and **constellation form equalizer**. Meanwhile the python script prints the **timestamp**.
![](./csi-screen-shot.jpg)
While running, all informations are also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline.
While running, all information is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline.
## Understand the CSI feature
The CSI information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.
@ -46,7 +54,7 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa
The python and Matlab scripts are recommended for you to understand the CSI packet format precisely.
## Config the capture condition and interval
The quick start guide will monitor all CSI informations of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**".
The quick start guide will monitor all CSI information of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**".
A quick example: Capture only CSI of those packets from the device with MAC address 56:5b:01:ec:e2:8f
```
@ -93,7 +101,7 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa
The interval will become N*1ms
## Config the num_eq
The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer informations. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m.
The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer information. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m.
- When insert the kernel module, use:
```
insmod side_ch.ko num_eq_init=3

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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2021 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
[ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
CSI (Channel State Information) of WiFi systems is available in some WiFi chips and can be used for sensing the environment (keystrokes, people, object) passively and secretly.
## Concept
How could a CSI fuzzer stop unauthorized sensing?
![](./csi-fuzzer-system-before-vs-now.png)
CSI fuzzer implementation principle.
![](./csi-fuzzer-principle.png)
## Demo instructions
Thanks to the full-duplex capability and CSI extraction feature of openwifi, you can monitor the artificial channel response via [side channel](./csi.md) by Tx-Rx over the air coupling without affecting the normal operation/traffic of openwifi. Before the self-monitoring, the auto-mute during Tx needs to be disabled.
The full demo steps are:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./fosdem-11ag.sh
(setup openwifi AP)
./sdrctl dev sdr0 set reg xpu 1 1
(Disable auto-muting to listen self-TX)
insmod side_ch.ko num_eq_init=0
./side_ch_ctl wh1h2001
./side_ch_ctl wh6hffffffff
(Let's only monitor self-beacon-TX CSI over-the-air loopback)
./side_ch_ctl g1
```
Go to openwifi/user_space/side_ch_ctl_src, and run `python3 side_info_display.py 0`. You should see the over-the-air loopback CSI when CSI fuzzer is not enabled. Then stop the python3 side_info_display.py script to ease the next step.
Start another ssh session to the openwifi board:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./csi_fuzzer_scan.sh 1
(CSI fuzzer applies possible artificial CSI by scanning all values)
(csi_fuzzer.sh is called. Please read both scripts to understand these commands)
```
Go to openwifi/user_space/side_ch_ctl_src, and run `python3 side_info_display.py 0`. Now you should see that CSI keeps changing like in this [video](https://youtu.be/aOPYwT77Qdw).
# Further explanation on parameters
CSI fuzzer in openwifi system architecture and related commands.
![](./csi-fuzzer-implementation.png)
# Example fuzzed CSI
CSI self-monitoring before fuzzing.
![](./csi-fuzzer-beacon-ant-back-0.jpg)
CSI self-monitoring after fuzzing command: `csi_fuzzer.sh 1 45 0 13`
![](./csi-fuzzer-beacon-ant-back-1-45-0-13.jpg)
`csi_fuzzer_scan.sh` can scan the c1 and c2 in different styles/modes by calling `csi_fuzzer.sh`.

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# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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<!--
Author: Michael Mehari
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
## IEEE 802.11n (Wi-Fi 4)

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<!--
Author: Michael Mehari, Xianjun Jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
## 802.11 packet injection
## 802.11 packet injection and fuzzing
The Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing.
The Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing and manual/total control mode (fuzzing).
Ping and Iperf are well established performance measurement tools. However, using such tools to measure 802.11 PHY performance can be misleading, simply because they touch multiple layers in the network stack.
Luckily, the mac80211 Linux subsystem provides packet injection functionality and it allows us to have finer control over physical layer testing.
Luckily, the mac80211 Linux subsystem provides packet injection functionality when the NIC is in the monitor mode and it allows us to have finer control for physical layer testing and/or fuzzing.
To this end, we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application originally written by Andy Green <andy@warmcat.com> and maintained by George Nychis <gnychis@gmail.com>.
Besides the traditional fuzzing tool (like scapy), we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application, which is originally written by Andy Green <andy@warmcat.com> and maintained by George Nychis <gnychis@gmail.com>, to show how to inject packets and control the FPGA behavior.
### inject_80211
### Build inject_80211 on board
Userspace program to inject 802.11 packets through mac80211 supported (softmac) wireless devices.
### Options
```
Login/ssh to the board and setup internet connection according to the Quick Start. Then
```
cd openwifi/inject_80211
make
```
### Customize the packet content
To customize the packet, following piece of the inject_80211.c needs to be changed:
```
/* IEEE80211 header */
static const u8 ieee_hdr[] =
{
0x08, 0x01, 0x00, 0x00, // FC 0x0801. 0--subtype; 8--type&version; 01--toDS1 fromDS0 (data packet to DS)
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP
0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Source address (STA)
0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Destination address (another STA under the same AP)
0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number
};
```
Note: The byte/bit order might not be intuitive when comparing with the standard.
### FPGA behavior control
- ACK and retransmission after FPGA sends packet
In openwifi_tx of sdr.c, many FPGA behaviors can be controled. Generally they are controled by the information from upper layer (Linux mac80211), but you can override them in driver (sdr.c)
If 802.11 ACK is expected from the peer after the packet is sent by FPGA, variable **pkt_need_ack** should be overridden to 1. In this case, the FPGA will try to receive ACK, and report the sending status (ACK is received or not) to upper layer (Linux mac80211)
The maximum times of transmission for the packet can be controled by variable **retry_limit_raw**. If no ACK is received after the packet is sent, FPGA will try retransmissions automatically if retry_limit_raw>1.
- ACK after FPGA receives packet in monitor mode
Even in monitor mode, openwifi FPGA still sends ACK after the packet is received, if the conditions are met: MAC address is matched, it is a data frame, etc. To disable this automatic ACK generation, the register 11 of xpu should be set to 16:
```
sdrctl dev sdr0 set reg xpu 11 16
```
### Options of program inject_80211
```
-m/--hw_mode <hardware operation mode> (a,g,n)
-r/--rate_index <rate/MCS index> (0,1,2,3,4,5,6,7)
-i/--sgi_flag (0,1)
@ -21,12 +62,24 @@ Userspace program to inject 802.11 packets through mac80211 supported (softmac)
-s/--payload_size <payload size in bytes>
-d/--delay <delay between packets in usec>
-h this menu
```
```
### Example:
Login/ssh to the board, Then
```
iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up
inject_80211 -m n -r 0 -n 64 -s 100 mon0 # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size
cd openwifi
./wgd.sh
./monitor_ch.sh sdr0 11
(Above will turn sdr0 into the monitor mode and monitor on channel 11)
./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 sdr0
(Above will inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size via NIC sdr0)
```
When above injection command is running, you could see the injected packets with wireshark (or other packet sniffer) on another WiFi device monitoring channel 11.
Or add extra virtual monitor interface on top of sdr0, and inject packets:
```
iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up
./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 mon0 # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size
```
### Link performance test
@ -57,7 +110,7 @@ done
On the receiver side, we can use tcpdump to collect the pcap traces.
```
iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up
iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up
tcpdump -i mon0 -w trace.pcap 'wlan addr1 ff:ff:ff:ff:ff:ff and wlan addr2 66:55:44:33:22:11'
```

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
We implement the **IQ sample capture** with interesting extensions: many **trigger conditions**; **RSSI**, RF chip **AGC** **status (lock/unlock)** and **gain**.
## Quick start
@ -34,8 +41,9 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg
(for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095)
```
The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see 3 figures showing run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**.
![](./iq-screen-shot.jpg)
While running, all informations are also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095.
While running, all information is also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095.
## Understand the IQ capture feature
The IQ information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.
@ -104,6 +112,12 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg
30|start tx, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th
31|start tx and need for ACK, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th
If free running is wanted (alway trigger), please use the following two commands together.
```
./side_ch_ctl wh8d0
./side_ch_ctl wh5d1
```
To set the RSSI threshold
```
./side_ch_ctl wh9dY
@ -123,7 +137,7 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg
The interval will become N*1ms
## Config the iq_len
The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independant from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m.
The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independent from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m.
- When insert the kernel module, use:
```
insmod side_ch.ko iq_len_init=3000

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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@ -1,9 +1,22 @@
Instead of [**normal IQ sample capture**](iq.md), this app note introduce how to enable the I/Q capture for dual antenna. In this dual antenna mode, the RSSI and AGC status won't be captured as in the normal mode. Instead, they are replaced by the I/Q samples from the other antenna. But you are suggested to read the [**normal IQ sample capture**](iq.md) to understand how do we use the side channel to capture I/Q sample by different trigger conditions.
<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2019 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
In this app note, we show how to use the dual antenna I/Q capture to capture the collision.
## Quick start
The currently selected antenna (rx0 by default if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1) will be also avaliable for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time.
Instead of [**normal IQ sample capture**](iq.md), this app note introduces how to enable the I/Q capture for dual antennas. Besides the I/Q from the main antenna (that is selected by baseband), the I/Q samples from the other antenna (monitoring antenna) is captured as well (coherently synchronized) in this dual antenna mode. You are suggested to read the [**normal IQ sample capture**](iq.md) to understand how we use the side channel to capture I/Q samples by different trigger conditions.
This feature also support capturing TX I/Q (loopback) to test the baseband transmitter.
- [[Quick start for collision capture](#Quick-start-for-collision-capture)]
- [[Quick start for TX IQ capture in trigger mode](#Quick-start-for-TX-IQ-capture-in-trigger-mode)]
- [[Quick start for TX IQ capture in free running mode](#Quick-start-for-TX-IQ-capture-in-free-running-mode)]
## Quick start for collision capture
![](./iq_2ant-setup.png)
The main antenna rx0 (by default selected by baseband if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1 -- monitoring antenna) will be also available for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time.
The collision capture steps:
- Change rx1 AGC to manual mode instead of fast_attack in rf_init.sh by:
@ -40,7 +53,10 @@ In this app note, we show how to use the dual antenna I/Q capture to capture the
python3 iq_capture_2ant.py
(if smaller FPGA, like z7020, is used, add a argument that equals to iq_len_init, like 4095)
```
Above script will plot the real-time rx0 and rx1 I/Q captured each time trigger condition met. Meanwhile the script also prints the maximum amplitutde of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicate a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets).
Above script will plot the real-time rx0 and rx1 I/Q captured each time the trigger condition is met. .
![](./iq_2ant-screen-shot.jpg)
In the above example, the upper half shows the signal received from the main antenna (self tx is not seen because of self muting in FPGA), the lower half shows not only the rx signal from the monitoring antenna but also the tx signal from the main antenna due to coupling.
Meanwhile the script also prints the maximum amplitude of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicates a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets).
- Set trigger condition to 29, which means that rx1 I/Q is found larger than a threshold while SDR is transmitting -- this means a collision condition is captured because rx1 I/Q implies the transmitting from the peer WiFi node. The threshold value is decided in the previous step (2500 is assumed here).
```
(Quit side_ch_ctl by Ctrl+C)
@ -51,3 +67,50 @@ In this app note, we show how to use the dual antenna I/Q capture to capture the
- Now the trigger condition can capture the case where both sides happen to transmit in an overlapped duration. If the printed "**side info count**" is increasing, it means the collision happens from time to time.
- You can also see it via iq_capture_2ant.py or do offline analysis by test_iq_2ant_file_display.m
- Check the **iq1** signal in FPGA ILA/probe (triggered by signal "iq_trigger") for further debug if you want to know what exactly happened when collision is captured.
## Quick start for TX IQ capture in trigger mode
To capture the TX I/Q (baseband loopback), a scenario where openwifi will do TX needs to be set up. Such as beacon TX when openwifi act as AP, or [packet injection](inject_80211.md).
The example command sequence on board and explanations are as follows.
```
cd openwifi
./fosdem.sh
insmod side_ch.ko iq_len_init=511
(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)
./side_ch_ctl wh11d1
(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)
./side_ch_ctl wh8d16
(trigger condition 16: phy_tx_started signal from openofdm tx core)
./side_ch_ctl wh5h2
(I/Q source selection: 2--openofdm_tx core; 4--tx_intf)
./side_ch_ctl wh3h11
./side_ch_ctl g1
```
On computer:
```
openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511
```
## Quick start for TX IQ capture in free running mode
```
cd openwifi
./fosdem.sh
insmod side_ch.ko iq_len_init=511
(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)
./side_ch_ctl wh11d1
(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)
./side_ch_ctl wh8d0
(trigger condition 0 is needed for free running mode)
./side_ch_ctl wh5h3
(I/Q source selection: 3--openofdm_tx core; 5--tx_intf)
./side_ch_ctl wh3h11
./side_ch_ctl g1
```
On computer:
```
openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511
```

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# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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@ -0,0 +1,5 @@
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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Hello,
The skywater PDK and free MPW shuttle are interesting. And indeed we are asked many times to consider sky130 or other ASIC process MPW.
We do agree that building a real openwifi chip will probably (or not) mean a lot for the community, user and the world.
But, due to our limited bandwidth, currently we are focusing on making the openwifi IP more stable/mature/as-good-as COTS WiFi chip by using the FPGA verification platform, so we haven’t found time to take a look at a real WiFi chip design yet.
WiFi chips could be as cheap as 0.5USD, but it doesn't mean the WiFi chip is simple. This is contrary to many people’s minds. I tried to explain the complexity of the WiFi chip in some videos, such as the FOSDEM and Libreplanet videos on this page: https://github.com/open-sdr/openwifi/blob/master/doc/videos.md . The WiFi chip is cheap only because they are sold so many per year. From this perspective, the WiFi chip is really an essential tiny thing of the modern world.
But we are definitely glad to support/answer-questions if someone else could jump in and do a solid analysis on the ASIC design effort. Some hints:
1 . The info and communication hub is our github: https://github.com/open-sdr/openwifi . The FPGA code is in https://github.com/open-sdr/openwifi-hw .
2 . The best way to get full picture and further info (resource/power/clock-speed/etc) of the openwifi FPGA design is downloading Xilinx Vivado (version is listed on our github) tool chain, and go through our full FPGA build procedure (README of openwifi-hw: https://github.com/open-sdr/openwifi-hw/blob/master/README.md ), where you will see the full system block diagram: not only the openwifi IP, but also all interfacing/peripheral IP around. Of course many of them are Xilinx/Analog-Devices specific.
3 . You don’t need to pay any fee for Xilinx Vivado, if you chose the FPGA boards (the full list of supported FPGA board is in the README of openwifi: https://github.com/open-sdr/openwifi/blob/master/README.md ) that has 7020 FPGA, because Xilinx offer free offer for that small scale FPGA.
4 . Try to find out all the vendor/3rd-part (Xilinx/Analog-Devices/etc) IPs, and evaluate/estimate how big the efforts will be if they need to be turned into sky130 or other ASIC design. As far as I remember (not full list), inside openwifi IP, we use these IP cores from Xilinx:
- FFT
- Viterbi decoder
- FIFO
- dual port RAM
- ROM
- FIR filter
- AXI stream DMA
- AXI lite bus
- integer divider
- integer multiplexer
- etc.
I guess most of them need to be ported if we go for a real chip.
5 . Also outside openwifi IP, there are interfacing/peripheral IPs from Xilinx/Analog-Devices, which can be seen if you create and open the openwifi project block diagram in Vivado (follow the openwifi-hw README). Two special things: RF and ARM processor interconnection.
- Currently the RF front-end is AD9361 (off-FPGA), which is not a dedicated WiFi front-end (2.4GH/5GHz only). Instead, AD9361 is a quite expensive front-end that supports 70M~6GHz for SDR (Software Defined Radio) applications. So of course, there will be dedicated AD9361 interfacing IPs from Analog Devices (open source as well: https://github.com/analogdevicesinc/hdl, but the license situation is complicated: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE )
- Unlike usual WiFi chips that work with processors via USB/PCIe/SDIO/etc bus, openwifi IP interconnects to the ARM processor via AXI bus. This brings us some unique benefits, such as low latency, but it also makes the IP quite platform dependent.
6 . Last but not least, considering the efforts (seems big) needed for a real openwifi ASIC, we believe that some bigger/stronger organizations (like foundation/company/person), that have rich experience on IP/licensing analysis and ASIC design, could set up an initiative to work on this openwifi chip activity. Of course, we will be more than happy to join and support it. But to be honest, the openwifi team has very limited ASIC design experiences, and we mainly focus on FPGA for now (due to the bandwidth: personal resource, funding, etc.)
Further discussions/ideas? Feel free to reach out to us!
Best regards,
Xianjun

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```
@electronic{openwifigithub,
author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael},
title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design},
url = {https://github.com/open-sdr/openwifi},
year = {2019},
}
```

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```
@inproceedings{jiao2020openwifi,
title={openwifi: a free and open-source IEEE802. 11 SDR implementation on SoC},
author={Jiao, Xianjun and Liu, Wei and Mehari, Michael and Aslam, Muhammad and Moerman, Ingrid},
booktitle={2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring)},
pages={1--2},
year={2020},
organization={IEEE}
}
```

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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<!--
Author: Xianjun jiao
SPDX-FileCopyrightText: 2021 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
If your work uses openwifi, please cite the first VTC2020 openwifi paper: [LaTex example](cite-openwifi-vtc-paper.md)
You can also cite openwifi github code: [LaTex example](cite-openwifi-github-code.md).
Other openwifi related publications:
- [VTC2020 spring Antwerp. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf)
- [ORCA project opencall: CSI MURDER](https://ans.unibs.it/projects/csi-murder/)
- [ELSEVIER Computer Networks, 2021. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X)
- [ICIT2021. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients](https://biblio.ugent.be/publication/8700714/file/8700715.pdf)
- [ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
- [Microwaves&RF, 2021. Wireless Time-Sensitive Networks: When Every Microsecond Counts](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts)
- [CNERT2021. High precision time synchronization on Wi-Fi based multi-hop network](https://biblio.ugent.be/publication/8709058/file/8709060.pdf)
- [Blackhat asia 2021, OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz)
- [UGent master thesis 2021. The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work by Cedric Den Haese](https://users.ugent.be/~xjiao/Cedric_Den_Haese_masterproef.pdf)
- [UGent master thesis 2021. IEEE 802.11 Physical Layer Fuzzing Using OpenWifi by Steven Heijse](https://users.ugent.be/~xjiao/Steven_Heijse_masterproef.pdf)
- [Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf)
- [Arxiv. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications](https://arxiv.org/abs/2109.03032)
- [Wireless Personal Communications (2021). Bringing Time-Sensitive Networking to Wireless Professional Private Networks](https://link.springer.com/article/10.1007/s11277-021-09056-0)
- [MethodsX. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks](https://www.sciencedirect.com/science/article/pii/S2215016121003368)
- [IEEE Transactions on Industrial Informatics. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP](https://ieeexplore.ieee.org/document/9573364)
**Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).**

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

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- The 1st public demo video [[Youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)]
- FOSDEM2020 presentation [[Youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)]
- Low latency for gaming and general introduction [[Youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)]
- CSI (Channel State Information) [[Youtube](https://youtu.be/DanB1ClVamU)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)]
- FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://mirror.as35701.net/video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)]
- FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)]
- Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)]
- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)]
- NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)]
- High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)]

11
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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
ad9361_drv-y := ad9361.o ad9361_conv.o
obj-m += ad9361_drv.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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<!--
Author: Xianjun Jiao
SPDX-FileCopyrightText: 2021 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
We don't maintain our own (modified) ad9361 driver anymore! The original ad9361 driver in the Linux kernel tree can be used with some extra EXPORT_SYMBOL.

21
driver/ad9361/ad9361.c
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@ -2,8 +2,6 @@
* AD9361 Agile RF Transceiver
*
* Copyright 2013-2015 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
* Licensed under the GPL-2.
*/
@ -1631,7 +1629,6 @@ static int ad9361_get_rx_gain(struct ad9361_rf_phy *phy,
out:
return rc;
}
EXPORT_SYMBOL(ad9361_get_rx_gain);
static u8 ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
{
@ -2009,7 +2006,6 @@ out:
return rc;
}
EXPORT_SYMBOL(ad9361_set_rx_gain);
static int ad9361_gc_update(struct ad9361_rf_phy *phy)
{
@ -2177,9 +2173,8 @@ static int ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy,
out:
return rc;
}
EXPORT_SYMBOL(ad9361_set_gain_ctrl_mode);
int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
static int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
{
struct spi_device *spi = phy->spi;
u8 reg_val_buf[6];
@ -2208,7 +2203,6 @@ int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
return rc;
}
EXPORT_SYMBOL(ad9361_read_rssi);
static int ad9361_rx_adc_setup(struct ad9361_rf_phy *phy, unsigned long bbpll_freq,
unsigned long adc_sampl_freq_Hz)
@ -3737,7 +3731,6 @@ int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable
}
EXPORT_SYMBOL(ad9361_ctrl_outs_setup);
//************************************************************
// Setup GPO
//************************************************************
@ -3783,7 +3776,7 @@ static int ad9361_gpo_setup(struct ad9361_rf_phy *phy, struct gpo_control *ctrl)
return 0;
}
int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
static int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
struct rssi_control *ctrl,
bool is_update)
{
@ -3874,7 +3867,6 @@ int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
return 0;
}
EXPORT_SYMBOL(ad9361_rssi_setup);
static int ad9361_bb_clk_change_handler(struct ad9361_rf_phy *phy)
{
@ -4078,12 +4070,6 @@ static int ad9361_validate_trx_clock_chain(struct ad9361_rf_phy *phy,
return -EINVAL;
}
int ad9361_clk_set_rate(struct clk *clk, unsigned long rate) {
clk_set_rate(clk, rate);
return 0;
}
EXPORT_SYMBOL(ad9361_clk_set_rate);
static int ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy,
unsigned long *rx_path_clks,
unsigned long *tx_path_clks)
@ -5226,7 +5212,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
return ret;
}
int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
u32 rf_rx_bw, u32 rf_tx_bw)
{
struct ad9361_rf_phy_state *st = phy->state;
@ -5260,7 +5246,6 @@ int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
return 0;
}
EXPORT_SYMBOL(ad9361_update_rf_bandwidth);
static int ad9361_verify_fir_filter_coef(struct ad9361_rf_phy *phy,
enum fir_dest dest,

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@ -1,255 +0,0 @@
/*
* AD9361
*
* Copyright 2013-2018 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
* Licensed under the GPL-2.
*/
#ifndef IIO_FREQUENCY_AD9361_H_
#define IIO_FREQUENCY_AD9361_H_
#include "ad9361_regs.h"
enum ad9361_clocks {
BB_REFCLK,
RX_REFCLK,
TX_REFCLK,
BBPLL_CLK,
ADC_CLK,
R2_CLK,
R1_CLK,
CLKRF_CLK,
RX_SAMPL_CLK,
DAC_CLK,
T2_CLK,
T1_CLK,
CLKTF_CLK,
TX_SAMPL_CLK,
RX_RFPLL_INT,
TX_RFPLL_INT,
RX_RFPLL_DUMMY,
TX_RFPLL_DUMMY,
RX_RFPLL,
TX_RFPLL,
NUM_AD9361_CLKS,
};
enum debugfs_cmd {
DBGFS_NONE,
DBGFS_INIT,
DBGFS_LOOPBACK,
DBGFS_BIST_PRBS,
DBGFS_BIST_TONE,
DBGFS_BIST_DT_ANALYSIS,
DBGFS_RXGAIN_1,
DBGFS_RXGAIN_2,
DBGFS_MCS,
DBGFS_CAL_SW_CTRL,
DBGFS_DIGITAL_TUNE,
DBGFS_GPO_SET,
};
enum dig_tune_flags {
BE_VERBOSE = 1,
BE_MOREVERBOSE = 2,
DO_IDELAY = 4,
DO_ODELAY = 8,
SKIP_STORE_RESULT = 16,
RESTORE_DEFAULT = 32,
};
enum ad9361_bist_mode {
BIST_DISABLE,
BIST_INJ_TX,
BIST_INJ_RX,
};
enum {
ID_AD9361,
ID_AD9364,
ID_AD9361_2,
ID_AD9363A,
};
enum rx_port_sel {
RX_A_BALANCED, /* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
RX_B_BALANCED, /* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced */
RX_C_BALANCED, /* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced */
RX_A_N, /* 3 = RX1A_N and RX2A_N enabled; unbalanced */
RX_A_P, /* 4 = RX1A_P and RX2A_P enabled; unbalanced */
RX_B_N, /* 5 = RX1B_N and RX2B_N enabled; unbalanced */
RX_B_P, /* 6 = RX1B_P and RX2B_P enabled; unbalanced */
RX_C_N, /* 7 = RX1C_N and RX2C_N enabled; unbalanced */
RX_C_P, /* 8 = RX1C_P and RX2C_P enabled; unbalanced */
TX_MON1, /* 9 = TX_MON1 enabled */
TX_MON2, /* 10 = TX_MON2 enabled */
TX_MON1_2, /* 11 = TX_MON1 & TX_MON2 enabled */
};
enum tx_port_sel {
TX_A,
TX_B,
};
enum digital_tune_skip_mode {
TUNE_RX_TX,
SKIP_TX,
SKIP_ALL,
};
enum rssi_restart_mode {
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
EN_AGC_PIN_IS_PULLED_HIGH,
ENTERS_RX_MODE,
GAIN_CHANGE_OCCURS,
SPI_WRITE_TO_REGISTER,
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
};
struct ctrl_outs_control {
u8 index;
u8 en_mask;
};
struct rssi_control {
enum rssi_restart_mode restart_mode;
bool rssi_unit_is_rx_samples; /* default unit is time */
u32 rssi_delay;
u32 rssi_wait;
u32 rssi_duration;
};
struct rf_rssi {
u32 ant; /* Antenna number for which RSSI is reported */
u32 symbol; /* Runtime RSSI */
u32 preamble; /* Initial RSSI */
s32 multiplier; /* Multiplier to convert reported RSSI */
u8 duration; /* Duration to be considered for measuring */
};
struct ad9361_rf_phy;
struct ad9361_debugfs_entry {
struct ad9361_rf_phy *phy;
const char *propname;
void *out_value;
u32 val;
u8 size;
u8 cmd;
};
struct ad9361_dig_tune_data {
u32 bist_loopback_mode;
u32 bist_config;
u32 ensm_state;
u8 skip_mode;
};
struct refclk_scale {
struct clk_hw hw;
struct spi_device *spi;
struct ad9361_rf_phy *phy;
unsigned long rate;
u32 mult;
u32 div;
enum ad9361_clocks source;
};
struct ad9361_rf_phy_state;
struct ad9361_ext_band_ctl;
struct ad9361_rf_phy {
struct spi_device *spi;
struct clk *clk_refin;
struct clk *clk_ext_lo_rx;
struct clk *clk_ext_lo_tx;
struct clk *clks[NUM_AD9361_CLKS];
struct notifier_block clk_nb_tx;
struct notifier_block clk_nb_rx;
struct refclk_scale clk_priv[NUM_AD9361_CLKS];
struct clk_onecell_data clk_data;
struct ad9361_phy_platform_data *pdata;
struct ad9361_debugfs_entry debugfs_entry[182];
struct bin_attribute bin;
struct bin_attribute bin_gt;
struct iio_dev *indio_dev;
struct work_struct work;
struct completion complete;
struct gain_table_info *gt_info;
char *bin_attr_buf;
u32 ad9361_debugfs_entry_index;
struct ad9361_ext_band_ctl *ext_band_ctl;
struct ad9361_rf_phy_state *state;
};
int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);
int ad9361_clk_set_rate(struct clk *clk, unsigned long rate);
int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
struct rssi_control *ctrl,
bool is_update);
int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,u32 rf_rx_bw, u32 rf_tx_bw);
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen);
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi);
int ad9361_spi_read(struct spi_device *spi, u32 reg);
int ad9361_spi_write(struct spi_device *spi, u32 reg, u32 val);
int ad9361_bist_loopback(struct ad9361_rf_phy *phy, unsigned mode);
int ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
int ad9361_find_opt(u8 *field, u32 size, u32 *ret_start);
int ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy);
int ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy);
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, u8 ensm_state);
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, u8 ensm_state);
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy);
int ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy,
unsigned long freq);
int ad9361_set_trx_clock_chain_default(struct ad9361_rf_phy *phy);
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags);
int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state);
int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);
int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed);
int ad9361_write_bist_reg(struct ad9361_rf_phy *phy, u32 val);
bool ad9361_uses_rx2tx2(struct ad9361_rf_phy *phy);
int ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy,
struct ad9361_dig_tune_data *data);
int ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy);
int ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy);
bool ad9361_uses_lvds_mode(struct ad9361_rf_phy *phy);
int ad9361_set_rx_port(struct ad9361_rf_phy *phy, enum rx_port_sel sel);
int ad9361_set_tx_port(struct ad9361_rf_phy *phy, enum tx_port_sel sel);
#ifdef CONFIG_AD9361_EXT_BAND_CONTROL
int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy);
int ad9361_adjust_rx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
int ad9361_adjust_tx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
void ad9361_unregister_ext_band_control(struct ad9361_rf_phy *phy);
#else
static inline int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy)
{
return 0;
}
static inline int ad9361_adjust_rx_ext_band_settings(
struct ad9361_rf_phy *phy, u64 freq)
{
return 0;
}
static inline int ad9361_adjust_tx_ext_band_settings(
struct ad9361_rf_phy *phy, u64 freq)
{
return 0;
}
static inline void ad9361_unregister_ext_band_control(
struct ad9361_rf_phy *phy)
{}
#endif
#endif

821
driver/ad9361/ad9361_conv.c
View File

@ -1,821 +0,0 @@
/*
* AD9361 Agile RF Transceiver
*
* Copyright 2013-2017 Analog Devices Inc.
*
* Licensed under the GPL-2.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include "ad9361.h"
#if IS_ENABLED(CONFIG_CF_AXI_ADC)
#include "cf_axi_adc.h"
static void ad9361_set_intf_delay(struct ad9361_rf_phy *phy, bool tx,
unsigned int clock_delay,
unsigned int data_delay, bool clock_changed)
{
if (clock_changed)
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_spi_write(phy->spi,
REG_RX_CLOCK_DATA_DELAY + (tx ? 1 : 0),
RX_DATA_DELAY(data_delay) |
DATA_CLK_DELAY(clock_delay));
if (clock_changed)
ad9361_ensm_force_state(phy, ENSM_STATE_FDD);
}
static unsigned int ad9361_num_phy_chan(struct axiadc_converter *conv)
{
if (conv->chip_info->num_channels > 4)
return 4;
return conv->chip_info->num_channels;
}
static int ad9361_check_pn(struct axiadc_converter *conv, bool tx,
unsigned int delay)
{
struct axiadc_state *st = iio_priv(conv->indio_dev);
unsigned int num_chan = ad9361_num_phy_chan(conv);
unsigned int chan;
for (chan = 0; chan < num_chan; chan++)
axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
ADI_PN_ERR | ADI_PN_OOS);
mdelay(delay);
if (!tx && !(axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS))
return 1;
for (chan = 0; chan < num_chan; chan++) {
if (axiadc_read(st, ADI_REG_CHAN_STATUS(chan)))
return 1;
}
return 0;
}
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct ad9361_dig_tune_data data;
int i, j, len = 0;
int ret;
u8 field[16][16];
u8 rx;
if (!conv)
return -ENODEV;
ret = ad9361_get_dig_tune_data(phy, &data);
if (ret < 0)
return ret;
dev_dbg(&phy->spi->dev, "%s:\n", __func__);
rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
/* Mute TX, we don't want to transmit the PRBS */
ad9361_tx_mute(phy, 1);
ad9361_ensm_mode_disable_pinctrl(phy);
ad9361_bist_loopback(phy, 0);
ad9361_bist_prbs(phy, BIST_INJ_RX);
for (i = 0; i < 16; i++) {
for (j = 0; j < 16; j++) {
ad9361_set_intf_delay(phy, false, i, j, j == 0);
field[j][i] = ad9361_check_pn(conv, false, 1);
}
}
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx);
ad9361_bist_loopback(phy, data.bist_loopback_mode);
ad9361_write_bist_reg(phy, data.bist_config);
ad9361_ensm_mode_restore_pinctrl(phy);
ad9361_ensm_restore_state(phy, data.ensm_state);
ad9361_tx_mute(phy, 0);
len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n",
clk_get_rate(phy->clks[RX_SAMPL_CLK]));
len += snprintf(buf + len, buflen, "DC");
for (i = 0; i < 16; i++)
len += snprintf(buf + len, buflen, "%x:", i);
len += snprintf(buf + len, buflen, "\n");
for (i = 0; i < 16; i++) {
len += snprintf(buf + len, buflen, "%x:", i);
for (j = 0; j < 16; j++) {
len += snprintf(buf + len, buflen, "%c ",
(field[i][j] ? '.' : 'o'));
}
len += snprintf(buf + len, buflen, "\n");
}
len += snprintf(buf + len, buflen, "\n");
return len;
}
EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
static ssize_t samples_pps_read(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan, char *buf)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
struct axiadc_state *st = iio_priv(conv->indio_dev);
u32 config, val, mode;
config = axiadc_read(st, ADI_REG_CONFIG);
if (!(config & ADI_PPS_RECEIVER_ENABLE))
return -ENODEV;
val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS_STATUS);
if (val & ADI_CLOCKS_PER_PPS_STAT_INVAL)
return -ETIMEDOUT;
mode = axiadc_read(st, ADI_REG_CNTRL);
/*
* Counts DATA_CLK cycles therefore needs to be corrected
* for 2rx2tx mode or for LVDS vs. CMOS mode.
*/
val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS);
if (!(mode & ADI_R1_MODE))
val /= 2;
if (!(config & ADI_CMOS_OR_LVDS_N))
val /= 2;
return sprintf(buf, "%u\n", val);
}
/*
* Returns the number of samples during a 1PPS (Pulse Per Second) interval.
*/
static struct iio_chan_spec_ext_info axiadc_ext_info[] = {
{
.name = "samples_pps",
.read = samples_pps_read,
.shared = IIO_SHARED_BY_TYPE,
},
{},
};
#define AIM_CHAN(_chan, _si, _bits, _sign) \
{ .type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS) | \
BIT(IIO_CHAN_INFO_CALIBPHASE), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.ext_info = axiadc_ext_info, \
.scan_index = _si, \
.scan_type = { \
.sign = _sign, \
.realbits = _bits, \
.storagebits = 16, \
.shift = 0, \
}, \
}
#define AIM_MC_CHAN(_chan, _si, _bits, _sign) \
{ .type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _chan, \
.scan_index = _si, \
.scan_type = { \
.sign = _sign, \
.realbits = _bits, \
.storagebits = 16, \
.shift = 0, \
}, \
}
static const unsigned long ad9361_2x2_available_scan_masks[] = {
0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, /* 1 & 2 chan */
0x10, 0x20, 0x40, 0x80, 0x30, 0xC0, /* 1 & 2 chan */
0x33, 0xCC, 0xC3, 0x3C, 0x0F, 0xF0, /* 4 chan */
0xFF, /* 8 chan */
0x00,
};
static const unsigned long ad9361_available_scan_masks[] = {
0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, 0x0F,
0x00,
};
static const struct axiadc_chip_info axiadc_chip_info_tbl[] = {
[ID_AD9361] = {
.name = "AD9361",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 4,
.scan_masks = ad9361_available_scan_masks,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
},
[ID_AD9361_2] = { /* MCS/MIMO 2x AD9361 */
.name = "AD9361-2",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 8,
.num_shadow_slave_channels = 4,
.scan_masks = ad9361_2x2_available_scan_masks,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
.channel[4] = AIM_MC_CHAN(4, 4, 12, 'S'),
.channel[5] = AIM_MC_CHAN(5, 5, 12, 'S'),
.channel[6] = AIM_MC_CHAN(6, 6, 12, 'S'),
.channel[7] = AIM_MC_CHAN(7, 7, 12, 'S'),
},
[ID_AD9364] = {
.name = "AD9364",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 2,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
},
};
static int ad9361_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
switch (m) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (!conv->clk)
return -ENODEV;
*val = conv->adc_clk = clk_get_rate(conv->clk);
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad9361_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
unsigned long r_clk;
int ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (!conv->clk)
return -ENODEV;
if (chan->extend_name)
return -ENODEV;
r_clk = clk_round_rate(conv->clk, val);
if (r_clk < 0 || r_clk > conv->chip_info->max_rate) {
dev_warn(&conv->spi->dev,
"Error setting ADC sample rate %ld", r_clk);
return -EINVAL;
}
ret = clk_set_rate(conv->clk, r_clk);
if (ret < 0)
return ret;
return 0;
break;
default:
return -EINVAL;
}
return 0;
}
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st;
unsigned reg, addr, chan, version;
if (!conv)
return -ENODEV;
st = iio_priv(conv->indio_dev);
version = axiadc_read(st, 0x4000);
/* Still there but implemented a bit different */
if (ADI_AXI_PCORE_VER_MAJOR(version) > 7)
addr = 0x4418;
else
addr = 0x4414;
for (chan = 0; chan < conv->chip_info->num_channels; chan++) {
reg = axiadc_read(st, addr + (chan) * 0x40);
if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) {
if (enable) {
if (reg != 0x8) {
conv->scratch_reg[chan] = reg;
reg = 0x8;
}
} else if (reg == 0x8) {
reg = conv->scratch_reg[chan];
}
} else {
/* DAC_LB_ENB If set enables loopback of receive data */
if (enable)
reg |= BIT(1);
else
reg &= ~BIT(1);
}
axiadc_write(st, addr + (chan) * 0x40, reg);
}
return 0;
}
EXPORT_SYMBOL(ad9361_hdl_loopback);
static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane,
unsigned val, bool tx)
{
if (tx) {
if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8)
axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val);
else
return -ENODEV;
} else {
axiadc_idelay_set(st, lane, val);
}
return 0;
}
static int ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int ret = 0, i;
for (i = 0; i < 7; i++)
ret |= ad9361_iodelay_set(st, i, 15, tx);
return 0;
}
static int ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int i, j;
u32 s0, c0;
u8 field[32];
for (i = 0; i < 7; i++) {
for (j = 0; j < 32; j++) {
ad9361_iodelay_set(st, i, j, tx);
mdelay(1);
field[j] = ad9361_check_pn(conv, tx, 10);
}
c0 = ad9361_find_opt(&field[0], 32, &s0);
ad9361_iodelay_set(st, i, s0 + c0 / 2, tx);
dev_info(&phy->spi->dev,
"%s Lane %d, window cnt %d , start %d, IODELAY set to %d\n",
tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2);
}
return 0;
}
static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy,
u8 field[][16], bool tx,
int sel_clk, int sel_data)
{
int i, j;
char c;
pr_info("SAMPL CLK: %lu tuning: %s\n",
clk_get_rate(phy->clks[RX_SAMPL_CLK]), tx ? "TX" : "RX");
pr_info(" ");
for (i = 0; i < 16; i++)
pr_cont("%x:", i);
pr_cont("\n");
for (i = 0; i < 2; i++) {
pr_info("%x:", i);
for (j = 0; j < 16; j++) {
if (field[i][j])
c = '#';
else if ((i == 0 && j == sel_data) ||
(i == 1 && j == sel_clk))
c = 'O';
else
c = 'o';
pr_cont("%c ", c);
}
pr_cont("\n");
}
}
static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
unsigned long max_freq,
enum dig_tune_flags flags, bool tx)
{
//static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; //some low end FPGA, such as z7020, lvds ADC interface seems not stable enough to support 61.44Msps
static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
unsigned int s0, s1, c0, c1;
unsigned int i, j, r;
bool half_data_rate;
u8 field[2][16];
if (ad9361_uses_lvds_mode(phy) || !ad9361_uses_rx2tx2(phy))
half_data_rate = false;
else
half_data_rate = true;
memset(field, 0, 32);
for (r = 0; r < (max_freq ? ARRAY_SIZE(rates) : 1); r++) {
if (max_freq)
ad9361_set_trx_clock_chain_freq(phy,
half_data_rate ? rates[r] / 2 : rates[r]);
for (i = 0; i < 2; i++) {
for (j = 0; j < 16; j++) {
/*
* i == 0: clock delay = 0, data delay from 0 to 15
* i == 1: clock delay = 15, data delay from 15 to 0
*/
ad9361_set_intf_delay(phy, tx, i ? 15 : 0,
i ? 15 - j : j, j == 0);
field[i][j] |= ad9361_check_pn(conv, tx, 4);
}
}
if ((flags & BE_MOREVERBOSE) && max_freq) {
ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
}
}
c0 = ad9361_find_opt(&field[0][0], 16, &s0);
c1 = ad9361_find_opt(&field[1][0], 16, &s1);
if (!c0 && !c1) {
ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__,
tx ? "TX" : "RX");
return -EIO;
} else if (flags & BE_VERBOSE) {
ad9361_dig_tune_verbose_print(phy, field, tx,
c1 > c0 ? (s1 + c1 / 2) : -1,
c1 > c0 ? -1 : (s0 + c0 / 2));
}
if (c1 > c0)
ad9361_set_intf_delay(phy, tx, s1 + c1 / 2, 0, true);
else
ad9361_set_intf_delay(phy, tx, 0, s0 + c0 / 2, true);
return 0;
}
static int ad9361_dig_tune_rx(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int ret;
ad9361_bist_loopback(phy, 0);
ad9361_bist_prbs(phy, BIST_INJ_RX);
ret = ad9361_dig_tune_delay(phy, max_freq, flags, false);
if (flags & DO_IDELAY)
ad9361_dig_tune_iodelay(phy, false);
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
return ret;
}
static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
u32 saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4];
unsigned int chan, num_chan;
unsigned int hdl_dac_version;
u32 tmp, saved = 0;
int ret;
num_chan = ad9361_num_phy_chan(conv);
hdl_dac_version = axiadc_read(st, 0x4000);
ad9361_bist_prbs(phy, BIST_DISABLE);
ad9361_bist_loopback(phy, 1);
axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
for (chan = 0; chan < num_chan; chan++) {
saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan));
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
ADI_ENABLE | ADI_IQCOR_ENB);
axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM);
saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40);
if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40);
axiadc_write(st, 0x4418 + (chan) * 0x40, 9);
axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */
axiadc_write(st, 0x4044, 1);
} else {
axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */
}
}
if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) {
saved = tmp = axiadc_read(st, 0x4048);
tmp &= ~0xF;
tmp |= 1;
axiadc_write(st, 0x4048, tmp);
}
ret = ad9361_dig_tune_delay(phy, max_freq, flags, true);
if (flags & DO_ODELAY)
ad9361_dig_tune_iodelay(phy, true);
if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8)
axiadc_write(st, 0x4048, saved);
for (chan = 0; chan < num_chan; chan++) {
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
saved_chan_ctrl0[chan]);
axiadc_set_pnsel(st, chan, ADC_PN9);
if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
axiadc_write(st, 0x4418 + chan * 0x40,
saved_dsel[chan]);
axiadc_write(st, 0x4044, 1);
}
axiadc_write(st, 0x4414 + chan * 0x40, saved_chan_ctrl6[chan]);
}
return ret;
}
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct ad9361_dig_tune_data data;
struct axiadc_state *st;
bool restore = false;
int ret = 0;
if (!conv)
return -ENODEV;
ret = ad9361_get_dig_tune_data(phy, &data);
if (ret < 0)
return ret;
dev_dbg(&phy->spi->dev, "%s: freq %lu flags 0x%X\n", __func__,
max_freq, flags);
st = iio_priv(conv->indio_dev);
if ((data.skip_mode == SKIP_ALL) ||
(flags & RESTORE_DEFAULT)) {
/* skip completely and use defaults */
restore = true;
} else {
/* Mute TX, we don't want to transmit the PRBS */
ad9361_tx_mute(phy, 1);
ad9361_ensm_mode_disable_pinctrl(phy);
if (flags & DO_IDELAY)
ad9361_midscale_iodelay(phy, false);
if (flags & DO_ODELAY)
ad9361_midscale_iodelay(phy, true);
ret = ad9361_dig_tune_rx(phy, max_freq, flags);
if (ret == 0 && (data.skip_mode == TUNE_RX_TX))
ret = ad9361_dig_tune_tx(phy, max_freq, flags);
ad9361_bist_loopback(phy, data.bist_loopback_mode);
ad9361_write_bist_reg(phy, data.bist_config);
if (ret == -EIO)
restore = true;
if (!max_freq)
ret = 0;
}
if (restore) {
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_write_clock_data_delays(phy);
} else if (!(flags & SKIP_STORE_RESULT)) {
ad9361_read_clock_data_delays(phy);
}
ad9361_ensm_mode_restore_pinctrl(phy);
ad9361_ensm_restore_state(phy, data.ensm_state);
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
ad9361_tx_mute(phy, 0);
return ret;
}
EXPORT_SYMBOL(ad9361_dig_tune);
static int ad9361_post_setup(struct iio_dev *indio_dev)
{
struct axiadc_state *st = iio_priv(indio_dev);
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
struct ad9361_rf_phy *phy = conv->phy;
bool rx2tx2 = ad9361_uses_rx2tx2(phy);
unsigned tmp, num_chan, flags;
int i, ret;
num_chan = ad9361_num_phy_chan(conv);
conv->indio_dev = indio_dev;
axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);
tmp = axiadc_read(st, 0x4048);
if (!rx2tx2) {
axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */
axiadc_write(st, 0x404c,
ad9361_uses_lvds_mode(phy) ? 1 : 0); /* RATE */
} else {
tmp &= ~BIT(5);
axiadc_write(st, 0x4048, tmp);
axiadc_write(st, 0x404c,
ad9361_uses_lvds_mode(phy) ? 3 : 1); /* RATE */
}
for (i = 0; i < num_chan; i++) {
axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),
ADI_DCFILT_OFFSET(0));
axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),
(i & 1) ? 0x00004000 : 0x40000000);
axiadc_write(st, ADI_REG_CHAN_CNTRL(i),
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
ADI_ENABLE | ADI_IQCOR_ENB);
}
flags = 0;
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
0 : 61440000, flags);
if (ret < 0)
goto error;
if (flags & (DO_IDELAY | DO_ODELAY)) {
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
0 : 61440000, flags & BE_VERBOSE);
if (ret < 0)
goto error;
}
ret = ad9361_set_trx_clock_chain_default(phy);
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_ensm_restore_prev_state(phy);
return 0;
error:
spi_set_drvdata(phy->spi, NULL);
return ret;
}
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
{
struct axiadc_converter *conv;
struct spi_device *spi = phy->spi;
int ret;
conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL);
if (conv == NULL)
return -ENOMEM;
conv->id = ad9361_spi_read(spi, REG_PRODUCT_ID) & PRODUCT_ID_MASK;
if (conv->id != PRODUCT_ID_9361) {
dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", conv->id);
ret = -ENODEV;
goto out;
}
conv->chip_info = &axiadc_chip_info_tbl[
(spi_get_device_id(spi)->driver_data == ID_AD9361_2) ?
ID_AD9361_2 : ad9361_uses_rx2tx2(phy) ? ID_AD9361 : ID_AD9364];
conv->write_raw = ad9361_write_raw;
conv->read_raw = ad9361_read_raw;
conv->post_setup = ad9361_post_setup;
conv->spi = spi;
conv->phy = phy;
conv->clk = phy->clks[RX_SAMPL_CLK];
conv->adc_clk = clk_get_rate(conv->clk);
spi_set_drvdata(spi, conv); /* Take care here */
return 0;
out:
spi_set_drvdata(spi, NULL);
return ret;
}
EXPORT_SYMBOL(ad9361_register_axi_converter);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
{
struct axiadc_converter *conv = spi_get_drvdata(spi);
return conv->phy;
}
EXPORT_SYMBOL(ad9361_spi_to_phy);
#else /* CONFIG_CF_AXI_ADC */
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
return -ENODEV;
}
EXPORT_SYMBOL(ad9361_dig_tune);
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen)
{
return 0;
}
EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
{
return -ENODEV;
}
EXPORT_SYMBOL(ad9361_hdl_loopback);
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
{
struct spi_device *spi = phy->spi;
spi_set_drvdata(spi, phy); /* Take care here */
return 0;
}
EXPORT_SYMBOL(ad9361_register_axi_converter);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
{
return spi_get_drvdata(spi);
}
EXPORT_SYMBOL(ad9361_spi_to_phy);
#endif /* CONFIG_CF_AXI_ADC */

507
driver/ad9361/ad9361_private.h
View File

@ -1,507 +0,0 @@
/*
* AD9361 - Private definitions to be used only in the ad9361.c file
*
* Copyright 2013-2018 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
* Licensed under the GPL-2.
*/
#ifndef IIO_AD9361_PRIVATE_H_
#define IIO_AD9361_PRIVATE_H_
#ifndef IIO_AD9361_USE_PRIVATE_H_
#error "Please do not include ad9361_private.h; use ad9361.h instead"
#endif
#include "ad9361.h"
/*
* Driver
*/
enum rx_gain_table_type {
RXGAIN_FULL_TBL,
RXGAIN_SPLIT_TBL,
};
enum rx_gain_table_name {
TBL_200_1300_MHZ,
TBL_1300_4000_MHZ,
TBL_4000_6000_MHZ,
RXGAIN_TBLS_END,
};
enum fir_dest {
FIR_TX1 = 0x01,
FIR_TX2 = 0x02,
FIR_TX1_TX2 = 0x03,
FIR_RX1 = 0x81,
FIR_RX2 = 0x82,
FIR_RX1_RX2 = 0x83,
FIR_IS_RX = 0x80,
};
struct rf_gain_ctrl {
u32 ant;
u8 mode;
};
enum rf_gain_ctrl_mode {
RF_GAIN_MGC,
RF_GAIN_FASTATTACK_AGC,
RF_GAIN_SLOWATTACK_AGC,
RF_GAIN_HYBRID_AGC
};
enum f_agc_target_gain_index_type {
MAX_GAIN,
SET_GAIN,
OPTIMIZED_GAIN,
NO_GAIN_CHANGE,
};
struct gain_control {
enum rf_gain_ctrl_mode rx1_mode;
enum rf_gain_ctrl_mode rx2_mode;
/* Common */
u8 adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */
u8 adc_small_overload_thresh; /* 0..255, 0x105 */
u8 adc_large_overload_thresh; /* 0..255, 0x104 */
u16 lmt_overload_high_thresh; /* 16..800 mV, 0x107 */
u16 lmt_overload_low_thresh; /* 16..800 mV, 0x108 */
u16 dec_pow_measuremnt_duration; /* Samples, 0x15C */
u8 low_power_thresh; /* -64..0 dBFS, 0x114 */
bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */
bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */
u8 max_dig_gain; /* 0..31 */
/* MGC */
bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */
bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */
u8 mgc_inc_gain_step; /* 1..8 */
u8 mgc_dec_gain_step; /* 1..8 */
u8 mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */
/* AGC */
u8 agc_attack_delay_extra_margin_us; /* 0..31 us */
u8 agc_outer_thresh_high;
u8 agc_outer_thresh_high_dec_steps;
u8 agc_inner_thresh_high;
u8 agc_inner_thresh_high_dec_steps;
u8 agc_inner_thresh_low;
u8 agc_inner_thresh_low_inc_steps;
u8 agc_outer_thresh_low;
u8 agc_outer_thresh_low_inc_steps;
u8 adc_small_overload_exceed_counter; /* 0..15, 0x122 */
u8 adc_large_overload_exceed_counter; /* 0..15, 0x122 */
u8 adc_large_overload_inc_steps; /* 0..15, 0x106 */
bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */
u8 lmt_overload_large_exceed_counter; /* 0..15, 0x121 */
u8 lmt_overload_small_exceed_counter; /* 0..15, 0x121 */
u8 lmt_overload_large_inc_steps; /* 0..7, 0x121 */
u8 dig_saturation_exceed_counter; /* 0..15, 0x128 */
u8 dig_gain_step_size; /* 1..8, 0x100 */
bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */
u32 gain_update_interval_us; /* in us */
bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */
bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */
/*
* Fast AGC
*/
u32 f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */
u32 f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */
/* Fast AGC - Low Power */
bool f_agc_allow_agc_gain_increase; /* 0x110:1 */
u8 f_agc_lp_thresh_increment_time; /* 0x11B RX samples */
u8 f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
/* Fast AGC - Lock Level */
u8 f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */
u8 f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */
/* Fast AGC - Peak Detectors and Final Settling */
u8 f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/
u8 f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/
u8 f_agc_final_overrange_count; /* 0x116:5 0..7 */
/* Fast AGC - Final Power Test */
bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */
/* Fast AGC - Unlocking the Gain */
/* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */
bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */
u8 f_agc_optimized_gain_offset; /*0x116 0..15 steps */
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */
u8 f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */
u8 f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */
u8 f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */
bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */
bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */
bool f_agc_rst_gla_en_agc_pulled_high_en;
/* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */
u8 f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/
u8 f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */
};
struct auxdac_control {
u16 dac1_default_value;
u16 dac2_default_value;
bool auxdac_manual_mode_en;
bool dac1_in_rx_en;
bool dac1_in_tx_en;
bool dac1_in_alert_en;
bool dac2_in_rx_en;
bool dac2_in_tx_en;
bool dac2_in_alert_en;
u8 dac1_rx_delay_us;
u8 dac1_tx_delay_us;
u8 dac2_rx_delay_us;
u8 dac2_tx_delay_us;
};
#if 0
enum rssi_restart_mode {
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
EN_AGC_PIN_IS_PULLED_HIGH,
ENTERS_RX_MODE,
GAIN_CHANGE_OCCURS,
SPI_WRITE_TO_REGISTER,
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
};
struct rssi_control {
enum rssi_restart_mode restart_mode;
bool rssi_unit_is_rx_samples; /* default unit is time */
u32 rssi_delay;
u32 rssi_wait;
u32 rssi_duration;
};
#endif
struct rx_gain_info {
enum rx_gain_table_type tbl_type;
int starting_gain_db;
int max_gain_db;
int gain_step_db;
int max_idx;
int idx_step_offset;
};
struct port_control {
u8 pp_conf[3];
u8 rx_clk_data_delay;
u8 tx_clk_data_delay;
u8 digital_io_ctrl;
u8 lvds_bias_ctrl;
u8 lvds_invert[2];
};
#if 0
struct ctrl_outs_control {
u8 index;
u8 en_mask;
};
#endif
struct elna_control {
u16 gain_mdB;
u16 bypass_loss_mdB;
u32 settling_delay_ns;
bool elna_1_control_en; /* GPO0 */
bool elna_2_control_en; /* GPO1 */
bool elna_in_gaintable_all_index_en;
};
struct auxadc_control {
s8 offset;
u32 temp_time_inteval_ms;
u32 temp_sensor_decimation;
bool periodic_temp_measuremnt;
u32 auxadc_clock_rate;
u32 auxadc_decimation;
};
struct gpo_control {
u32 gpo_manual_mode_enable_mask;
bool gpo_manual_mode_en;
bool gpo0_inactive_state_high_en;
bool gpo1_inactive_state_high_en;
bool gpo2_inactive_state_high_en;
bool gpo3_inactive_state_high_en;
bool gpo0_slave_rx_en;
bool gpo0_slave_tx_en;
bool gpo1_slave_rx_en;
bool gpo1_slave_tx_en;
bool gpo2_slave_rx_en;
bool gpo2_slave_tx_en;
bool gpo3_slave_rx_en;
bool gpo3_slave_tx_en;
u8 gpo0_rx_delay_us;
u8 gpo0_tx_delay_us;
u8 gpo1_rx_delay_us;
u8 gpo1_tx_delay_us;
u8 gpo2_rx_delay_us;
u8 gpo2_tx_delay_us;
u8 gpo3_rx_delay_us;
u8 gpo3_tx_delay_us;
};
struct tx_monitor_control {
bool tx_mon_track_en;
bool one_shot_mode_en;
u32 low_high_gain_threshold_mdB;
u8 low_gain_dB;
u8 high_gain_dB;
u16 tx_mon_delay;
u16 tx_mon_duration;
u8 tx1_mon_front_end_gain;
u8 tx2_mon_front_end_gain;
u8 tx1_mon_lo_cm;
u8 tx2_mon_lo_cm;
};
enum ad9361_pdata_rx_freq {
BBPLL_FREQ,
ADC_FREQ,
R2_FREQ,
R1_FREQ,
CLKRF_FREQ,
RX_SAMPL_FREQ,
NUM_RX_CLOCKS,
};
enum ad9361_pdata_tx_freq {
IGNORE,
DAC_FREQ,
T2_FREQ,
T1_FREQ,
CLKTF_FREQ,
TX_SAMPL_FREQ,
NUM_TX_CLOCKS,
};
enum ad9361_clkout {
CLKOUT_DISABLE,
BUFFERED_XTALN_DCXO,
ADC_CLK_DIV_2,
ADC_CLK_DIV_3,
ADC_CLK_DIV_4,
ADC_CLK_DIV_8,
ADC_CLK_DIV_16,
};
enum synth_pd_ctrl {
LO_DONTCARE,
LO_OFF,
LO_ON,
};
struct ad9361_phy_platform_data {
bool rx2tx2;
bool fdd;
bool fdd_independent_mode;
bool split_gt;
bool use_extclk;
bool ensm_pin_pulse_mode;
bool ensm_pin_ctrl;
bool debug_mode;
bool tdd_use_dual_synth;
bool tdd_skip_vco_cal;
bool use_ext_rx_lo;
bool use_ext_tx_lo;
bool rx1rx2_phase_inversion_en;
bool qec_tracking_slow_mode_en;
bool dig_interface_tune_fir_disable;
bool lo_powerdown_managed_en;
u8 dc_offset_update_events;
u8 dc_offset_attenuation_high;
u8 dc_offset_attenuation_low;
u8 rf_dc_offset_count_high;
u8 rf_dc_offset_count_low;
u8 dig_interface_tune_skipmode;
u32 dcxo_coarse;
u32 dcxo_fine;
bool rf_rx_input_sel_lock;
bool rf_tx_output_sel_lock;
u32 rx1tx1_mode_use_rx_num;
u32 rx1tx1_mode_use_tx_num;
unsigned long rx_path_clks[NUM_RX_CLOCKS];
unsigned long tx_path_clks[NUM_TX_CLOCKS];
u32 trx_synth_max_fref;
u64 rx_synth_freq;
u64 tx_synth_freq;
u32 rf_rx_bandwidth_Hz;
u32 rf_tx_bandwidth_Hz;
int tx_atten;
bool update_tx_gain_via_alert;
u32 rx_fastlock_delay_ns;
u32 tx_fastlock_delay_ns;
bool trx_fastlock_pinctrl_en[2];
enum ad9361_clkout ad9361_clkout_mode;
struct gain_control gain_ctrl;
struct rssi_control rssi_ctrl;
u32 rssi_lna_err_tbl[4];
u32 rssi_mixer_err_tbl[16];
u32 rssi_gain_step_calib_reg_val[5];
bool rssi_skip_calib;
struct port_control port_ctrl;
struct ctrl_outs_control ctrl_outs_ctrl;
struct elna_control elna_ctrl;
struct auxadc_control auxadc_ctrl;
struct auxdac_control auxdac_ctrl;
struct gpo_control gpo_ctrl;
struct tx_monitor_control txmon_ctrl;
struct gpio_desc *reset_gpio;
/* MCS SYNC */
struct gpio_desc *sync_gpio;
struct gpio_desc *cal_sw1_gpio;
struct gpio_desc *cal_sw2_gpio;
};
struct rf_rx_gain {
u32 ant; /* Antenna number to read gain */
s32 gain_db; /* gain value in dB */
u32 fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */
u32 lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/
u32 lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/
u32 digital_gain; /* Digital gain in dB / index */
/* Debug only */
u32 lna_index; /* LNA Index (Split GT mode only) */
u32 tia_index; /* TIA Index (Split GT mode only) */
u32 mixer_index; /* MIXER Index (Split GT mode only) */
};
#if 0
struct rf_rssi {
u32 ant; /* Antenna number for which RSSI is reported */
u32 symbol; /* Runtime RSSI */
u32 preamble; /* Initial RSSI */
s32 multiplier; /* Multiplier to convert reported RSSI */
u8 duration; /* Duration to be considered for measuring */
};
#endif
struct SynthLUT {
u16 VCO_MHz;
u8 VCO_Output_Level;
u8 VCO_Varactor;
u8 VCO_Bias_Ref;
u8 VCO_Bias_Tcf;
u8 VCO_Cal_Offset;
u8 VCO_Varactor_Reference;
u8 Charge_Pump_Current;
u8 LF_C2;
u8 LF_C1;
u8 LF_R1;
u8 LF_C3;
u8 LF_R3;
};
#define SYNTH_LUT_SIZE 53
enum {
LUT_FTDD_40,
LUT_FTDD_60,
LUT_FTDD_80,
LUT_FTDD_ENT,
};
struct ad9361_fastlock_entry {
#define FASTLOOK_INIT 1
u8 flags;
u8 alc_orig;
u8 alc_written;
};
struct ad9361_fastlock {
u8 save_profile;
u8 current_profile[2];
struct ad9361_fastlock_entry entry[2][8];
};
struct ad9361_rf_phy_state {
u8 prev_ensm_state;
u8 curr_ensm_state;
u8 cached_rx_rfpll_div;
u8 cached_tx_rfpll_div;
u8 cached_synth_pd[2];
int tx_quad_lpf_tia_match;
int current_table;
int rx_sampl_freq_avail[3];
int tx_sampl_freq_avail[3];
int rx_gain_avail[3];
bool ensm_pin_ctl_en;
bool auto_cal_en;
bool manual_tx_quad_cal_en;
u64 last_tx_quad_cal_freq;
u32 last_tx_quad_cal_phase;
u64 current_tx_lo_freq;
u64 current_rx_lo_freq;
bool current_tx_use_tdd_table;
bool current_rx_use_tdd_table;
unsigned long current_rx_path_clks[NUM_RX_CLOCKS];
unsigned long current_tx_path_clks[NUM_TX_CLOCKS];
unsigned long flags;
unsigned long cal_threshold_freq;
u32 current_rx_bw_Hz;
u32 current_tx_bw_Hz;
u32 rxbbf_div;
u32 rate_governor;
bool bypass_rx_fir;
bool bypass_tx_fir;
bool rx_eq_2tx;
bool filt_valid;
unsigned long filt_rx_path_clks[NUM_RX_CLOCKS];
unsigned long filt_tx_path_clks[NUM_TX_CLOCKS];
u32 filt_rx_bw_Hz;
u32 filt_tx_bw_Hz;
u8 tx_fir_int;
u8 tx_fir_ntaps;
u8 rx_fir_dec;
u8 rx_fir_ntaps;
u8 agc_mode[2];
bool rfdc_track_en;
bool bbdc_track_en;
bool quad_track_en;
bool txmon_tdd_en;
u16 auxdac1_value;
u16 auxdac2_value;
u32 tx1_atten_cached;
u32 tx2_atten_cached;
u8 bist_loopback_mode;
u8 bist_config;
u32 rf_rx_input_sel;
u32 rf_tx_output_sel;
struct ad9361_fastlock fastlock;
};
#endif

2831
driver/ad9361/ad9361_regs.h
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File diff suppressed because it is too large Load Diff

351
driver/ad9361/cf_axi_adc.h
View File

@ -1,351 +0,0 @@
/*
* ADI-AIM ADI ADC Interface Module
*
* Copyright 2012-2017 Analog Devices Inc.
*
* Licensed under the GPL-2.
*
* http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
*/
#ifndef ADI_AXI_ADC_H_
#define ADI_AXI_ADC_H_
#include <linux/fpga/adi-axi-common.h>
/* ADC COMMON */
#define ADI_REG_CONFIG 0x000C
#define ADI_IQCORRECTION_DISABLE (1 << 0)
#define ADI_DCFILTER_DISABLE (1 << 1)
#define ADI_DATAFORMAT_DISABLE (1 << 2)
#define ADI_USERPORTS_DISABLE (1 << 3)
#define ADI_MODE_1R1T (1 << 4)
#define ADI_SCALECORRECTION_ONLY (1 << 5)
#define ADI_CMOS_OR_LVDS_N (1 << 7)
#define ADI_PPS_RECEIVER_ENABLE (1 << 8)
#define ADI_REG_RSTN 0x0040
#define ADI_RSTN (1 << 0)
#define ADI_MMCM_RSTN (1 << 1)
#define ADI_REG_CNTRL 0x0044
#define ADI_R1_MODE (1 << 2)
#define ADI_DDR_EDGESEL (1 << 1)
#define ADI_PIN_MODE (1 << 0)
#define ADI_REG_CLK_FREQ 0x0054
#define ADI_CLK_FREQ(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_CLK_FREQ(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_CLK_RATIO 0x0058
#define ADI_CLK_RATIO(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_CLK_RATIO(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_STATUS 0x005C
#define ADI_MUX_PN_ERR (1 << 3)
#define ADI_MUX_PN_OOS (1 << 2)
#define ADI_MUX_OVER_RANGE (1 << 1)
#define ADI_STATUS (1 << 0)
#define ADI_REG_DELAY_CNTRL 0x0060 /* <= v8.0 */
#define ADI_DELAY_SEL (1 << 17)
#define ADI_DELAY_RWN (1 << 16)
#define ADI_DELAY_ADDRESS(x) (((x) & 0xFF) << 8)
#define ADI_TO_DELAY_ADDRESS(x) (((x) >> 8) & 0xFF)
#define ADI_DELAY_WDATA(x) (((x) & 0x1F) << 0)
#define ADI_TO_DELAY_WDATA(x) (((x) >> 0) & 0x1F)
#define ADI_REG_DELAY_STATUS 0x0064 /* <= v8.0 */
#define ADI_DELAY_LOCKED (1 << 9)
#define ADI_DELAY_STATUS (1 << 8)
#define ADI_DELAY_RDATA(x) (((x) & 0x1F) << 0)
#define ADI_TO_DELAY_RDATA(x) (((x) >> 0) & 0x1F)
#define ADI_REG_DRP_CNTRL 0x0070
#define ADI_DRP_SEL (1 << 29)
#define ADI_DRP_RWN (1 << 28)
#define ADI_DRP_ADDRESS(x) (((x) & 0xFFF) << 16)
#define ADI_TO_DRP_ADDRESS(x) (((x) >> 16) & 0xFFF)
#define ADI_DRP_WDATA(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DRP_WDATA(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_DRP_STATUS 0x0074
#define ADI_DRP_STATUS (1 << 16)
#define ADI_DRP_RDATA(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DRP_RDATA(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_DMA_STATUS 0x0088
#define ADI_DMA_OVF (1 << 2)
#define ADI_DMA_UNF (1 << 1)
#define ADI_DMA_STATUS (1 << 0)
#define ADI_REG_DMA_BUSWIDTH 0x008C
#define ADI_DMA_BUSWIDTH(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_DMA_BUSWIDTH(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_USR_CNTRL_1 0x00A0
#define ADI_USR_CHANMAX(x) (((x) & 0xFF) << 0)
#define ADI_TO_USR_CHANMAX(x) (((x) >> 0) & 0xFF)
#define ADI_REG_GP_CONTROL 0x00BC
#define ADI_REG_CLOCKS_PER_PPS 0x00C0
#define ADI_REG_CLOCKS_PER_PPS_STATUS 0x00C4
#define ADI_CLOCKS_PER_PPS_STAT_INVAL (1 << 0)
/* ADC CHANNEL */
#define ADI_REG_CHAN_CNTRL(c) (0x0400 + (c) * 0x40)
#define ADI_PN_SEL (1 << 10) /* !v8.0 */
#define ADI_IQCOR_ENB (1 << 9)
#define ADI_DCFILT_ENB (1 << 8)
#define ADI_FORMAT_SIGNEXT (1 << 6)
#define ADI_FORMAT_TYPE (1 << 5)
#define ADI_FORMAT_ENABLE (1 << 4)
#define ADI_PN23_TYPE (1 << 1) /* !v8.0 */
#define ADI_ENABLE (1 << 0)
#define ADI_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40)
#define ADI_PN_ERR (1 << 2)
#define ADI_PN_OOS (1 << 1)
#define ADI_OVER_RANGE (1 << 0)
#define ADI_REG_CHAN_CNTRL_1(c) (0x0410 + (c) * 0x40)
#define ADI_DCFILT_OFFSET(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_DCFILT_OFFSET(x) (((x) >> 16) & 0xFFFF)
#define ADI_DCFILT_COEFF(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DCFILT_COEFF(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_CHAN_CNTRL_2(c) (0x0414 + (c) * 0x40)
#define ADI_IQCOR_COEFF_1(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_IQCOR_COEFF_1(x) (((x) >> 16) & 0xFFFF)
#define ADI_IQCOR_COEFF_2(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_IQCOR_COEFF_2(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_CHAN_CNTRL_3(c) (0x0418 + (c) * 0x40) /* v8.0 */
#define ADI_ADC_PN_SEL(x) (((x) & 0xF) << 16)
#define ADI_TO_ADC_PN_SEL(x) (((x) >> 16) & 0xF)
#define ADI_ADC_DATA_SEL(x) (((x) & 0xF) << 0)
#define ADI_TO_ADC_DATA_SEL(x) (((x) >> 0) & 0xF)
enum adc_pn_sel {
ADC_PN9 = 0,
ADC_PN23A = 1,
ADC_PN7 = 4,
ADC_PN15 = 5,
ADC_PN23 = 6,
ADC_PN31 = 7,
ADC_PN_CUSTOM = 9,
ADC_PN_OFF = 10,
};
enum adc_data_sel {
ADC_DATA_SEL_NORM,
ADC_DATA_SEL_LB, /* DAC loopback */
ADC_DATA_SEL_RAMP, /* TBD */
};
#define ADI_REG_CHAN_USR_CNTRL_1(c) (0x0420 + (c) * 0x40)
#define ADI_USR_DATATYPE_BE (1 << 25)
#define ADI_USR_DATATYPE_SIGNED (1 << 24)
#define ADI_USR_DATATYPE_SHIFT(x) (((x) & 0xFF) << 16)
#define ADI_TO_USR_DATATYPE_SHIFT(x) (((x) >> 16) & 0xFF)
#define ADI_USR_DATATYPE_TOTAL_BITS(x) (((x) & 0xFF) << 8)
#define ADI_TO_USR_DATATYPE_TOTAL_BITS(x) (((x) >> 8) & 0xFF)
#define ADI_USR_DATATYPE_BITS(x) (((x) & 0xFF) << 0)
#define ADI_TO_USR_DATATYPE_BITS(x) (((x) >> 0) & 0xFF)
#define ADI_REG_CHAN_USR_CNTRL_2(c) (0x0424 + (c) * 0x40)
#define ADI_USR_DECIMATION_M(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_USR_DECIMATION_M(x) (((x) >> 16) & 0xFFFF)
#define ADI_USR_DECIMATION_N(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_USR_DECIMATION_N(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_ADC_DP_DISABLE 0x00C0
/* PCORE Version > 8.00 */
#define ADI_REG_DELAY(l) (0x0800 + (l) * 0x4)
/* debugfs direct register access */
#define DEBUGFS_DRA_PCORE_REG_MAGIC 0x80000000
#define AXIADC_MAX_CHANNEL 16
#include <linux/spi/spi.h>
#include <linux/clk/clkscale.h>
struct axiadc_chip_info {
char *name;
unsigned num_channels;
unsigned num_shadow_slave_channels;
const unsigned long *scan_masks;
const int (*scale_table)[2];
int num_scales;
int max_testmode;
unsigned long max_rate;
struct iio_chan_spec channel[AXIADC_MAX_CHANNEL];
};
struct axiadc_state {
struct device *dev_spi;
struct iio_info iio_info;
struct clk *clk;
struct gpio_desc *gpio_decimation;
size_t regs_size;
void __iomem *regs;
void __iomem *slave_regs;
unsigned max_usr_channel;
unsigned adc_def_output_mode;
unsigned max_count;
unsigned id;
unsigned pcore_version;
unsigned decimation_factor;
unsigned int oversampling_ratio;
bool dp_disable;
unsigned long long adc_clk;
unsigned have_slave_channels;
bool additional_channel;
struct iio_hw_consumer *frontend;
struct iio_chan_spec channels[AXIADC_MAX_CHANNEL];
};
struct axiadc_converter {
struct spi_device *spi;
struct clk *clk;
struct clock_scale adc_clkscale;
struct clk *lane_clk;
struct clk *sysref_clk;
void *phy;
struct gpio_desc *pwrdown_gpio;
struct gpio_desc *reset_gpio;
unsigned id;
unsigned adc_output_mode;
unsigned testmode[AXIADC_MAX_CHANNEL];
unsigned scratch_reg[AXIADC_MAX_CHANNEL];
unsigned long adc_clk;
const struct axiadc_chip_info *chip_info;
struct delayed_work watchdog_work;
bool sample_rate_read_only;
int (*reg_access)(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval);
int (*setup)(struct spi_device *spi, unsigned mode);
struct iio_chan_spec const *channels;
int num_channels;
const struct attribute_group *attrs;
struct iio_dev *indio_dev;
int (*read_raw)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask);
int (*write_raw)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask);
int (*read_event_value)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val,
int *val2);
int (*write_event_value)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val,
int val2);
int (*read_event_config)(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir);
int (*write_event_config)(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state);
int (*post_setup)(struct iio_dev *indio_dev);
int (*post_iio_register)(struct iio_dev *indio_dev);
int (*set_pnsel)(struct iio_dev *indio_dev, unsigned chan,
enum adc_pn_sel sel);
};
static inline struct axiadc_converter *to_converter(struct device *dev)
{
struct axiadc_converter *conv = spi_get_drvdata(to_spi_device(dev));
if (conv)
return conv;
return ERR_PTR(-ENODEV);
};
struct axiadc_spidev {
struct device_node *of_nspi;
struct device *dev_spi;
};
/*
* IO accessors
*/
static inline void axiadc_write(struct axiadc_state *st, unsigned reg, unsigned val)
{
iowrite32(val, st->regs + reg);
}
static inline unsigned int axiadc_read(struct axiadc_state *st, unsigned reg)
{
return ioread32(st->regs + reg);
}
static inline void axiadc_slave_write(struct axiadc_state *st, unsigned reg, unsigned val)
{
iowrite32(val, st->slave_regs + reg);
}
static inline unsigned int axiadc_slave_read(struct axiadc_state *st, unsigned reg)
{
return ioread32(st->slave_regs + reg);
}
static inline void axiadc_idelay_set(struct axiadc_state *st,
unsigned lane, unsigned val)
{
if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8) {
axiadc_write(st, ADI_REG_DELAY(lane), val);
} else {
axiadc_write(st, ADI_REG_DELAY_CNTRL, 0);
axiadc_write(st, ADI_REG_DELAY_CNTRL,
ADI_DELAY_ADDRESS(lane)
| ADI_DELAY_WDATA(val)
| ADI_DELAY_SEL);
}
}
int axiadc_set_pnsel(struct axiadc_state *st, int channel, enum adc_pn_sel sel);
enum adc_pn_sel axiadc_get_pnsel(struct axiadc_state *st,
int channel, const char **name);
int axiadc_configure_ring_stream(struct iio_dev *indio_dev,
const char *dma_name);
void axiadc_unconfigure_ring_stream(struct iio_dev *indio_dev);
#endif /* ADI_AXI_ADC_H_ */

57
driver/hw_def.h
View File

@ -1,7 +1,14 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
// Author: Xianjun jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
const char *sdr_compatible_str = "sdr,sdr";
enum openwifi_fpga_type {
SMALL_FPGA = 0,
LARGE_FPGA = 1,
};
enum openwifi_band {
BAND_900M = 0,
BAND_2_4GHZ,
@ -20,7 +27,7 @@ const char *tx_intf_compatible_str = "sdr,tx_intf";
#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4)
#define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4)
#define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4)
#define TX_INTF_REG_CSI_FUZZER_ADDR (5*4)
#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4)
#define TX_INTF_REG_MISC_SEL_ADDR (7*4)
#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
@ -54,7 +61,7 @@ const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
struct tx_intf_driver_api {
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
@ -64,7 +71,7 @@ struct tx_intf_driver_api {
u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
u32 (*TX_INTF_REG_CSI_FUZZER_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
u32 (*TX_INTF_REG_MISC_SEL_read)(void);
u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
@ -84,7 +91,7 @@ struct tx_intf_driver_api {
void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
void (*TX_INTF_REG_MISC_SEL_write)(u32 value);
void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
@ -182,6 +189,7 @@ const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
#define OPENOFDM_RX_REG_ENABLE_ADDR (1*4)
#define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4)
#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4)
#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)
#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
enum openofdm_rx_mode {
@ -204,6 +212,7 @@ struct openofdm_rx_driver_api {
void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);
};
// ---------------------------------------openofdm tx-------------------------------
@ -240,21 +249,22 @@ struct openofdm_tx_driver_api {
const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4)
#define XPU_REG_SLICE_COUNT_START_ADDR (21*4)
@ -341,6 +351,9 @@ struct xpu_driver_api {
void (*XPU_REG_DIFS_ADVANCE_write)(u32 value);
u32 (*XPU_REG_DIFS_ADVANCE_read)(void);
void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value);
u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void);
u32 (*XPU_REG_TRX_STATUS_read)(void);
u32 (*XPU_REG_TX_RESULT_read)(void);
@ -384,7 +397,9 @@ struct xpu_driver_api {
u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value);
void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value);
u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void);
void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
};

23
driver/make_all.sh
View File

@ -1,12 +1,17 @@
#!/bin/bash
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)"
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
exit 1
fi
OPENWIFI_DIR=$1
XILINX_DIR=$2
ARCH_OPTION=$3
OPENWIFI_DIR=$(pwd)/../
XILINX_DIR=$1
ARCH_OPTION=$2
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
@ -34,10 +39,12 @@ if [ "$ARCH_OPTION" == "64" ]; then
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
ARCH="arm64"
CROSS_COMPILE="aarch64-linux-gnu-"
echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
else
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/
ARCH="arm"
CROSS_COMPILE="arm-linux-gnueabihf-"
echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
fi
# check if user entered the right path to analog device linux
@ -65,9 +72,7 @@ cd $OPENWIFI_DIR/driver/rx_intf
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/xpu
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/ad9361
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/xilinx_dma
./make_xilinx_dma.sh $OPENWIFI_DIR $XILINX_DIR $ARCH_OPTION
# cd $OPENWIFI_DIR/driver/ad9361
# make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $home_dir

13
driver/openofdm_rx/openofdm_rx.c
View File

@ -1,7 +1,8 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
@ -51,7 +52,9 @@ static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) {
static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_rx", },
{}
@ -94,6 +97,7 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
// 1) power threshold configuration and reset
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100);
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write(1);
//rst
for (i=0;i<8;i++)
@ -139,6 +143,7 @@ static int dev_probe(struct platform_device *pdev)
openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write;
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);

6
driver/openofdm_tx/openofdm_tx.c
View File

@ -1,7 +1,9 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>

8
driver/rx_intf/rx_intf.c
View File

@ -1,7 +1,9 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
@ -287,7 +289,7 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
//rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000);
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100);
//0x000-normal; 0x100-sig and fcs valid are controled by bit4 and bit0;
//0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0;
//0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0);

231
driver/sdr.c
View File

@ -1,4 +1,6 @@
//Author: Xianjun Jiao. putaoshu@msn.com; xianjun.jiao@imec.be
// Author: Xianjun Jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
#include <linux/bitops.h>
#include <linux/dmapool.h>
@ -43,11 +45,16 @@
#include <linux/leds.h>
#define IIO_AD9361_USE_PRIVATE_H_
#include "ad9361/ad9361_regs.h"
#include "ad9361/ad9361.h"
#include "ad9361/ad9361_private.h"
#include <../../drivers/iio/adc/ad9361_regs.h>
#include <../../drivers/iio/adc/ad9361.h>
#include <../../drivers/iio/adc/ad9361_private.h>
#include <../../drivers/iio/frequency/cf_axi_dds.h>
extern int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);
extern int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
bool tx1, bool tx2, bool immed);
extern int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
struct ctrl_outs_control *ctrl);
#include "../user_space/sdrctl_src/nl80211_testmode_def.h"
#include "hw_def.h"
@ -126,14 +133,15 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
u32 actual_rx_lo = conf->chandef.chan->center_freq - priv->rx_freq_offset_to_lo_MHz + priv->drv_rx_reg_val[DRV_RX_REG_IDX_EXTRA_FO];
u32 actual_tx_lo;
bool change_flag = (actual_rx_lo != priv->actual_rx_lo);
int static_lbt_th, auto_lbt_th, fpga_lbt_th;
if (change_flag) {
priv->actual_rx_lo = actual_rx_lo;
actual_tx_lo = conf->chandef.chan->center_freq - priv->tx_freq_offset_to_lo_MHz;
ad9361_clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo )>>1) );
ad9361_clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo )>>1) );
clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo )>>1) );
clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo )>>1) );
if (actual_rx_lo<2412) {
priv->rssi_correction = 153;
@ -150,8 +158,14 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
}
// xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62)<<1); // -62dBm
xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44
// xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44
auto_lbt_th = ((priv->rssi_correction-62-16)<<1);
static_lbt_th = priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH];
fpga_lbt_th = (static_lbt_th==0?auto_lbt_th:static_lbt_th);
xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th);
priv->last_auto_fpga_lbt_th = auto_lbt_th;
if (actual_rx_lo < 2500) {
//priv->slot_time = 20; //20 is default slot time in ERP(OFDM)/11g 2.4G; short one is 9.
//xpu_api->XPU_REG_BAND_CHANNEL_write(BAND_2_4GHZ<<16);
@ -183,8 +197,8 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
//printk("%s ad9361_rf_set_channel tune to %d read back %llu\n", sdr_compatible_str,conf->chandef.chan->center_freq,2*priv->ad9361_phy->state->current_rx_lo_freq);
//ad9361_set_trx_clock_chain_default(priv->ad9361_phy);
//printk("%s ad9361_rf_set_channel tune to %d read back %llu\n", sdr_compatible_str,conf->chandef.chan->center_freq,2*priv->ad9361_phy->state->current_rx_lo_freq);
printk("%s ad9361_rf_set_channel %dM rssi_correction %d (change flag %d) fpga_lbt_th %d (auto %d static %d)\n", sdr_compatible_str,conf->chandef.chan->center_freq,priv->rssi_correction,change_flag,fpga_lbt_th,auto_lbt_th,static_lbt_th);
}
printk("%s ad9361_rf_set_channel %dM rssi_correction %d (change flag %d)\n", sdr_compatible_str,conf->chandef.chan->center_freq,priv->rssi_correction,change_flag);
}
const struct openwifi_rf_ops ad9361_rf_ops = {
@ -229,8 +243,8 @@ static int openwifi_init_tx_ring(struct openwifi_priv *priv, int ring_idx)
for (i = 0; i < NUM_TX_BD; i++) {
ring->bds[i].skb_linked=0; // for tx, skb is from upper layer
//at frist right after skb allocated, head, data, tail are the same.
ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from uppler layer in tx routine
//at first right after skb allocated, head, data, tail are the same.
ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from upper layer in tx routine
}
return 0;
@ -253,8 +267,8 @@ static void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx)
// dev_kfree_skb(ring->bds[i].skb_linked); // only use dev_kfree_skb when there is exception
if ( (ring->bds[i].dma_mapping_addr != 0 && ring->bds[i].skb_linked == 0) ||
(ring->bds[i].dma_mapping_addr == 0 && ring->bds[i].skb_linked != 0))
printk("%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08llx\n", sdr_compatible_str,
ring_idx, i, (void*)(ring->bds[i].skb_linked), ring->bds[i].dma_mapping_addr);
printk("%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08x\n", sdr_compatible_str,
ring_idx, i, (void*)(ring->bds[i].skb_linked), (unsigned int)(ring->bds[i].dma_mapping_addr));
ring->bds[i].skb_linked=0;
ring->bds[i].dma_mapping_addr = 0;
@ -266,12 +280,24 @@ static void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx)
static int openwifi_init_rx_ring(struct openwifi_priv *priv)
{
int i;
u8 *pdata_tmp;
priv->rx_cyclic_buf = dma_alloc_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,&priv->rx_cyclic_buf_dma_mapping_addr,GFP_KERNEL);
if (!priv->rx_cyclic_buf) {
printk("%s openwifi_init_rx_ring: WARNING dma_alloc_coherent failed!\n", sdr_compatible_str);
dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr);
return(-1);
}
// Set tsft_low and tsft_high to 0. If they are not zero, it means there is a packet in the buffer by DMA
for (i=0; i<NUM_RX_BD; i++) {
pdata_tmp = priv->rx_cyclic_buf + i*RX_BD_BUF_SIZE; // our header insertion is at the beginning
(*((u32*)(pdata_tmp+0 ))) = 0;
(*((u32*)(pdata_tmp+4 ))) = 0;
}
printk("%s openwifi_init_rx_ring: tsft_low and tsft_high are cleared!\n", sdr_compatible_str);
return 0;
}
@ -317,20 +343,29 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
struct ieee80211_hdr *hdr;
u32 addr1_low32=0, addr2_low32=0, addr3_low32=0, len, rate_idx, tsft_low, tsft_high, loop_count=0, ht_flag, short_gi;//, fc_di;
// u32 dma_driver_buf_idx_mod;
u8 *pdata_tmp, fcs_ok, target_buf_idx;//, phy_rx_sn_hw;
u8 *pdata_tmp, fcs_ok;//, target_buf_idx;//, phy_rx_sn_hw;
s8 signal;
u16 rssi_val, addr1_high16=0, addr2_high16=0, addr3_high16=0, sc=0;
u16 agc_status_and_pkt_exist_flag, rssi_val, addr1_high16=0, addr2_high16=0, addr3_high16=0, sc=0;
bool content_ok = false, len_overflow = false;
struct dma_tx_state state;
static u8 target_buf_idx_old = 0xFF;
#ifdef USE_NEW_RX_INTERRUPT
int i;
spin_lock(&priv->lock);
priv->rx_chan->device->device_tx_status(priv->rx_chan,priv->rx_cookie,&state);
target_buf_idx = ((state.residue-1)&(NUM_RX_BD-1));
while( target_buf_idx_old!=target_buf_idx ) { // loop all rx buffers that have new rx packets
target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1));
for (i=0; i<NUM_RX_BD; i++) {
pdata_tmp = priv->rx_cyclic_buf + i*RX_BD_BUF_SIZE;
agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10))); //check rx_intf_pl_to_m_axis.v. FPGA TODO: add pkt exist 1bit flag next to gpio_status_lock_by_sig_valid
if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer
continue;
#else
static u8 target_buf_idx_old = 0;
spin_lock(&priv->lock);
while(1) { // loop all rx buffers that have new rx packets
pdata_tmp = priv->rx_cyclic_buf + target_buf_idx_old*RX_BD_BUF_SIZE; // our header insertion is at the beginning
agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10)));
if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer
break;
#endif
tsft_low = (*((u32*)(pdata_tmp+0 )));
tsft_high = (*((u32*)(pdata_tmp+4 )));
rssi_val = (*((u16*)(pdata_tmp+8 )));
@ -388,11 +423,15 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
if (len>=28)
sc = hdr->seq_ctrl;
if ( addr1_low32!=0xffffffff || addr1_high16!=0xffff )
if ( (addr1_low32!=0xffffffff || addr1_high16!=0xffff) || (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&4) )
printk("%s openwifi_rx_interrupt:%4dbytes ht%d %3dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x fcs%d buf_idx%d %ddBm\n", sdr_compatible_str,
len, ht_flag, wifi_rate_table[rate_idx], hdr->frame_control, hdr->duration_id,
reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
#ifdef USE_NEW_RX_INTERRUPT
sc, fcs_ok, i, signal);
#else
sc, fcs_ok, target_buf_idx_old, signal);
#endif
}
// priv->phy_rx_sn_hw_old = phy_rx_sn_hw;
@ -424,7 +463,11 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
} else
printk("%s openwifi_rx_interrupt: WARNING dev_alloc_skb failed!\n", sdr_compatible_str);
}
(*((u16*)(pdata_tmp+10))) = 0; // clear the field (set by rx_intf_pl_to_m_axis.v) to indicate the packet has been processed
loop_count++;
#ifndef USE_NEW_RX_INTERRUPT
target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1));
#endif
}
if ( loop_count!=1 && (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&1) )
@ -442,7 +485,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
struct openwifi_ring *ring;
struct sk_buff *skb;
struct ieee80211_tx_info *info;
u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, loop_count=0;//, i;
u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, num_slot_random, cw, loop_count=0;//, i;
u8 tx_result_report;
// u16 prio_rd_idx_store[64]={0};
@ -450,8 +493,15 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
while(1) { // loop all packets that have been sent by FPGA
reg_val = tx_intf_api->TX_INTF_REG_PKT_INFO_read();
if (reg_val!=0x7FFFF) {
prio = (reg_val>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
if (reg_val!=0xFFFFFFFF) {
prio = ((0x7FFFF & reg_val)>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
cw = ((0xF0000000 & reg_val) >> 28);
num_slot_random = ((0xFF80000 &reg_val)>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
if(cw > 10) {
cw = 10 ;
num_slot_random += 512 ;
}
ring = &(priv->tx_ring[prio]);
ring->bd_rd_idx = ((reg_val>>5)&MAX_PHY_TX_SN);
skb = ring->bds[ring->bd_rd_idx].skb_linked;
@ -506,6 +556,8 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
if ( (tx_result_report&0x10) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&1) )
printk("%s openwifi_tx_interrupt: WARNING tx_result %02x prio%d wr%d rd%d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx);
if ( ( (!(info->flags & IEEE80211_TX_CTL_NO_ACK))||(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&4) ) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&2) )
printk("%s openwifi_tx_interrupt: tx_result %02x prio%d wr%d rd%d num_rand_slot %d cw %d \n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx, num_slot_random,cw);
ieee80211_tx_status_irqsafe(dev, skb);
@ -685,7 +737,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
}
}
//}
queue_idx = (i>=MAX_NUM_HW_QUEUE?2:i); // if no address is hit, use FPGA queue 2. becuase the queue 2 is the longest.
queue_idx = (i>=MAX_NUM_HW_QUEUE?2:i); // if no address is hit, use FPGA queue 2. because the queue 2 is the longest.
}
// -------------------- end of Map Linux/SW "prio" to hardware "queue_idx" ------------------
@ -769,7 +821,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
sc = hdr->seq_ctrl;
}
if ( (!addr_flag) && (priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&2) )
if ( ( (!addr_flag)||(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&4) ) && (priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&2) )
printk("%s openwifi_tx: %4dbytes ht%d %3dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x flag%08x retr%d ack%d prio%d q%d wr%d rd%d\n", sdr_compatible_str,
len_mac_pdu, (use_ht_rate == false ? 0 : 1), (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]),frame_control,duration_id,
reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
@ -818,7 +870,6 @@ static void openwifi_tx(struct ieee80211_hw *dev,
skb_push( skb, LEN_PHY_HEADER );
rate_signal_value = calc_phy_header(rate_hw_value, use_ht_rate, use_short_gi, len_mac_pdu+LEN_PHY_CRC, skb->data); //fill the phy header
//make sure dma length is integer times of DDC_NUM_BYTE_PER_DMA_SYMBOL
if (skb_tailroom(skb)<num_byte_pad) {
printk("%s openwifi_tx: WARNING sn %d skb_tailroom(skb)<num_byte_pad!\n", sdr_compatible_str, ring->bd_wr_idx);
@ -827,7 +878,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
}
skb_put( skb, num_byte_pad );
retry_limit_hw_value = (retry_limit_raw - 1)&0xF;
retry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) );
dma_buf = skb->data;
cts_rate_signal_value = wifi_mcs_table_11b_force_up[cts_rate_hw_value];
@ -839,8 +890,8 @@ static void openwifi_tx(struct ieee80211_hw *dev,
*/
//wmb();
// entry->flags = cpu_to_le32(tx_flags);
/* We must be sure this has been written before followings HW
* register write, because this write will made the HW attempts
/* We must be sure this has been written before following HW
* register write, because this write will make the HW attempts
* to DMA the just-written data
*/
//wmb();
@ -899,7 +950,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
goto openwifi_tx_after_dma_mapping;
}
// seems everything ok. let's mark this pkt in bd descriptor ring
// seems everything is ok. let's mark this pkt in bd descriptor ring
ring->bds[ring->bd_wr_idx].skb_linked = skb;
ring->bds[ring->bd_wr_idx].dma_mapping_addr = dma_mapping_addr;
@ -975,28 +1026,27 @@ static int openwifi_start(struct ieee80211_hw *dev)
priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
xpu_api->hw_init(priv->xpu_cfg);
agc_gain_delay = 50; //samples
rssi_half_db_offset = 150;
rssi_half_db_offset = 150; // to be consistent
xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );
xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
// rssi_half_db_th = 87<<1; // -62dBm // will settup in runtime in _rf_set_channel
// rssi_half_db_th = 87<<1; // -62dBm // will setup in runtime in _rf_set_channel
// xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
// xpu_api->XPU_REG_CSMA_CFG_write(3); // cw_min -- already set in xpu.c
xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
//xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51+23)<<16)|(0+23) );//we have more time when we use FIR in AD9361
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
@ -1048,19 +1098,19 @@ static int openwifi_start(struct ieee80211_hw *dev)
}
priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm");
if (IS_ERR(priv->rx_chan)) {
if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) {
ret = PTR_ERR(priv->rx_chan);
pr_err("%s openwifi_start: No Rx channel %d\n",sdr_compatible_str,ret);
pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan);
goto err_dma;
}
priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s");
if (IS_ERR(priv->tx_chan)) {
if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) {
ret = PTR_ERR(priv->tx_chan);
pr_err("%s openwifi_start: No Tx channel %d\n",sdr_compatible_str,ret);
pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan);
goto err_dma;
}
printk("%s openwifi_start: DMA channel setup successfully.\n",sdr_compatible_str);
printk("%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\n",sdr_compatible_str, priv->rx_chan, priv->tx_chan);
ret = openwifi_init_rx_ring(priv);
if (ret) {
@ -1093,7 +1143,7 @@ static int openwifi_start(struct ieee80211_hw *dev)
priv->irq_tx = irq_of_parse_and_map(priv->pdev->dev.of_node, 3);
ret = request_irq(priv->irq_tx, openwifi_tx_interrupt,
IRQF_SHARED, "sdr,tx_itrpt1", dev);
IRQF_SHARED, "sdr,tx_itrpt", dev);
if (ret) {
wiphy_err(dev->wiphy, "openwifi_start: failed to register IRQ handler openwifi_tx_interrupt\n");
goto err_free_rings;
@ -1378,12 +1428,35 @@ static void openwifi_bss_info_changed(struct ieee80211_hw *dev,
changed&BSS_CHANGED_BEACON_ENABLED,changed&BSS_CHANGED_BEACON);
}
}
// helper function
u32 log2val(u32 val){
u32 ret_val = 0 ;
while(val>1){
val = val >> 1 ;
ret_val ++ ;
}
return ret_val ;
}
static int openwifi_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
const struct ieee80211_tx_queue_params *params)
{
printk("%s openwifi_conf_tx: WARNING [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
u32 reg_val, cw_min_exp, cw_max_exp;
printk("%s openwifi_conf_tx: [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\n",
sdr_compatible_str,queue,params->aifs,params->cw_min,params->cw_max,params->txop);
reg_val=xpu_api->XPU_REG_CSMA_CFG_read();
cw_min_exp = (log2val(params->cw_min + 1) & 0x0F);
cw_max_exp = (log2val(params->cw_max + 1) & 0x0F);
switch(queue){
case 0: reg_val = ( (reg_val & 0xFFFFFF00) | ((cw_min_exp | (cw_max_exp << 4)) << 0) ); break;
case 1: reg_val = ( (reg_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8) ); break;
case 2: reg_val = ( (reg_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16) ); break;
case 3: reg_val = ( (reg_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24) ); break;
default: printk("%s openwifi_conf_tx: WARNING queue %d does not exist",sdr_compatible_str, queue); return(0);
}
xpu_api->XPU_REG_CSMA_CFG_write(reg_val);
return(0);
}
@ -1620,9 +1693,11 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
if (!tb[OPENWIFI_ATTR_RSSI_TH])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]);
printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp);
xpu_api->XPU_REG_LBT_TH_write(tmp);
return 0;
// printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp);
// xpu_api->XPU_REG_LBT_TH_write(tmp);
// return 0;
printk("%s WARNING Please use command: sdrctl dev sdr0 set reg drv_xpu 0 reg_value! (1~2047, 0 means AUTO)!\n", sdr_compatible_str);
return -EOPNOTSUPP;
case OPENWIFI_CMD_GET_RSSI_TH:
skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
@ -1653,7 +1728,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
reg_addr_idx = (reg_addr>>2);
printk("%s recv set cmd reg cat %d addr %08x val %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_val, reg_addr_idx);
if (reg_cat==1)
printk("%s reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
else if (reg_cat==2)
rx_intf_api->reg_write(reg_addr,reg_val);
else if (reg_cat==3)
@ -1677,7 +1752,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
//priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];
}
} else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else if (reg_cat==8) {
if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {
@ -1695,16 +1770,25 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];
}
} else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else if (reg_cat==9) {
if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG)
if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {
priv->drv_xpu_reg_val[reg_addr_idx]=reg_val;
else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) {
if (reg_val) {
xpu_api->XPU_REG_LBT_TH_write(reg_val);
printk("%s override FPGA LBT threshold to %d. The last_auto_fpga_lbt_th %d\n", sdr_compatible_str, reg_val, priv->last_auto_fpga_lbt_th);
} else {
xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th);
printk("%s Restore last_auto_fpga_lbt_th %d to FPGA. ad9361_rf_set_channel will take control\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th);
}
}
} else
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else
printk("%s reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
return 0;
case REG_CMD_GET:
@ -1717,7 +1801,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
reg_addr_idx = (reg_addr>>2);
printk("%s recv get cmd reg cat %d addr %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_addr_idx);
if (reg_cat==1) {
printk("%s reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
tmp = 0xFFFFFFFF;
}
else if (reg_cat==2)
@ -1743,7 +1827,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
}
tmp = priv->drv_rx_reg_val[reg_addr_idx];
} else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else if (reg_cat==8) {
if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG) {
@ -1757,16 +1841,16 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
}
tmp = priv->drv_tx_reg_val[reg_addr_idx];
} else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else if (reg_cat==9) {
if (reg_addr_idx>=0 && reg_addr_idx<MAX_NUM_DRV_REG)
tmp = priv->drv_xpu_reg_val[reg_addr_idx];
else
printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
}
else
printk("%s reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
if (nla_put_u32(skb, REG_ATTR_VAL, tmp))
goto nla_put_failure;
@ -1833,7 +1917,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
struct ieee80211_hw *dev;
struct openwifi_priv *priv;
int err=1, rand_val;
const char *chip_name;
const char *chip_name, *fpga_model;
u32 reg;//, reg1;
struct device_node *np = pdev->dev.of_node;
@ -1868,6 +1952,19 @@ static int openwifi_dev_probe(struct platform_device *pdev)
priv = dev->priv;
priv->pdev = pdev;
err = of_property_read_string(of_find_node_by_path("/"), "model", &fpga_model);
if(err < 0) {
printk("%s openwifi_dev_probe: WARNING unknown openwifi FPGA model %d\n",sdr_compatible_str, err);
priv->fpga_type = SMALL_FPGA;
} else {
// LARGE FPGAs (i.e. ZCU102, Z7035, ZC706)
if(strstr(fpga_model, "ZCU102") != NULL || strstr(fpga_model, "Z7035") != NULL || strstr(fpga_model, "ZC706") != NULL)
priv->fpga_type = LARGE_FPGA;
// SMALL FPGA: (i.e. ZED, ZC702, Z7020)
else if(strstr(fpga_model, "ZED") != NULL || strstr(fpga_model, "ZC702") != NULL || strstr(fpga_model, "Z7020") != NULL)
priv->fpga_type = SMALL_FPGA;
}
// //-------------find ad9361-phy driver for lo/channel control---------------
priv->actual_rx_lo = 0;
tmp_dev = bus_find_device( &spi_bus_type, NULL, "ad9361-phy", custom_match_spi_dev );
@ -1949,6 +2046,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
// else
// printk("%s openwifi_dev_probe: WARNING rfkill radio off failed. tx att read %d %d require %d\n",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT);
priv->last_auto_fpga_lbt_th = 134;//just to avoid uninitialized
priv->rssi_correction = 43;//this will be set in real-time by _rf_set_channel()
//priv->rf_bw = 20000000; // Signal quality issue! NOT use for now. 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode
@ -2005,10 +2103,9 @@ static int openwifi_dev_probe(struct platform_device *pdev)
if (reg == AD9361_RADIO_ON_TX_ATT) {
priv->rfkill_off = 1;// 0 off, 1 on
printk("%s openwifi_dev_probe: rfkill radio on\n",sdr_compatible_str);
}
else
} else
printk("%s openwifi_dev_probe: WARNING rfkill radio on failed. tx att read %d require %d\n",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT);
memset(priv->drv_rx_reg_val,0,sizeof(priv->drv_rx_reg_val));
memset(priv->drv_tx_reg_val,0,sizeof(priv->drv_tx_reg_val));
memset(priv->drv_xpu_reg_val,0,sizeof(priv->drv_xpu_reg_val));
@ -2021,7 +2118,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
printk("%s openwifi_dev_probe: ad9361_update_rf_bandwidth %dHz err %d\n",sdr_compatible_str, priv->rf_bw,err);
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
printk("%s openwifi_dev_probe: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\n",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);
@ -2142,7 +2239,7 @@ static int openwifi_dev_probe(struct platform_device *pdev)
}
// // //--------------------hook leds (not complete yet)--------------------------------
// tmp_dev = bus_find_device( &platform_bus_type, NULL, "leds", custom_match_platform_dev ); //leds is the name in devicetree, not "compatiable" field
// tmp_dev = bus_find_device( &platform_bus_type, NULL, "leds", custom_match_platform_dev ); //leds is the name in devicetree, not "compatible" field
// if (!tmp_dev) {
// printk(KERN_ERR "%s bus_find_device platform_bus_type leds-gpio failed\n",sdr_compatible_str);
// err = -ENOMEM;

19
driver/sdr.h
View File

@ -1,10 +1,14 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
// Author: Xianjun Jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
#ifndef OPENWIFI_SDR
#define OPENWIFI_SDR
#include "pre_def.h"
// -------------------for leds--------------------------------
struct gpio_led_data { //pleas always align with the leds-gpio.c in linux kernel
struct gpio_led_data { //please always align with the leds-gpio.c in linux kernel
struct led_classdev cdev;
struct gpio_desc *gpiod;
u8 can_sleep;
@ -12,7 +16,7 @@ struct gpio_led_data { //pleas always align with the leds-gpio.c in linux kernel
gpio_blink_set_t platform_gpio_blink_set;
};
struct gpio_leds_priv { //pleas always align with the leds-gpio.c in linux kernel
struct gpio_leds_priv { //please always align with the leds-gpio.c in linux kernel
int num_leds;
struct gpio_led_data leds[];
};
@ -77,6 +81,7 @@ union u16_byte2 {
#define DRV_RX_REG_IDX_EXTRA_FO 2
#define DRV_RX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1)
#define DRV_XPU_REG_IDX_LBT_TH 0
#define DRV_XPU_REG_IDX_GIT_REV (MAX_NUM_DRV_REG-1)
// ------end of software reg definition ------------
@ -88,7 +93,13 @@ union u16_byte2 {
#define RING_ROOM_THRESHOLD 4
#define NUM_TX_BD 64 // !!! should align to the fifo size in tx_bit_intf.v
#ifdef USE_NEW_RX_INTERRUPT
#define NUM_RX_BD 8
#else
#define NUM_RX_BD 16
#endif
#define TX_BD_BUF_SIZE (8192)
#define RX_BD_BUF_SIZE (8192)
@ -304,6 +315,7 @@ struct openwifi_priv {
struct ieee80211_vif *vif[MAX_NUM_VIF];
const struct openwifi_rf_ops *rf;
enum openwifi_fpga_type fpga_type;
struct cf_axi_dds_state *dds_st; //axi_ad9361 hdl ref design module, dac channel
struct axiadc_state *adc_st; //axi_ad9361 hdl ref design module, adc channel
@ -362,6 +374,7 @@ struct openwifi_priv {
u32 drv_rx_reg_val[MAX_NUM_DRV_REG];
u32 drv_tx_reg_val[MAX_NUM_DRV_REG];
u32 drv_xpu_reg_val[MAX_NUM_DRV_REG];
int last_auto_fpga_lbt_th;
// u8 num_led;
// struct led_classdev *led[MAX_NUM_LED];//zc706 has 4 user leds. please find openwifi_dev_probe to see how we get them.
// char led_name[MAX_NUM_LED][OPENWIFI_LED_MAX_NAME_LEN];

17
driver/side_ch/make_driver.sh
View File

@ -1,12 +1,17 @@
#!/bin/bash
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)"
# Author: Xianjun Jiao, Wei Liu
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
exit 1
fi
OPENWIFI_DIR=$1
XILINX_DIR=$2
ARCH_OPTION=$3
OPENWIFI_DIR=$(pwd)/../../
XILINX_DIR=$1
ARCH_OPTION=$2
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
@ -55,4 +60,4 @@ home_dir=$(pwd)
cd $OPENWIFI_DIR/driver/side_ch
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $home_dir
cd $home_dir

6
driver/side_ch/side_ch.c
View File

@ -1,7 +1,9 @@
/*
* openwifi side channel driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun Jiao
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>

4
driver/side_ch/side_ch.h
View File

@ -1,4 +1,6 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
// Author: Xianjun Jiao
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
// ---------------------------------------side channel-------------------------------
const char *side_ch_compatible_str = "sdr,side_ch";

37
driver/tx_intf/tx_intf.c
View File

@ -1,7 +1,9 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
@ -54,8 +56,8 @@ static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){
return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){
return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR);
static inline u32 TX_INTF_REG_CSI_FUZZER_read(void){
return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR);
}
static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){
@ -132,8 +134,8 @@ static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){
reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value);
static inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){
reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value);
}
static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){
@ -194,7 +196,7 @@ static struct tx_intf_driver_api tx_intf_driver_api_inst;
static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
EXPORT_SYMBOL(tx_intf_api);
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){
int err=0, i;
u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0;
@ -208,7 +210,12 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
for (i=0;i<8;i++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
switch(mode)
{
case TX_INTF_AXIS_LOOP_BACK:
@ -276,7 +283,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel);
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2);
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
@ -331,7 +338,7 @@ static int dev_probe(struct platform_device *pdev)
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read;
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read;
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read;
tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read;
tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
@ -351,7 +358,7 @@ static int dev_probe(struct platform_device *pdev)
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write;
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write;
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write;
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write;
tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
@ -371,16 +378,16 @@ static int dev_probe(struct platform_device *pdev)
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);
printk("%s dev_probe succeed!\n", tx_intf_compatible_str);
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8);
//err = hw_init(TX_INTF_BYPASS, 8, 8);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA);
//err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma
return err;
}

6
driver/xilinx_dma/README.md
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@ -1,3 +1,9 @@
<!--
Author: Xianjun Jiao
SPDX-FileCopyrightText: 2021 UGent
SPDX-License-Identifier: AGPL-3.0-or-later
-->
We don't maintain our own (modified) xilinx dma driver anymore! The original xilinx dma driver in the Linux kernel tree can be used.
===============Following are obsolete content=================

15
driver/xilinx_dma/make_xilinx_dma.sh
View File

@ -1,13 +1,18 @@
#!/bin/bash
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$ARCH(32 or 64)"
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 arguments: \$XILINX_DIR \$ARCH(32 or 64)"
exit 1
fi
WORKDIR=$PWD
OPENWIFI_DIR=$1
XILINX_DIR=$2
ARCH_OPTION=$3
OPENWIFI_DIR=$(pwd)/../../
XILINX_DIR=$1
ARCH_OPTION=$2
set -x

12
driver/xilinx_dma/xilinx_dma.c
View File

@ -1,11 +1,9 @@
/*
* DMA driver for Xilinx Video DMA Engine
*
* Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
*
* Based on the Freescale DMA driver.
*
* Modified by Xianjun Jiao. putaoshu@msn.com; xianjun.jiao@imec.be
* SPDX-FileCopyrightText: Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved
* Based on the Freescale DMA driver
* Modified by Xianjun Jiao
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Description:
* The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
@ -421,7 +419,7 @@ struct xilinx_dma_config {
* @ext_addr: Indicates 64 bit addressing is supported by dma device
* @pdev: Platform device structure pointer
* @dma_config: DMA config structure
* @axi_clk: DMA Axi4-lite interace clock
* @axi_clk: DMA Axi4-lite interface clock
* @tx_clk: DMA mm2s clock
* @txs_clk: DMA mm2s stream clock
* @rx_clk: DMA s2mm clock

37
driver/xpu/xpu.c
View File

@ -1,7 +1,9 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
@ -140,6 +142,14 @@ static inline u32 XPU_REG_DIFS_ADVANCE_read(void){
return reg_read(XPU_REG_DIFS_ADVANCE_ADDR);
}
static inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) {
reg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data);
}
static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){
return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);
}
static inline u32 XPU_REG_TRX_STATUS_read(void){
return reg_read(XPU_REG_TRX_STATUS_ADDR);
}
@ -251,13 +261,15 @@ static inline u32 XPU_REG_SLICE_COUNT_END_read(void){
return reg_read(XPU_REG_SLICE_COUNT_END_ADDR);
}
static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
}
static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value);
static inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value);
}
static inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){
return reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR);
}
static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){
@ -337,7 +349,7 @@ static inline u32 hw_init(enum xpu_mode mode){
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"!
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz
//xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
//xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
// xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47);
xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed
@ -397,11 +409,13 @@ static inline u32 hw_init(enum xpu_mode mode){
rssi_half_db_th = 87<<1; // -62dBm
xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
xpu_api->XPU_REG_CSMA_DEBUG_write(0);
xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
// xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
@ -472,6 +486,9 @@ static int dev_probe(struct platform_device *pdev)
xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write;
xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read;
xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;
xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;
xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read;
xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read;
@ -508,7 +525,9 @@ static int dev_probe(struct platform_device *pdev)
xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read;
xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;
xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read;
xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write;

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kernel_boot/boards/antsdr/devicetree.dtb Normal file
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883
kernel_boot/boards/antsdr/devicetree.dts Normal file
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@ -0,0 +1,883 @@
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "MicroPhase ANTSDR-E310 (Z7020/AD9361 Z7020/AD9363)";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9364_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x2>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x2>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x40>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x40>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x7>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x8>;
phandle = <0x8>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x8>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x8>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x8>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0x9>;
phandle = <0x9>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x9>;
#clock-cells = <0x0>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x39 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0xa>;
phandle = <0xa>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x2>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x0>;
};
};
};
dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x38 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0xc>;
phandle = <0xc>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x0>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x2>;
};
};
};
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
dmas = <0xa 0x0>;
dma-names = "rx";
spibus-connected = <0xb>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0xb 0xd>;
clock-names = "sampl_clk";
dmas = <0xc 0x0>;
dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x6 0xF 0>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x1>;
#size-cells = <0x0>;
autorepeat;
sw1 {
label = "SW1";
linux,input-type = <0x5>;
linux,code = <0x3>;
gpios = <0x6 0xE 0x0>;
};
};
};

15
kernel_boot/boards/antsdr/notes.md Normal file
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@ -0,0 +1,15 @@
# antsdr for openwifi-hw
## Introduction
[ANTSDR](https://github.com/MicroPhase/antsdr-fw) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.
<!--
This README file will give the instructions about how to make the openwifi-hw project for antsdr in the [antsdr branch](https://github.com/MicroPhase/openwifi-hw/tree/antsdr) of openwifi-hw project.
-->
<!--
Above should be unnecessary, because antsdr will be in the master in the future.
-->
## Work to be done
The antsdr has RF switch in the front-end, for now, the RF switch is fixed at a higer range, which will isolation the frequency below 3GHz and pass the frequency at 3GHz~6GHz.
For future work, it can add the rf swicth control in the devicetree, and this will change the rf switch with the frequency change.

BIN
kernel_boot/boards/antsdr/u-boot.elf Executable file
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19
kernel_boot/build_boot_bin.sh
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@ -1,24 +1,29 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_2014r2
if [ "$#" -ne 1 ]; then
echo "You must enter the \$BOARD_NAME as argument"
echo "Like: adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371"
if [ "$#" -ne 2 ]; then
echo "You must enter the \$OPENWIFI_HW_DIR \$BOARD_NAME as argument"
echo "BOARD_NAME Like: antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371"
exit 1
fi
BOARD_NAME=$1
if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
OPENWIFI_HW_DIR=$1
BOARD_NAME=$2
if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
echo "\$BOARD_NAME is not correct. Please check!"
exit 1
else
echo "\$BOARD_NAME is found!"
fi
set -ex
HDF_FILE=../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf
HDF_FILE=$OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf
UBOOT_FILE=./boards/$BOARD_NAME/u-boot.elf
BUILD_DIR=./boards/$BOARD_NAME/build_boot_bin
OUTPUT_DIR=./boards/$BOARD_NAME/output_boot_bin

7
kernel_boot/build_zynqmp_boot_bin.sh
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@ -1,4 +1,8 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp
set -ex
@ -97,7 +101,8 @@ tool_version=${tool_version%\ (64-bit)*}
# (https://www.xilinx.com/support/answers/71961.html)
if [ $tool_version == "v2018.3" ];then
(
wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
# wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
cp -P 72113-files.zip $BUILD_DIR
unzip $BUILD_DIR/72113-files.zip -d $BUILD_DIR
)
fi

5
openwifi-arch.jpg.license Normal file
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@ -0,0 +1,5 @@
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later

1
openwifi-hw

@ -1 +0,0 @@
Subproject commit b3bd6e298feaa75f7be688f5fe2ded842351fca1

25
user_space/boot_bin_gen.sh
View File

@ -1,13 +1,23 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME"
echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME"
exit 1
fi
OPENWIFI_DIR=$1
OPENWIFI_HW_DIR=$1
XILINX_DIR=$2
BOARD_NAME=$3
OPENWIFI_DIR=$(pwd)/../
echo OPENWIFI_DIR $OPENWIFI_DIR
echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
@ -22,13 +32,20 @@ else
exit 1
fi
if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
echo "\$BOARD_NAME is not correct. Please check!"
exit 1
else
echo "\$BOARD_NAME is found!"
fi
if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then
echo "\$OPENWIFI_HW_DIR is found!"
else
echo "\$OPENWIFI_HW_DIR is not correct. Please check!"
exit 1
fi
home_dir=$(pwd)
set -ex
@ -38,6 +55,6 @@ source $XILINX_DIR/SDK/2018.3/settings64.sh
cd $OPENWIFI_DIR/kernel_boot
./build_boot_bin.sh $BOARD_NAME
./build_boot_bin.sh $OPENWIFI_HW_DIR $BOARD_NAME
cd $home_dir

25
user_space/boot_bin_gen_zynqmp.sh
View File

@ -1,13 +1,23 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME"
echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME"
exit 1
fi
OPENWIFI_DIR=$1
OPENWIFI_HW_DIR=$1
XILINX_DIR=$2
BOARD_NAME=$3
OPENWIFI_DIR=$(pwd)/../
echo OPENWIFI_DIR $OPENWIFI_DIR
echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
@ -29,6 +39,13 @@ else
echo "\$BOARD_NAME is found!"
fi
if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then
echo "\$OPENWIFI_HW_DIR is found!"
else
echo "\$OPENWIFI_HW_DIR is not correct. Please check!"
exit 1
fi
home_dir=$(pwd)
set -ex
@ -38,8 +55,8 @@ source $XILINX_DIR/SDK/2018.3/settings64.sh
cd $OPENWIFI_DIR/kernel_boot
./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf
# ./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf download
./build_zynqmp_boot_bin.sh $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf
rm -rf build_boot_bin
rm -rf boards/$BOARD_NAME/output_boot_bin
mv output_boot_bin boards/$BOARD_NAME/

15
user_space/build_wpa_supplicant_wo11b.sh
View File

@ -1,10 +1,15 @@
#!/bin/bash
if [ "$#" -ne 1 ]; then
echo "You must enter exactly 1 arguments: \$OPENWIFI_DIR"
exit 1
fi
OPENWIFI_DIR=$1
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# if [ "$#" -ne 1 ]; then
# echo "You must enter exactly 1 arguments: \$OPENWIFI_DIR"
# exit 1
# fi
OPENWIFI_DIR=$(pwd)/../
set -x

61
user_space/csi_fuzzer.sh Executable file
View File

@ -0,0 +1,61 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2021 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -lt 4 ]; then
echo "You must enter 4 arguments: c1_rot90_en c1_raw(-64 to 63) c2_rot90_en c2_raw(-64 to 63)"
exit 1
fi
c1_rot90_en=$1
c1_raw=$2
c2_rot90_en=$3
c2_raw=$4
if (($c1_rot90_en != 0)) && (($c1_rot90_en != 1)); then
echo "c1_rot90_en must be 0 or 1!"
exit 1
fi
if (($c1_raw < -64)) || (($c1_raw > 63)); then
echo "c1_raw must be -64 to 63!"
exit 1
fi
if (($c2_rot90_en != 0)) && (($c2_rot90_en != 1)); then
echo "c2_rot90_en must be 0 or 1!"
exit 1
fi
if (($c2_raw < -64)) || (($c2_raw > 63)); then
echo "c2_raw must be -64 to 63!"
exit 1
fi
if (($c1_raw < 0)); then
unsigned_c1=$(expr 128 + $c1_raw)
# echo $unsigned_c1
else
unsigned_c1=$c1_raw
fi
if (($c2_raw < 0)); then
unsigned_c2=$(expr 128 + $c2_raw)
# echo $unsigned_c2
else
unsigned_c2=$c2_raw
fi
# echo $c1_rot90_en
# echo $unsigned_c1
# echo $c2_rot90_en
# echo $unsigned_c2
unsigned_dec_combined=$(($unsigned_c1 + 512 * $c1_rot90_en + 1024 * $unsigned_c2 + 524288 * $c2_rot90_en))
# echo $unsigned_dec_combined
echo "./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined"
./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined

110
user_space/csi_fuzzer_scan.sh Executable file
View File

@ -0,0 +1,110 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2021 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -lt 1 ]; then
echo "You must enter 1 arguments: 1, 2, 3 or 4. For scan c1, c2, c2&c1 or c1&c2,"
exit 1
fi
SCAN_OPTION=$1
if (($SCAN_OPTION == 1)); then
echo "Scan tap1:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 0 0
sleep 0.01
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 0 0
sleep 0.01
done
done
exit 1
fi
if (($SCAN_OPTION == 2)); then
echo "Scan tap2:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 0 0 $i
sleep 0.01
done
for i in {-64..63};
do
./csi_fuzzer.sh 0 0 1 $i
sleep 0.01
done
done
exit 1
fi
if (($SCAN_OPTION == 3)); then
echo "Scan tap1 after tap2:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $j 0 $i
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 0 $j 1 $i
# sleep 0.1
done
done
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 1 $j 0 $i
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $j 1 $i
# sleep 0.1
done
done
exit 1
fi
if (($SCAN_OPTION == 4)); then
echo "Scan tap2 after tap1:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 0 $j
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 0 $j
# sleep 0.1
done
done
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 1 $j
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 1 $j
# sleep 0.1
done
done
exit 1
fi

4
user_space/fosdem-11ag.sh
View File

@ -1,5 +1,9 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
killall hostapd
killall webfsd

4
user_space/fosdem.sh
View File

@ -1,5 +1,9 @@
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
killall hostapd
killall webfsd

28
user_space/get_fpga.sh
View File

@ -1,28 +0,0 @@
#!/bin/bash
if [ "$#" -ne 1 ]; then
echo "You must enter the \$OPENWIFI_DIR (the openwifi root directory) as argument"
exit 1
fi
OPENWIFI_DIR=$1
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
echo "\$OPENWIFI_DIR is not correct. Please check!"
exit 1
fi
home_dir=$(pwd)
set -ex
cd $OPENWIFI_DIR/
git submodule init openwifi-hw
git submodule update openwifi-hw
cd openwifi-hw
git checkout master
git pull
cd $home_dir

4
user_space/inject_80211/analyze_80211.c
View File

@ -1,5 +1,7 @@
// (c)2020 Michael Tetemke Mehari <michael.mehari@ugent.be>
// Author: Michael Mehari
// SPDX-FileCopyrightText: 2020 UGent
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This program is free software; you can redistribute it and/or modify

18
user_space/inject_80211/inject_80211.c
View File

@ -1,5 +1,7 @@
// (c)2007 Andy Green <andy@warmcat.com>
// (r)2020 Michael Tetemke Mehari <michael.mehari@ugent.be>
// Modified by: Michael Mehari
// SPDX-FileCopyrightText: 2020 UGent
// SPDX-FileCopyrightText: 2007 Andy Green <andy@warmcat.com>
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This program is free software; you can redistribute it and/or modify
@ -58,11 +60,11 @@ static const u8 u8aRadiotapHeader[] =
/* IEEE80211 header */
static const u8 ieee_hdr[] =
{
0x08, 0x01, 0x00, 0x00,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
0x10, 0x86,
0x08, 0x01, 0x00, 0x00, // FC 0x0801. 0--subtype; 8--type&version; 01--toDS1 fromDS0 (data packet to DS)
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP
0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Source address (STA)
0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Destination address (another STA under the same AP)
0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number
};
// Generate random string
@ -117,7 +119,7 @@ void usage(void)
int main(int argc, char *argv[])
{
u8 buffer[1536];
char szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1536], hw_mode = 'n';
char szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1484], hw_mode = 'n';
int i, nLinkEncap = 0, r, rate_index = 0, sgi_flag = 0, num_packets = 10, payload_size = 64, packet_size, nDelay = 100000;
pcap_t *ppcap = NULL;

6
user_space/inject_80211/inject_80211.h
View File

@ -1,3 +1,9 @@
/*
* Author: Michael Mehari
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include <stdlib.h>
#include <resolv.h>
#include <string.h>

4
user_space/inject_80211/inject_80211.sh
View File

@ -1,5 +1,9 @@
#!/bin/bash
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
HW_MODE='n'
COUNT=100
DELAY=1000

2
user_space/inject_80211/radiotap.c
View File

@ -107,7 +107,7 @@ int ieee80211_radiotap_iterator_init(
* present fields. @this_arg can be changed by the caller (eg,
* incremented to move inside a compound argument like
* IEEE80211_RADIOTAP_CHANNEL). The args pointed to are in
* little-endian format whatever the endianess of your CPU.
* little-endian format whatever the endianness of your CPU.
*/
int ieee80211_radiotap_iterator_next(

4
user_space/link_perf_test.sh
View File

@ -1,5 +1,9 @@
#!/bin/bash
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
PL_MIN=100
PL_INC=100
PL_MAX=1500

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