diff --git a/.github/ISSUE_TEMPLATE/issue-description.md b/.github/ISSUE_TEMPLATE/issue-description.md new file mode 100644 index 0000000..1608861 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/issue-description.md @@ -0,0 +1,28 @@ +--- +name: Issue description +about: Please report issue by this template +title: '' +labels: '' +assignees: '' + +--- + +0. Could you send email to xianjun.jiao@ugent.be to introduce your self? + +1. Our image is used directly or you build your own image? + +2. What is your own modification? + +3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision + +4. Board/hardware type + +5. WiFi channel number + +6. Steps to reproduce the issue, and the related error message, screenshot, etc + +7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts" + +8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods + +9. Any other thing we need to know for helping you better? diff --git a/.gitmodules b/.gitmodules index 0d6fc15..42cab05 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,6 +4,3 @@ [submodule "adi-linux-64"] path = adi-linux-64 url = https://github.com/analogdevicesinc/linux.git -[submodule "openwifi-hw"] - path = openwifi-hw - url = https://github.com/open-sdr/openwifi-hw.git diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 94f49cb..b54a75f 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,3 +1,9 @@ + + CLA([Individual](https://users.ugent.be/~xjiao/openwifi-Individual.pdf), [Entity](https://users.ugent.be/~xjiao/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing. CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html). diff --git a/LICENSE b/LICENSE index 4ac29ae..dba13ed 100644 --- a/LICENSE +++ b/LICENSE @@ -659,39 +659,3 @@ specific requirements. if any, to sign a "copyright disclaimer" for the program, if necessary. For more information on this, and how to apply and follow the GNU AGPL, see . - - -The license terms used for the scard class (in pcsc_usim) derived from wpa_supplicant -------------------------------------------------------------------------------------- - -Modified BSD license (no advertisement clause): - -Copyright (c) 2002-2017, Jouni Malinen and contributors -All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met: - -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name(s) of the above-listed copyright holder(s) nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/LICENSES/AGPL-3.0-or-later.txt b/LICENSES/AGPL-3.0-or-later.txt new file mode 100644 index 0000000..dba13ed --- /dev/null +++ b/LICENSES/AGPL-3.0-or-later.txt @@ -0,0 +1,661 @@ + GNU AFFERO GENERAL PUBLIC LICENSE + Version 3, 19 November 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU Affero General Public License is a free, copyleft license for +software and other kinds of works, specifically designed to ensure +cooperation with the community in the case of network server software. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +our General Public Licenses are intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + Developers that use our General Public Licenses protect your rights +with two steps: (1) assert copyright on the software, and (2) offer +you this License which gives you legal permission to copy, distribute +and/or modify the software. + + A secondary benefit of defending all users' freedom is that +improvements made in alternate versions of the program, if they +receive widespread use, become available for other developers to +incorporate. Many developers of free software are heartened and +encouraged by the resulting cooperation. However, in the case of +software used on network servers, this result may fail to come about. +The GNU General Public License permits making a modified version and +letting the public access it on a server without ever releasing its +source code to the public. + + The GNU Affero General Public License is designed specifically to +ensure that, in such cases, the modified source code becomes available +to the community. It requires the operator of a network server to +provide the source code of the modified version running there to the +users of that server. Therefore, public use of a modified version, on +a publicly accessible server, gives the public access to the source +code of the modified version. + + An older license, called the Affero General Public License and +published by Affero, was designed to accomplish similar goals. This is +a different license, not a version of the Affero GPL, but Affero has +released a new version of the Affero GPL which permits relicensing under +this license. + + The precise terms and conditions for copying, distribution and +modification follow. + + TERMS AND CONDITIONS + + 0. Definitions. + + "This License" refers to version 3 of the GNU Affero General Public License. + + "Copyright" also means copyright-like laws that apply to other kinds of +works, such as semiconductor masks. + + "The Program" refers to any copyrightable work licensed under this +License. Each licensee is addressed as "you". "Licensees" and +"recipients" may be individuals or organizations. + + To "modify" a work means to copy from or adapt all or part of the work +in a fashion requiring copyright permission, other than the making of an +exact copy. The resulting work is called a "modified version" of the +earlier work or a work "based on" the earlier work. + + A "covered work" means either the unmodified Program or a work based +on the Program. + + To "propagate" a work means to do anything with it that, without +permission, would make you directly or secondarily liable for +infringement under applicable copyright law, except executing it on a +computer or modifying a private copy. Propagation includes copying, +distribution (with or without modification), making available to the +public, and in some countries other activities as well. + + To "convey" a work means any kind of propagation that enables other +parties to make or receive copies. Mere interaction with a user through +a computer network, with no transfer of a copy, is not conveying. + + An interactive user interface displays "Appropriate Legal Notices" +to the extent that it includes a convenient and prominently visible +feature that (1) displays an appropriate copyright notice, and (2) +tells the user that there is no warranty for the work (except to the +extent that warranties are provided), that licensees may convey the +work under this License, and how to view a copy of this License. If +the interface presents a list of user commands or options, such as a +menu, a prominent item in the list meets this criterion. + + 1. Source Code. + + The "source code" for a work means the preferred form of the work +for making modifications to it. "Object code" means any non-source +form of a work. + + A "Standard Interface" means an interface that either is an official +standard defined by a recognized standards body, or, in the case of +interfaces specified for a particular programming language, one that +is widely used among developers working in that language. + + The "System Libraries" of an executable work include anything, other +than the work as a whole, that (a) is included in the normal form of +packaging a Major Component, but which is not part of that Major +Component, and (b) serves only to enable use of the work with that +Major Component, or to implement a Standard Interface for which an +implementation is available to the public in source code form. A +"Major Component", in this context, means a major essential component +(kernel, window system, and so on) of the specific operating system +(if any) on which the executable work runs, or a compiler used to +produce the work, or an object code interpreter used to run it. + + The "Corresponding Source" for a work in object code form means all +the source code needed to generate, install, and (for an executable +work) run the object code and to modify the work, including scripts to +control those activities. However, it does not include the work's +System Libraries, or general-purpose tools or generally available free +programs which are used unmodified in performing those activities but +which are not part of the work. For example, Corresponding Source +includes interface definition files associated with source files for +the work, and the source code for shared libraries and dynamically +linked subprograms that the work is specifically designed to require, +such as by intimate data communication or control flow between those +subprograms and other parts of the work. + + The Corresponding Source need not include anything that users +can regenerate automatically from other parts of the Corresponding +Source. + + The Corresponding Source for a work in source code form is that +same work. + + 2. Basic Permissions. + + All rights granted under this License are granted for the term of +copyright on the Program, and are irrevocable provided the stated +conditions are met. This License explicitly affirms your unlimited +permission to run the unmodified Program. The output from running a +covered work is covered by this License only if the output, given its +content, constitutes a covered work. This License acknowledges your +rights of fair use or other equivalent, as provided by copyright law. + + You may make, run and propagate covered works that you do not +convey, without conditions so long as your license otherwise remains +in force. You may convey covered works to others for the sole purpose +of having them make modifications exclusively for you, or provide you +with facilities for running those works, provided that you comply with +the terms of this License in conveying all material for which you do +not control copyright. Those thus making or running the covered works +for you must do so exclusively on your behalf, under your direction +and control, on terms that prohibit them from making any copies of +your copyrighted material outside their relationship with you. + + Conveying under any other circumstances is permitted solely under +the conditions stated below. Sublicensing is not allowed; section 10 +makes it unnecessary. + + 3. Protecting Users' Legal Rights From Anti-Circumvention Law. + + No covered work shall be deemed part of an effective technological +measure under any applicable law fulfilling obligations under article +11 of the WIPO copyright treaty adopted on 20 December 1996, or +similar laws prohibiting or restricting circumvention of such +measures. + + When you convey a covered work, you waive any legal power to forbid +circumvention of technological measures to the extent such circumvention +is effected by exercising rights under this License with respect to +the covered work, and you disclaim any intention to limit operation or +modification of the work as a means of enforcing, against the work's +users, your or third parties' legal rights to forbid circumvention of +technological measures. + + 4. Conveying Verbatim Copies. + + You may convey verbatim copies of the Program's source code as you +receive it, in any medium, provided that you conspicuously and +appropriately publish on each copy an appropriate copyright notice; +keep intact all notices stating that this License and any +non-permissive terms added in accord with section 7 apply to the code; +keep intact all notices of the absence of any warranty; and give all +recipients a copy of this License along with the Program. + + You may charge any price or no price for each copy that you convey, +and you may offer support or warranty protection for a fee. + + 5. Conveying Modified Source Versions. + + You may convey a work based on the Program, or the modifications to +produce it from the Program, in the form of source code under the +terms of section 4, provided that you also meet all of these conditions: + + a) The work must carry prominent notices stating that you modified + it, and giving a relevant date. + + b) The work must carry prominent notices stating that it is + released under this License and any conditions added under section + 7. This requirement modifies the requirement in section 4 to + "keep intact all notices". + + c) You must license the entire work, as a whole, under this + License to anyone who comes into possession of a copy. This + License will therefore apply, along with any applicable section 7 + additional terms, to the whole of the work, and all its parts, + regardless of how they are packaged. This License gives no + permission to license the work in any other way, but it does not + invalidate such permission if you have separately received it. + + d) If the work has interactive user interfaces, each must display + Appropriate Legal Notices; however, if the Program has interactive + interfaces that do not display Appropriate Legal Notices, your + work need not make them do so. + + A compilation of a covered work with other separate and independent +works, which are not by their nature extensions of the covered work, +and which are not combined with it such as to form a larger program, +in or on a volume of a storage or distribution medium, is called an +"aggregate" if the compilation and its resulting copyright are not +used to limit the access or legal rights of the compilation's users +beyond what the individual works permit. Inclusion of a covered work +in an aggregate does not cause this License to apply to the other +parts of the aggregate. + + 6. Conveying Non-Source Forms. + + You may convey a covered work in object code form under the terms +of sections 4 and 5, provided that you also convey the +machine-readable Corresponding Source under the terms of this License, +in one of these ways: + + a) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by the + Corresponding Source fixed on a durable physical medium + customarily used for software interchange. + + b) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by a + written offer, valid for at least three years and valid for as + long as you offer spare parts or customer support for that product + model, to give anyone who possesses the object code either (1) a + copy of the Corresponding Source for all the software in the + product that is covered by this License, on a durable physical + medium customarily used for software interchange, for a price no + more than your reasonable cost of physically performing this + conveying of source, or (2) access to copy the + Corresponding Source from a network server at no charge. + + c) Convey individual copies of the object code with a copy of the + written offer to provide the Corresponding Source. This + alternative is allowed only occasionally and noncommercially, and + only if you received the object code with such an offer, in accord + with subsection 6b. + + d) Convey the object code by offering access from a designated + place (gratis or for a charge), and offer equivalent access to the + Corresponding Source in the same way through the same place at no + further charge. You need not require recipients to copy the + Corresponding Source along with the object code. If the place to + copy the object code is a network server, the Corresponding Source + may be on a different server (operated by you or a third party) + that supports equivalent copying facilities, provided you maintain + clear directions next to the object code saying where to find the + Corresponding Source. Regardless of what server hosts the + Corresponding Source, you remain obligated to ensure that it is + available for as long as needed to satisfy these requirements. + + e) Convey the object code using peer-to-peer transmission, provided + you inform other peers where the object code and Corresponding + Source of the work are being offered to the general public at no + charge under subsection 6d. + + A separable portion of the object code, whose source code is excluded +from the Corresponding Source as a System Library, need not be +included in conveying the object code work. + + A "User Product" is either (1) a "consumer product", which means any +tangible personal property which is normally used for personal, family, +or household purposes, or (2) anything designed or sold for incorporation +into a dwelling. In determining whether a product is a consumer product, +doubtful cases shall be resolved in favor of coverage. For a particular +product received by a particular user, "normally used" refers to a +typical or common use of that class of product, regardless of the status +of the particular user or of the way in which the particular user +actually uses, or expects or is expected to use, the product. A product +is a consumer product regardless of whether the product has substantial +commercial, industrial or non-consumer uses, unless such uses represent +the only significant mode of use of the product. + + "Installation Information" for a User Product means any methods, +procedures, authorization keys, or other information required to install +and execute modified versions of a covered work in that User Product from +a modified version of its Corresponding Source. The information must +suffice to ensure that the continued functioning of the modified object +code is in no case prevented or interfered with solely because +modification has been made. + + If you convey an object code work under this section in, or with, or +specifically for use in, a User Product, and the conveying occurs as +part of a transaction in which the right of possession and use of the +User Product is transferred to the recipient in perpetuity or for a +fixed term (regardless of how the transaction is characterized), the +Corresponding Source conveyed under this section must be accompanied +by the Installation Information. But this requirement does not apply +if neither you nor any third party retains the ability to install +modified object code on the User Product (for example, the work has +been installed in ROM). + + The requirement to provide Installation Information does not include a +requirement to continue to provide support service, warranty, or updates +for a work that has been modified or installed by the recipient, or for +the User Product in which it has been modified or installed. Access to a +network may be denied when the modification itself materially and +adversely affects the operation of the network or violates the rules and +protocols for communication across the network. + + Corresponding Source conveyed, and Installation Information provided, +in accord with this section must be in a format that is publicly +documented (and with an implementation available to the public in +source code form), and must require no special password or key for +unpacking, reading or copying. + + 7. Additional Terms. + + "Additional permissions" are terms that supplement the terms of this +License by making exceptions from one or more of its conditions. +Additional permissions that are applicable to the entire Program shall +be treated as though they were included in this License, to the extent +that they are valid under applicable law. If additional permissions +apply only to part of the Program, that part may be used separately +under those permissions, but the entire Program remains governed by +this License without regard to the additional permissions. + + When you convey a copy of a covered work, you may at your option +remove any additional permissions from that copy, or from any part of +it. (Additional permissions may be written to require their own +removal in certain cases when you modify the work.) You may place +additional permissions on material, added by you to a covered work, +for which you have or can give appropriate copyright permission. + + Notwithstanding any other provision of this License, for material you +add to a covered work, you may (if authorized by the copyright holders of +that material) supplement the terms of this License with terms: + + a) Disclaiming warranty or limiting liability differently from the + terms of sections 15 and 16 of this License; or + + b) Requiring preservation of specified reasonable legal notices or + author attributions in that material or in the Appropriate Legal + Notices displayed by works containing it; or + + c) Prohibiting misrepresentation of the origin of that material, or + requiring that modified versions of such material be marked in + reasonable ways as different from the original version; or + + d) Limiting the use for publicity purposes of names of licensors or + authors of the material; or + + e) Declining to grant rights under trademark law for use of some + trade names, trademarks, or service marks; or + + f) Requiring indemnification of licensors and authors of that + material by anyone who conveys the material (or modified versions of + it) with contractual assumptions of liability to the recipient, for + any liability that these contractual assumptions directly impose on + those licensors and authors. + + All other non-permissive additional terms are considered "further +restrictions" within the meaning of section 10. If the Program as you +received it, or any part of it, contains a notice stating that it is +governed by this License along with a term that is a further +restriction, you may remove that term. If a license document contains +a further restriction but permits relicensing or conveying under this +License, you may add to a covered work material governed by the terms +of that license document, provided that the further restriction does +not survive such relicensing or conveying. + + If you add terms to a covered work in accord with this section, you +must place, in the relevant source files, a statement of the +additional terms that apply to those files, or a notice indicating +where to find the applicable terms. + + Additional terms, permissive or non-permissive, may be stated in the +form of a separately written license, or stated as exceptions; +the above requirements apply either way. + + 8. Termination. + + You may not propagate or modify a covered work except as expressly +provided under this License. Any attempt otherwise to propagate or +modify it is void, and will automatically terminate your rights under +this License (including any patent licenses granted under the third +paragraph of section 11). + + However, if you cease all violation of this License, then your +license from a particular copyright holder is reinstated (a) +provisionally, unless and until the copyright holder explicitly and +finally terminates your license, and (b) permanently, if the copyright +holder fails to notify you of the violation by some reasonable means +prior to 60 days after the cessation. + + Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. + + Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, you do not qualify to receive new licenses for the same +material under section 10. + + 9. Acceptance Not Required for Having Copies. + + You are not required to accept this License in order to receive or +run a copy of the Program. Ancillary propagation of a covered work +occurring solely as a consequence of using peer-to-peer transmission +to receive a copy likewise does not require acceptance. However, +nothing other than this License grants you permission to propagate or +modify any covered work. These actions infringe copyright if you do +not accept this License. Therefore, by modifying or propagating a +covered work, you indicate your acceptance of this License to do so. + + 10. Automatic Licensing of Downstream Recipients. + + Each time you convey a covered work, the recipient automatically +receives a license from the original licensors, to run, modify and +propagate that work, subject to this License. You are not responsible +for enforcing compliance by third parties with this License. + + An "entity transaction" is a transaction transferring control of an +organization, or substantially all assets of one, or subdividing an +organization, or merging organizations. If propagation of a covered +work results from an entity transaction, each party to that +transaction who receives a copy of the work also receives whatever +licenses to the work the party's predecessor in interest had or could +give under the previous paragraph, plus a right to possession of the +Corresponding Source of the work from the predecessor in interest, if +the predecessor has it or can get it with reasonable efforts. + + You may not impose any further restrictions on the exercise of the +rights granted or affirmed under this License. For example, you may +not impose a license fee, royalty, or other charge for exercise of +rights granted under this License, and you may not initiate litigation +(including a cross-claim or counterclaim in a lawsuit) alleging that +any patent claim is infringed by making, using, selling, offering for +sale, or importing the Program or any portion of it. + + 11. Patents. + + A "contributor" is a copyright holder who authorizes use under this +License of the Program or a work on which the Program is based. The +work thus licensed is called the contributor's "contributor version". + + A contributor's "essential patent claims" are all patent claims +owned or controlled by the contributor, whether already acquired or +hereafter acquired, that would be infringed by some manner, permitted +by this License, of making, using, or selling its contributor version, +but do not include claims that would be infringed only as a +consequence of further modification of the contributor version. For +purposes of this definition, "control" includes the right to grant +patent sublicenses in a manner consistent with the requirements of +this License. + + Each contributor grants you a non-exclusive, worldwide, royalty-free +patent license under the contributor's essential patent claims, to +make, use, sell, offer for sale, import and otherwise run, modify and +propagate the contents of its contributor version. + + In the following three paragraphs, a "patent license" is any express +agreement or commitment, however denominated, not to enforce a patent +(such as an express permission to practice a patent or covenant not to +sue for patent infringement). To "grant" such a patent license to a +party means to make such an agreement or commitment not to enforce a +patent against the party. + + If you convey a covered work, knowingly relying on a patent license, +and the Corresponding Source of the work is not available for anyone +to copy, free of charge and under the terms of this License, through a +publicly available network server or other readily accessible means, +then you must either (1) cause the Corresponding Source to be so +available, or (2) arrange to deprive yourself of the benefit of the +patent license for this particular work, or (3) arrange, in a manner +consistent with the requirements of this License, to extend the patent +license to downstream recipients. "Knowingly relying" means you have +actual knowledge that, but for the patent license, your conveying the +covered work in a country, or your recipient's use of the covered work +in a country, would infringe one or more identifiable patents in that +country that you have reason to believe are valid. + + If, pursuant to or in connection with a single transaction or +arrangement, you convey, or propagate by procuring conveyance of, a +covered work, and grant a patent license to some of the parties +receiving the covered work authorizing them to use, propagate, modify +or convey a specific copy of the covered work, then the patent license +you grant is automatically extended to all recipients of the covered +work and works based on it. + + A patent license is "discriminatory" if it does not include within +the scope of its coverage, prohibits the exercise of, or is +conditioned on the non-exercise of one or more of the rights that are +specifically granted under this License. You may not convey a covered +work if you are a party to an arrangement with a third party that is +in the business of distributing software, under which you make payment +to the third party based on the extent of your activity of conveying +the work, and under which the third party grants, to any of the +parties who would receive the covered work from you, a discriminatory +patent license (a) in connection with copies of the covered work +conveyed by you (or copies made from those copies), or (b) primarily +for and in connection with specific products or compilations that +contain the covered work, unless you entered into that arrangement, +or that patent license was granted, prior to 28 March 2007. + + Nothing in this License shall be construed as excluding or limiting +any implied license or other defenses to infringement that may +otherwise be available to you under applicable patent law. + + 12. No Surrender of Others' Freedom. + + If conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot convey a +covered work so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you may +not convey it at all. For example, if you agree to terms that obligate you +to collect a royalty for further conveying from those to whom you convey +the Program, the only way you could satisfy both those terms and this +License would be to refrain entirely from conveying the Program. + + 13. Remote Network Interaction; Use with the GNU General Public License. + + Notwithstanding any other provision of this License, if you modify the +Program, your modified version must prominently offer all users +interacting with it remotely through a computer network (if your version +supports such interaction) an opportunity to receive the Corresponding +Source of your version by providing access to the Corresponding Source +from a network server at no charge, through some standard or customary +means of facilitating copying of software. This Corresponding Source +shall include the Corresponding Source for any work covered by version 3 +of the GNU General Public License that is incorporated pursuant to the +following paragraph. + + Notwithstanding any other provision of this License, you have +permission to link or combine any covered work with a work licensed +under version 3 of the GNU General Public License into a single +combined work, and to convey the resulting work. The terms of this +License will continue to apply to the part which is the covered work, +but the work with which it is combined will remain governed by version +3 of the GNU General Public License. + + 14. Revised Versions of this License. + + The Free Software Foundation may publish revised and/or new versions of +the GNU Affero General Public License from time to time. Such new versions +will be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + + Each version is given a distinguishing version number. If the +Program specifies that a certain numbered version of the GNU Affero General +Public License "or any later version" applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU Affero General Public License, you may choose any version ever published +by the Free Software Foundation. + + If the Program specifies that a proxy can decide which future +versions of the GNU Affero General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + + Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + + 15. Disclaimer of Warranty. + + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY +APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT +HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY +OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM +IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF +ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF +DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD +PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), +EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF +SUCH DAMAGES. + + 17. Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU Affero General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Affero General Public License for more details. + + You should have received a copy of the GNU Affero General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If your software can interact with users remotely through a computer +network, you should also make sure that it provides a way for users to +get its source. For example, if your program is a web application, its +interface could display a "Source" link that leads users to an archive +of the code. There are many ways you could offer source, and different +solutions will be better for different programs; see section 13 for the +specific requirements. + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU AGPL, see +. diff --git a/LICENSES/BSD-3-Clause.txt b/LICENSES/BSD-3-Clause.txt new file mode 100644 index 0000000..5d9a8a7 --- /dev/null +++ b/LICENSES/BSD-3-Clause.txt @@ -0,0 +1,31 @@ +Modified BSD license (no advertisement clause): + +Copyright (c) 2002-2017, Jouni Malinen and contributors +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name(s) of the above-listed copyright holder(s) nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/LICENSES/GPL-2.0-or-later.txt b/LICENSES/GPL-2.0-or-later.txt new file mode 100644 index 0000000..7210918 --- /dev/null +++ b/LICENSES/GPL-2.0-or-later.txt @@ -0,0 +1,116 @@ + +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + + Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + + You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + 2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. + b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. + c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) + + These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + + Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + + In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) + + The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + + If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + 4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + 5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + 6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + 7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + + If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + + It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + + This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + 8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + + NO WARRANTY + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + + +Copyright (C) + +This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. + +, 1 April 1989 Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. +Standard License Header + + +Copyright (C) + +This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + diff --git a/LICENSES/ISC.txt b/LICENSES/ISC.txt new file mode 100644 index 0000000..51b1ee0 --- /dev/null +++ b/LICENSES/ISC.txt @@ -0,0 +1,5 @@ +Copyright + +Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/README.md b/README.md index 23425cf..6ea134c 100644 --- a/README.md +++ b/README.md @@ -1,15 +1,24 @@ + + # openwifi **openwifi:** Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio). -This repository includes Linux driver and software. [openwifi-hw](https://github.com/open-sdr/openwifi-hw) repository has the FPGA design. +This repository includes Linux driver and software. [openwifi-hw](https://github.com/open-sdr/openwifi-hw) repository has the FPGA design. It is **YOUR RESPONSIBILITY** to follow your **LOCAL SPECTRUM REGULATION** or use **CABLE** to avoid potential interference over the air. -[[Project document](doc)], [[Quick start](#Quick-start)], [[Application notes](doc/app_notes)] +[[Quick start](#Quick-start)] +[[Project document](doc/README.md)] +[[Application notes](doc/app_notes/README.md)] +[[Videos](doc/videos.md)] +[[Publications and How to Cite](doc/publications.md)] +[[maillist](https://lists.ugent.be/wws/subscribe/openwifi)] -[[Videos](#Videos)] [[Papers](#Papers)] [openwifi [maillist](https://lists.ugent.be/wws/subscribe/openwifi)] [[Cite openwifi project](#Cite-openwifi-project)] - -Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opensource license, please contact Filip.Louagie@UGent.be. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md). +Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/blob/master/LICENSE) is the opensource license. For non-opensource and advanced feature license, please contact Filip.Louagie@UGent.be. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md). **Features:** @@ -17,16 +26,18 @@ Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opens - 20MHz bandwidth; 70 MHz to 6 GHz frequency range - Mode tested: Ad-hoc; Station; AP, Monitor - DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved) +- [802.11 packet injection and fuzzing](doc/app_notes/inject_80211.md) +- [CSI](doc/app_notes/csi.md): Channel State Information, freq offset, equalizer to computer +- [CSI fuzzer](doc/app_notes/csi_fuzzer.md): Create artificial channel response in WiFi transmitter +- [[IQ capture](doc/app_notes/iq.md)]: real-time AGC, RSSI, IQ sample to computer. [[Dual antenna version](doc/app_notes/iq_2ant.md)] - Configurable channel access priority parameters: - duration of RTS/CTS, CTS-to-self - SIFS/DIFS/xIFS/slot-time/CW/etc -- Time slicing based on MAC address +- Time slicing based on MAC address (time gated/scheduled FPGA queues) - Easy to change bandwidth and frequency: - 2MHz for 802.11ah in sub-GHz - 10MHz for 802.11p/vehicle in 5.9GHz -- CSI (Channel State Information, freq offset, equalizer to computer) [[CSI notes](doc/app_notes/csi.md)] -- IQ capture (real-time AGC, RSSI, IQ sample to computer) [[IQ notes](doc/app_notes/iq.md)][[IQ notes for dual antenna](doc/app_notes/iq_2ant.md)] -- On roadmap: **802.11ax** +- **802.11ax** under development **Performance (AP: openwifi at channel 44, client: TL-WDN4200 N900 USB Dongle):** - AP --> client: 30.6Mbps(TCP), 38.8Mbps(UDP) @@ -34,15 +45,16 @@ Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opens **Supported SDR platforms:** (Check [Porting guide](#Porting-guide) for your new board if it isn't in the list) -board_name|board combination|status|SD card img --------|-------|----|---- -zc706_fmcs2|Xilinx ZC706 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz) -zed_fmcs2|Xilinx zed board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz) -adrv9364z7020|ADRV9364-Z7020 + ADRV1CRR-BOB|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz) -adrv9361z7035|ADRV9361-Z7035 + ADRV1CRR-BOB/FMC|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz) -zc702_fmcs2|Xilinx ZC702 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-32bit.img.xz) -zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-6-64bit.img.xz) -zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future +board_name|board combination|status|SD card img|Vivado license +-------|-------|----|----|----- +zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|Need +zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need +adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need +adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|Need +zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need +antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.2.1-leuven-2-32bit.img.xz)|**NO** need +zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.2.0-leuven-2-64bit.img.xz)|Need +zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need - board_name is used to identify FPGA design in openwifi-hw/boards/ - Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial. @@ -57,14 +69,13 @@ zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] [[Special note for 11b](#Special-note-for-11b)] [[Porting guide](#Porting-guide)] - -[[Project document](doc)] -[[Application notes](doc/app_notes)] +[[Project document](doc/README.md)] +[[Application notes](doc/app_notes/README.md)] ## Quick start - Burn openwifi board specific img file (from the table) into a SD card ("Open With Disk Image Writer". Or "dd" command after unzip). The SD card has two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: - - Copy files in **openwifi/board_name** to the base directory of BOOT partiton. - - Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partiton + - Copy files in **openwifi/board_name** to the base directory of BOOT partition. + - Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partition - Connect two antennas to RXA/TXA ports. Config the board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on. - Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**. ``` @@ -72,18 +83,19 @@ zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|Future ``` - On board, run openwifi AP and the on board webserver ``` - ~/openwifi/fosdem.sh + ~/openwifi/fosdem-11ag.sh ``` -- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your deivce, you should see the webpage hosted by the webserver on board. + **NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!! +- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board. - Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh. - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts) -- To give the Wi-Fii client internet access, configure routing/NAT **on the PC**: +- To give the Wi-Fi client internet access, configure routing/NAT **on the PC**: ``` sudo sysctl -w net.ipv4.ip_forward=1 - sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE + sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX ``` - **ethX** is the PC NIC name connecting the board. **ethY** is the PC NIC name connecting internet. + **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet). If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC. - To monitor **real-time CSI (Chip State Information)**, such as timestamp, frequency offset, channel state, equalizer, please refer to [[CSI notes](doc/app_notes/csi.md)]. @@ -108,26 +120,25 @@ The board actually is an Linux/Ubuntu computer which is running **hostapd** to o ## Update FPGA -Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to udpate the fpga bitstream on board. +Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the fpga bitstream on board. - Install Vivado/SDK 2018.3 (If you don't need to generate new FPGA bitstream, WebPack version without license is enough) - Setup environment variables (use absolute path): ``` export XILINX_DIR=your_Xilinx_directory - export OPENWIFI_DIR=your_openwifi_directory + export OPENWIFI_HW_DIR=your_openwifi-hw_directory export BOARD_NAME=your_board_name ``` -- Get the latest FPGA bitstream from openwifi-hw, generate BOOT.BIN and transfer it on board via ssh channel: +- Pick the FPGA bitstream from openwifi-hw, and generate BOOT.BIN and transfer it on board via ssh channel: ``` - $OPENWIFI_DIR/user_space/get_fpga.sh $OPENWIFI_DIR - For Zynq 7000: - $OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME + + cd openwifi/user_space; ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME For Zynq MPSoC (like zcu102 board): - $OPENWIFI_DIR/user_space/boot_bin_gen_zynqmp.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME + cd openwifi/user_space; ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME - scp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN root@192.168.10.122: + cd openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin; scp ./BOOT.BIN root@192.168.10.122: ``` - On board: Put the BOOT.BIN into the BOOT partition. ``` @@ -139,27 +150,29 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i ## Update Driver -Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to udpate the driver on board. +Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the driver on board. - Prepare Analog Devices Linux kernel source code (only need to run once): ``` - $OPENWIFI_DIR/user_space/prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT + cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT build (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64) ``` + **Note**: In Ubuntu, gcc-10 might have issue ('yylloc' error), so use gcc-9 if you encounter error. - Compile the latest openwifi driver ``` - $OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT + cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64) ``` - Copy the driver files to the board via ssh channel ``` - scp `find $OPENWIFI_DIR/driver/ -name \*.ko` root@192.168.10.122:openwifi/ + cd openwifi/driver; scp `find ./ -name \*.ko` root@192.168.10.122:openwifi/ ``` Now you can use **wgd.sh** on board to load the new openwifi driver. + **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need to follow [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to generate your new SD card image. ## Update sdrctl - Copy the sdrctl source files to the board via ssh channel ``` - scp `find $OPENWIFI_DIR/user_space/sdrctl_src/ -name \*` root@192.168.10.122:openwifi/sdrctl_src/ + cd openwifi/user_space/sdrctl_src; scp `find ./ -name \*` root@192.168.10.122:openwifi/sdrctl_src/ ``` - Compile the sdrctl **on board**: ``` @@ -168,7 +181,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i ## Easy Access and etc - FPGA and driver on board update scripts - - Setup [ftp server](https://help.ubuntu.com/lts/serverguide/ftp-server.html) on PC, allow anonymous and change ftp root directory to $OPENWIFI_DIR. + - Setup [ftp server](https://help.ubuntu.com/lts/serverguide/ftp-server.html) on PC, allow anonymous and change ftp root directory to the openwifi directory. - On board: ``` ./sdcard_boot_update.sh $BOARD_NAME @@ -186,12 +199,12 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i ``` export SDCARD_DIR=sdcard_mount_point export XILINX_DIR=your_Xilinx_directory - export OPENWIFI_DIR=your_openwifi_directory + export OPENWIFI_HW_DIR=your_openwifi-hw_directory export BOARD_NAME=your_board_name ``` - Run script to update SD card: ``` - $OPENWIFI_DIR/user_space/update_sdcard.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR + cd openwifi/user_space; ./update_sdcard.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR ``` - Config your board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on. - Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with one time password **analog**. @@ -201,10 +214,10 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i - Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config. ``` sudo sysctl -w net.ipv4.ip_forward=1 - sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE + sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX ``` - **ethX** is the PC NIC name connecting the board. **ethY** is the PC NIC name connecting internet. + **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet). If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC. - Run **one time** script on board to complete post installation/config (After this, password becomes **openwifi**) @@ -224,43 +237,18 @@ For hostapd program, 802.11b rates can be suppressed using configuration command On the other hand, the wpa_supplicant program on the client side (commercial Wi-Fi dongle/board) cannot suppress 802.11b rates out of the box in 2.4GHz band, so there will be an issue when connecting openwifi (OFDM only). A patched wpa_supplicant should be used at the client side. ``` sudo apt-get install libssl1.0-dev -$OPENWIFI_DIR/user_space/build_wpa_supplicant_wo11b.sh $OPENWIFI_DIR +cd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh ``` ## Porting guide -This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 4fea7c5 (2019 r1) of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl). +This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2019_R1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl). - Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help) - Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository) - "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor". -- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached deivce (FPGA blocks in our case). +- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case). - We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design. - Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN and Linux kernel uImage and put them together to build the full SD card image. -## Videos +## License -Demo [[youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)] - -FOSDEM2020 [[youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)] - -Low latency for gaming and introduction [[youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)] - -CSI (Channel State Information) [[twitter](https://twitter.com/i/status/1314207380561780738)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)] - -## Papers - -- [openwifi: a free and open-source IEEE802.11 SDR implementation on SoC](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf) -- [csi murder](https://ans.unibs.it/projects/csi-murder/) - -Openwifi was born in [ORCA project](https://www.orca-project.eu/) (EU's Horizon2020 programme under agreement number 732174). - -## Cite openwifi project - -Any use of openwifi project which results in a publication should include a citation via (bibtex example): -``` -@electronic{openwifigithub, - author = {Xianjun, Jiao and Wei, Liu and Michael, Mehari}, - title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design}, - url = {https://github.com/open-sdr/openwifi}, - year = {2019}, -} -``` +This project is available as open source under the terms of the AGPL 3.0 Or later. However, some elements are being licensed under GPL 2-0 or later and BSD 3 license . For accurate information, please check individual files. diff --git a/adi-linux b/adi-linux index 4fea7c5..b6e3799 160000 --- a/adi-linux +++ b/adi-linux @@ -1 +1 @@ -Subproject commit 4fea7c58ad92283acb90f182821b51d72b6afefa +Subproject commit b6e379910a11af77e6500ed8b0895006e471a279 diff --git a/adi-linux-64 b/adi-linux-64 index 4fea7c5..b6e3799 160000 --- a/adi-linux-64 +++ b/adi-linux-64 @@ -1 +1 @@ -Subproject commit 4fea7c58ad92283acb90f182821b51d72b6afefa +Subproject commit b6e379910a11af77e6500ed8b0895006e471a279 diff --git a/doc/README.md b/doc/README.md index 183c258..04630e3 100644 --- a/doc/README.md +++ b/doc/README.md @@ -1,3 +1,10 @@ + + + # Openwifi document @@ -10,7 +17,7 @@ Above figure shows software and hardware/FPGA modules that compose the openwifi - [Regulation and channel config](#Regulation-and-channel-config) - [Analog and digital frequency design](#Analog-and-digital-frequency-design) - [Debug methods](#Debug-methods) -- [Application notes](app_notes) +- [Application notes](app_notes/README.md) ## Driver and software overall principle @@ -53,7 +60,7 @@ sdrctl dev sdr0 set para_name value ``` para_name|meaning|comment ---------|-------|---- -slice_idx|the slice that will be set/get|0~3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwize the start/end of different slices have different actual time +slice_idx|the slice that will be set/get|0 to 3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwise the start/end of different slices have different actual time addr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1 slice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999 slice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000 @@ -65,11 +72,13 @@ tsf| sets TSF value| it requires two values "high_TSF low_TSF". Decimal sdrctl dev sdr0 get reg module_name reg_idx sdrctl dev sdr0 set reg module_name reg_idx reg_value ``` -module_name refers to the name of driver functionality, can be drv_rx/drv_tx/drv_xpu. Related registers are defined in sdr.h (drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val) +module_name drv_rx/drv_tx/drv_xpu refers to the corresponding driver functionality. Related registers are defined in sdr.h. Search drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val in sdr.c to see their functionalities. -module_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h. +module_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h and mapped to slv_regX in .v file (X is the register index). Check rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu.c and .v files to see their functionalities. -module_name: **drv_rx** +Please be aware that some registers are set by sdr.c in real-time (instructed by Linux mac80211), so be careful when set them manually. + +module_name: **drv_rx** (for full list, search drv_rx_reg_val in sdr.c) reg_idx|meaning|comment -------|-------|---- @@ -78,7 +87,7 @@ reg_idx|meaning|comment (In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command) -module_name: **drv_tx** +module_name: **drv_tx** (for full list, search drv_tx_reg_val in sdr.c) reg_idx|meaning|comment -------|-------|---- @@ -86,11 +95,11 @@ reg_idx|meaning|comment 1|tx antenna selection|0:tx1, 1:tx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh 7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON) -module_name: **drv_xpu** +module_name: **drv_xpu** (for full list, search drv_xpu_reg_val in sdr.c) reg_idx|meaning|comment -------|-------|---- -7|git revision when build the driver|example: return value 0071bc74 means git revision is 071bc74 (the 1st 0 must be removed!) +7|git revision when build the driver|example: return value 0071bc74 means git revision is 071bc74 (the 1st 0 is always 0!) module_name: **rf** @@ -98,58 +107,83 @@ reg_idx|meaning|comment -------|-------|---- x|x|to be defined -module_name: **rx_intf** +module_name: **rx_intf** (for full list, check rx_intf.c and **slv_reg** in rx_intf.v) reg_idx|meaning|comment -------|-------|---- +1|trigger for ILA debug|bit4 and bit0. Please check slv_reg1 in rx_intf.v 2|enable/disable rx interrupt|256(0x100):disable, 0:enable +3|get loopback I/Q from tx_intf|256(0x100):from tx_intf, 0:from ad9361 ADC +11|rx digital I/Q gain|number of bit shift to left. default 4 in rx_intf.c: rx_intf_api->RX_INTF_REG_BB_GAIN_write(4) +13|delay from RX DMA complete to RX packet interrupt|unit 0.1us +16|rx antenna selection|0:ant0, 1:ant1. default 0 in rx_intf.c: rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel) -module_name: **tx_intf** +module_name: **tx_intf** (for full list, check tx_intf.c and **slv_reg** in tx_intf.v) reg_idx|meaning|comment -------|-------|---- +1|DUC config|tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg) in tx_intf.c and openwifi-hw/ip/mixer_duc/src/mixer_duc.cpp +4|CTS to Self config|auto set by cts_reg in openwifi_tx of sdr.c. bit31: enable/disable, bit30: rate selection: 1: use traffic rate, 0: manual rate in bit7-4, bit23-8: duration +6|CTS to Self sending delay (for SIFS)|unit 0.1us. bit13-0 for 2.4GHz, bit29-16 for 5GHz +11|threshold for FPGA fifo almost full|driver(sdr.c) read 1bit flag in slv_reg21 (4bit in total for 4 queue) to know the FPGA fifo/queue is almost full. +12|threshold to pause openofdm_tx|back pressure flow control for I/Q generation speed of openofdm_tx 13|tx I/Q digital gain before DUC|current optimal value: 100 -14|enable/disable tx interrupt|196672(0x30040):disable, 64(0x40):enable +14|enable/disable tx interrupt|196612(0x30004):disable, 4:enable +16|tx antenna selection|1:ant0, 2:ant1. default 1 in tx_intf.c: tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel) +21|queue almost full flag|4bit for 4 queue. criteria is the threshold in slv_reg11. check by tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read() in sdr.c -module_name: **rx** +module_name: **rx** (for full list, check openofdm_rx.c and **slv_reg** in openofdm_rx.v) reg_idx|meaning|comment -------|-------|---- +2|power trigger threshold|default 0. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0) +3|minimum plateau used for short preamble detection|default 100. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100) +4|soft or hard decision for viterbi decoder|0:hard, 1:soft. default 1. openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write(1) 20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working -module_name: **tx** +module_name: **tx** (for full list, check openofdm_tx.c and **slv_reg** in openofdm_tx.v) reg_idx|meaning|comment -------|-------|---- 1|pilot scrambler initial state|lowest 7 bits are used. 0x7E by default in openofdm_tx.c 2|data scrambler initial state|lowest 7 bits are used. 0x7F by default in openofdm_tx.c -module_name: **xpu** +module_name: **xpu** (for full list, check xpu.c and **slv_reg** in xpu.v) reg_idx|meaning|comment -------|-------|---- -1|mute rx I/Q when tx|0:mute (default), 1:unmute, which means rx baseband will receive our own tx signal. Rx packet and tx packet (such as ACK) can be monitored in FPGA for timing analysis -2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 32bit -3|TSF timer high 32bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB -4|band and channel number setting|see enum openwifi_band in hw_def.h. it will be set automatically by Linux. normally you shouldn't set it -11|max number of retransmission in FPGA|normally number of retransmissions controlled by Linux in real-time. If you write non-zeros value to this register, it will override Linux real-time setting -19|CSMA enable/disable|3758096384(0xe0000000): disable, 3:enable +1|mute rx I/Q when tx|0:mute when tx, 1:unmute, which means rx baseband will receive tx signal from its own. Rx packet and tx packet (such as ACK) can be monitored in FPGA for timing analysis +2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 31bit +3|TSF timer high 31bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB +4|band, channel and ERP short slot setting|see enum/define in hw_def.h. set automatically by Linux. manual set will be overrided unless you change sdr.c +5|DIFS and backoff advance (us)|advance (us) for tx preparation before the end of DIFS/backoff. bit7-0:DIFS advance, bit15-8: backoff advance +6|forced idle, CSMA settings|bit7-0: forced channel idle (us) after decoding done to avoid false alarm caused by strong "AGC tail" signal. bit31: NAV enable, bit30: DIFS enable, bit29: EIFS enable, bit28: dynamic CW enable (when disable, CW is taken from bit3-0 of register 19) +7|some RSSI and delay setting|please check xpu.v (search slv_reg7) +8|RSSI threshold for channel idle/busy|set by ad9361_rf_set_channel --> xpu_api->XPU_REG_LBT_TH_write +9|some time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9) +10|BB RF delay setting|bit7-0: BB RF delay (0.1us), bit11-8: RF end extended time (0.1us). check xpu.v (search slv_reg10) +11|ACK control and max num retransmission|bit4: 0:normal ACK, 1:disable auto ACK reply in FPGA. bit3-0: 0: the number of retransmission is decided by Linux, non-zero: Linux auto setting about num of retransmission will be replaced by this value +16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet +17|setting when wait for ACK in 5GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet +18|setting for sending ACK|unit 0.1us. bit14-0: ACK sending delay in 2.4GHz, bit30-16: ACK sending delay in 5GHz +19|CW min and max setting for 4 FPGA queues|bit3-0: CW min for queue 0, bit7-4: CW max for queue 0, bit11-8: CW min for queue 1, bit15-12: CW max for queue 1, bit19-16: CW min for queue 2, bit23-20: CW max for queue 2, bit27-24: CW min for queue 3, bit31-28: CW max for queue 3. automatically set by openwifi_conf_tx of sdr.c +26|CTS to RTS setting|bit15-0: extra duration, bit20-16: rate/MCS, bit31: 0:enable CTStoRTS 1:disable CTStoRTS 27|FPGA packet filter config|check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering) -28|BSSID address low 32bit for BSSID filtering|normally it is set by Linux in real-time automatically -29|BSSID address high 32bit for BSSID filtering|normally it is set by Linux in real-time automatically -30|openwifi MAC address low 32bit| -31|openwifi MAC address high 32bit|check XPU_REG_MAC_ADDR_write in sdr.c to see how we set MAC address to FPGA when NIC start +28|BSSID address low 32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_LOW_write in openwifi_bss_info_changed of sdr.c +29|BSSID address high 32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c +30|MAC address low 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c +31|MAC address high 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c 58|TSF runtime value low 32bit|read only 59|TSF runtime value high 32bit|read only -63|git revision when build the FPGA|example: return value 065272ac means git revision is 65272ac (the 1st 0 must be removed!) +63|git revision when build the FPGA|example: return value 065272ac means git revision is 65272ac (the 1st 0 is always 0) ## Rx packet flow and filtering config -After FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c will be triggered to do necessary operation and give the information to upper layer (Linux mac80211 subsystem). +After FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c serves the interrupt and gives the necessary information to upper layer (Linux mac80211 subsystem) via ieee80211_rx_irqsafe. - frame filtering -The FPGA frame filtering configuration is done in real-time by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is bad. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, openwifi_configure_filter() will set **MONITOR_ALL** to the frame filtering module pkt_filter_ctl.v in FPGA. This makes sure transfer all received packets to Linux mac80211 via rx interrupt. +The FPGA frame filtering configuration is done in real-time by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is bad. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, all received packets (including ACK) will be given to Linux mac80211. - main rx interrupt operations in openwifi_rx_interrupt() - get raw content from DMA buffer. When Linux receives interrupt from FPGA rx_intf module, the content has been ready in Linux DMA buffer @@ -165,16 +199,16 @@ The FPGA frame filtering configuration is done in real-time by function openwifi Linux mac80211 subsystem calls openwifi_tx() to initiate a packet sending. - main operations in openwifi_tx() - - get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration use + - get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration - packet length and MCS - unicast or broadcast? does it need ACK? how many retransmissions at most are allowed to be tried by FPGA in case ACK is not received in time? - - which time slice in FPGA the packet should go? + - which queue (time slice) in FPGA the packet should go? - should RTS-CTS be used? (Send RTS and wait for CTS before actually send the data packet) - should CTS-to-self be used? (Send CTS-to-self packet before sending the data packet. You can force this on by force_use_cts_protect = true;) - - should a sequence number be set for this packet? + - should a sequence number be inserted? - generate SIGNAL field according to length and MCS information. Insert it before the packet for the future openofdm_tx FPGA module use - - generate FPGA/PHY sequence number (priv->phy_tx_sn) for internal use (cross check between Linux and FPGA) - - config FPGA register according to the above information to make sure FPGA do correct actions according to the packet specific requirement. + - maintain sequence number (ring->bd_wr_idx) for internal use (cross check between Linux and FPGA) + - config FPGA register according to the above information to help FPGA do correct actions according to the packet specific requirement. - fire DMA transmission from Linux to one of FPGA tx queues. The packet may not be sent immediately if there are still some packets in FPGA tx queue (FPGA does the queue packet transmission according to channel and low MAC state) Each time when FPGA sends a packet, an interrupt will be raised to Linux reporting the packet sending result. This interrupt handler is openwifi_tx_interrupt(). @@ -182,12 +216,12 @@ Each time when FPGA sends a packet, an interrupt will be raised to Linux reporti - main operations in openwifi_tx_interrupt() - get necessary information/status of the packet just sent by FPGA - packet length and sequence number to capture abnormal situation (cross checking between Linux and FPGA) - - packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions are used for the packet sending (in case FPGA doesn't receive ACK in time, FPGA will do retransmission immediately) + - packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions have been done (in case FPGA doesn't receive ACK in time, FPGA will do retransmission according to CSMA/CA low MAC state) - send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe() ## Regulation and channel config -SDR is a powerful tool for research. It is the user's duty to align with local spectrum regulation. +SDR is a powerful tool for research. It is the user's responsibility to align with local spectrum regulation. This section explains how openwifi config the frequency/channel range and change it in real-time. After knowing the mechanism, you can try to extend frequency/channel by yourself. @@ -199,7 +233,7 @@ dev->wiphy->regulatory_flags = xxx wiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd); ``` sdr_regd is the predefined variable in sdr.h. You can search the definition/meaning of its type: struct ieee80211_regdomain. -Then not difficult to find out how to change the frequency range in SDR_2GHZ_CH01_14 and SDR_5GHZ_CH36_64. +Then it is not difficult to find out how to change the frequency range in SDR_2GHZ_CH01_14 and SDR_5GHZ_CH36_64. ### Supported channel @@ -220,72 +254,89 @@ Linux mac80211 (struct ieee80211_ops openwifi_ops in sdr.c) uses the "config" AP ## Analog and digital frequency design -Following figure shows the current openwifi analog and digital frequency design strategy. The Tx RF center frequency is tuned with 10MHz offset deliberately to ease Tx Lo leakage suppressed by Rx filter. This RF offset is pre-compensated by Tx DUC (Digital Up Converter) in FPGA (duc_bank_core.bd used by tx_intf.v). It combines AD9361's bandwidth, frequency, sampling rate and FPGA's digital down/up converter (ddc_bank_core.bd/duc_bank_core.bd) setting to achieve this example spectrum arrangement. Values in the figure are configurable in the openwifi design. Please be noticed that **ddc_bank_core.bd is not used anymore**. Because the digital and analog RX Lo is the same, mixer is not needed. Decimation by 2 is implemented in adc_intv.v. +Following figure shows the current openwifi analog and digital frequency design strategy. The Tx RF center frequency is tuned with 10MHz offset deliberately to ease Tx Lo leakage suppressed by Rx filter. This RF offset is pre-compensated by Tx DUC (Digital Up Converter) in FPGA (duc_bank_core.bd used by tx_intf.v). It combines AD9361's bandwidth, frequency, sampling rate and FPGA's digital up converter (duc_bank_core.bd) setting to achieve this example spectrum arrangement. Values in the figure are configurable in the openwifi design. ![](./rf-digital-if-chain-spectrum.jpg) Above spectrum setting has two benefits: - The Tx Lo leakage is suppressed by Rx filter -- The centered Rx Lo and single channel Rx analog filter leads to more easy/accurate RSSI estimation in FPGA (together with real-time AD9361 AGC gain value accessed via FPGA GPIO) +- The centered Rx Lo leads to more easy/accurate RSSI estimation in FPGA (together with real-time AD9361 AGC gain value accessed via FPGA GPIO) -Following figure shows the detailed configuration point in AD9361, driver (sdr.c/tx_intf.c/rx_intf.c/ad9361.c/etc) and related FPGA modules. +Following figure shows the detailed configuration point in AD9361, driver (.c file) and related FPGA modules (.v file). ![](./rf-digital-if-chain-config.jpg) ## Debug methods ### dmesg -To debug/see the basic driver behaviour, you could turn on message printing by +To debug/see the basic driver behaviour, you could turn on **dmesg** message printing by ``` -See all printing: +./sdrctl dev sdr0 set reg drv_tx 7 X +./sdrctl dev sdr0 set reg drv_rx 7 X + +The bit in value X controls what type of information will be printed to the dmesg (0--no print; 1--print). +bit0: error message +bit1: regular message for unicast packet (openwifi_tx/openwifi_tx_interrupt/openwifi_rx_interrupt) +bit2: regular message for broadcast packet + +For example, regular message for unicast packet and error message ./sdrctl dev sdr0 set reg drv_tx 7 3 ./sdrctl dev sdr0 set reg drv_rx 7 3 -See only error printing: + +For example, error message only: ./sdrctl dev sdr0 set reg drv_tx 7 1 ./sdrctl dev sdr0 set reg drv_rx 7 1 -See only regular printing: -./sdrctl dev sdr0 set reg drv_tx 7 2 -./sdrctl dev sdr0 set reg drv_rx 7 2 -Turn off printing: -./sdrctl dev sdr0 set reg drv_tx 7 0 -./sdrctl dev sdr0 set reg drv_rx 7 0 ``` -and use dmesg command in Linux to see those messages. openwifi driver prints normal tx/rx packet information when a packet is sent or received. The driver also prints WARNING information if it feels something abnormal happens. You can search "printk" in sdr.c to see all the printing points. +and use **dmesg** command in Linux to see those messages. Regular printing includes tx/rx packet information when a packet is sent or received. Error printing has WARNING information if something abnormal happens. You can search "printk" in sdr.c to see all the printing points. -- tx printing example - - sdr,sdr openwifi_tx: 84bytes 48M FC0208 DI002c addr1/2/3:b0481ada2ef2/66554433222a/66554433222a SC2100 flag40000012 retr6 ack1 prio2 q2 wr4 rd3 - - printing from sdr driver, openwifi_tx function. - - 84bytes: packet size (length field in SIGNAL) - - 48M: MCS (rate field in SIGNAL) - - FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client). - - DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK). - - addr1/2/3: address fields. Target MAC address b0481ada2ef2, source MAC address 66554433222a (openwifi). - - SC2100: Sequence Control field 0x2100, which means that the driver inserts sequence number 0x2100 to the packet under request of upper layer. - - flag40000012: flags field from upper layer struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.). Here is 0x40000012. - - retry6: upper layer tells us the maximum number of retransmissions for this packet is 6. - - ack1: upper layer tells us this packet needs ACK. - - prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background) - - q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c) - - wr4 rd3: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt). +### tx printing example +``` +sdr,sdr openwifi_tx: 1410bytes ht0 540M FC0208 DI002c addr1/2/3:2ec08902fdb2/6655443322ad/6655443322ad SC2100 flag40000012 retr6 ack1 prio2 q2 wr44 rd31 +``` +- printing from sdr driver, openwifi_tx function +- 1410bytes: packet size (length field in SIGNAL) +- ht0: non-ht means 11a/g; ht1 means 11n +- 54M: MCS (rate field in SIGNAL) +- FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client) +- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK) +- addr1/2/3: address fields. Target MAC address 2ec08902fdb2, source MAC address 6655443322ad (openwifi) +- SC2100: Sequence Control, which means that the driver inserts sequence number 0x2100 to the packet under request of Linux mac80211 +- flag40000012: flags field from Linux mac80211 struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.) +- retry6: Linux mac80211 tells driver the maximum number of transmissions for this packet is 6 +- ack1: Linux mac80211 tells driver this packet needs ACK +- prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background) +- q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c) +- wr44 rd31: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt/FPGA) -- rx printing example - - sdr,sdr openwifi_rx_interrupt: 28bytes 24M FC0108 DI002c addr1/2/3:66554433222a/b0481ada2ef2/66554433222a SC4760 fcs1 buf_idx13 -30dBm - - printing from sdr driver, openwifi_rx_interrupt function. - - 28bytes: packet size (length field in SIGNAL) - - 24M: MCS (rate field in SIGNAL) - - FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP). - - DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK). - - addr1/2/3: address fields. Target MAC address 66554433222a (openwifi), source MAC address b0481ada2ef2. - - SC4760: Sequence Control field 0x4760, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer). - - fcs1: FCS/CRC is OK. (fcs0 means bad CRC) - - buf_idx13: current rx packet DMA buffer index 13. - - -30dBm: signal strength of this received packet. +### tx interrupt printing example +``` +sdr,sdr openwifi_tx_interrupt: tx_result 02 prio2 wr28 rd25 num_rand_slot 21 cw 6 +``` +- printing from sdr driver, openwifi_tx_interrupt function +- tx_result: 5bit, bit3~0 tells how many tx attempts are made on this packet, and bit4 indicates NO ACK (1) or an ACK (0) is received +- prio, wr, rd: these fields can be interpreted the same way as the print in openwifi_tx function +- num_rand_slot: tells how many slots the CSMA/CA state machine waited until the packet is sent in the last tx attempt +- cw: the exponent of the Contention Window for this packet. 6 means the CW size 64. If the contention phase is never entered, CW is 0 + +### rx printing example +``` +sdr,sdr openwifi_rx_interrupt: 796bytes ht0 120M FC0108 DI0030 addr1/2/3:6655443322f4/2ec08902fdb2/6655443322f4 SC4760 fcs1 buf_idx13 -50dBm +``` +- printing from sdr driver, openwifi_rx_interrupt function +- 796bytes: packet size (length field in SIGNAL) +- ht0: non-ht means 11a/g; ht1 means 11n +- 12M: MCS (rate field in SIGNAL) +- FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP) +- DI0030: Duration/ID field 0x0030. How many us this packet will occupy the channel (including waiting for ACK) +- addr1/2/3: address fields. Target MAC address 6655443322f4 (openwifi), source MAC address 2ec08902fdb2 +- SC4760: Sequence Control, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer) +- fcs1: FCS/CRC is OK. (fcs0 means bad CRC) +- buf_idx13: current rx packet DMA buffer index 13 +- -50dBm: signal strength of this received packet (after calibration) ### Native Linux tools -For protocol, many native Linux tools you still could rely on. Such as tcpdump. +For analysis/debug, many native Linux tools you still could rely on. Such as tcpdump, tshark, etc. ### FPGA -For FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals. Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level funtionalities. +For FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals. Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level functionalities. diff --git a/doc/app_notes/40mhz.png.license b/doc/app_notes/40mhz.png.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/40mhz.png.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/README.md b/doc/app_notes/README.md index 9dcbc2b..8f6882f 100644 --- a/doc/app_notes/README.md +++ b/doc/app_notes/README.md @@ -1,3 +1,9 @@ + + Application notes collect many small topics about using openwifi in different scenarios/modes. - [Use openwifi on the w-iLab.t testbed remotely](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) @@ -5,6 +11,8 @@ Application notes collect many small topics about using openwifi in different sc - [Communication between two SDR boards under ad-hoc mode](ad-hoc-two-sdr.md) - [From CSI (Channel State Information) to CSI (Chip State Information)](csi.md) - [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) -- [Capture dual antenna IQ for multi-purpose (capture collision)](iq_2ant.md) +- [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md) - [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md) -- [802.11 packet injection](inject_80211.md) +- [802.11 packet injection and fuzzing](inject_80211.md) +- [CSI fuzzer](csi_fuzzer.md) +- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/E7mer/Owfuzz) diff --git a/doc/app_notes/ad-hoc-two-sdr.md b/doc/app_notes/ad-hoc-two-sdr.md index 64ebd63..87f4ef4 100644 --- a/doc/app_notes/ad-hoc-two-sdr.md +++ b/doc/app_notes/ad-hoc-two-sdr.md @@ -1,3 +1,13 @@ + + +**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet. + +**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!! + - Power on two SDR boards. Call one board "adhoc1" and the other "adhoc2". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation. - Connect a computer to the adhoc1 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal: ``` @@ -12,7 +22,7 @@ (Above command setup ad-hoc network at channel 44 with static IP assigned to sdr0 NIC) iwconfig sdr0 ``` -- You shold see output like: +- You should see output like: ``` sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc" Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0 @@ -31,10 +41,10 @@ cd openwifi ./wgd.sh ifconfig sdr0 up - ./sdr-ad-hoc-up.sh sdr0 44 192.168.13.1 + ./sdr-ad-hoc-up.sh sdr0 44 192.168.13.2 iwconfig sdr0 ``` -- You shold see output like: +- You should see output like: ``` sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc" Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0 diff --git a/doc/app_notes/ap-client-two-sdr.md b/doc/app_notes/ap-client-two-sdr.md index 757ae34..4a767dd 100644 --- a/doc/app_notes/ap-client-two-sdr.md +++ b/doc/app_notes/ap-client-two-sdr.md @@ -1,3 +1,13 @@ + + +**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet. + +**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!! + - Power on two SDR boards. Call one board "AP board" and the other "client board". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation. - Connect a computer to the AP board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal: ``` @@ -22,23 +32,36 @@ ifconfig sdr0 up iwlist sdr0 scan (The "openwifi" AP should be listed in the scanning results) - iwconfig sdr0 essid openwifi + wpa_supplicant -i sdr0 -c wpa-openwifi.conf + ("iwconfig sdr0 essid openwifi" could also work. Less info compared to wpa_supplicant) ``` -- Now the client is trying to associate with the AP. The AP board terminal should print like: + If wpa-openwifi.conf is not on board, please create it with [this content](https://github.com/open-sdr/openwifi/blob/master/user_space/wpa-openwifi.conf). +- Now the client is trying to associate with the AP. You should see like: + ``` + root@analog:~/openwifi# wpa_supplicant -i sdr0 -c wpa-openwifi.conf + Successfully initialized wpa_supplicant + sdr0: CTRL-EVENT-SCAN-STARTED + sdr0: SME: Trying to authenticate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz) + sdr0: Trying to associate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz) + sdr0: Associated with 66:55:44:33:22:8c + sdr0: CTRL-EVENT-CONNECTED - Connection to 66:55:44:33:22:8c completed [id=0 id_str=] + ``` + The AP board terminal should print like: ``` ... - sdr0: AP-STA-CONNECTED 66:55:44:33:22:58 - sdr0: STA 66:55:44:33:22:58 RADIUS: starting accounting session 1FF1C1B4-00000001 + sdr0: STA 66:55:44:33:22:4c IEEE 802.11: authenticated + sdr0: STA 66:55:44:33:22:4c IEEE 802.11: associated (aid 1) + sdr0: AP-STA-CONNECTED 66:55:44:33:22:4c + sdr0: STA 66:55:44:33:22:4c RADIUS: starting accounting session 613E16DE-00000000 ``` If not, please adjust antenna/distance and re-run the commands on the client side. -- After association is done, in the terminal of client: +- After association is done, in another terminal of client (**DO NOT** terminate wpa_supplicant in the original client terminal!): ``` dhclient sdr0 (Wait for it completed) ifconfig sdr0 (Now you should see the IP address like 192.168.13.x allocated by AP) - ./set_csma_normal.sh ping 192.168.13.1 (Ping the AP) ``` diff --git a/doc/app_notes/csi-architecture.jpg.license b/doc/app_notes/csi-architecture.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/csi-architecture.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/csi-fuzzer-beacon-ant-back-0.jpg b/doc/app_notes/csi-fuzzer-beacon-ant-back-0.jpg new file mode 100644 index 0000000..ce8a2b6 Binary files /dev/null and b/doc/app_notes/csi-fuzzer-beacon-ant-back-0.jpg differ diff --git a/doc/app_notes/csi-fuzzer-beacon-ant-back-1-45-0-13.jpg b/doc/app_notes/csi-fuzzer-beacon-ant-back-1-45-0-13.jpg new file mode 100644 index 0000000..f77d137 Binary files /dev/null and b/doc/app_notes/csi-fuzzer-beacon-ant-back-1-45-0-13.jpg differ diff --git a/doc/app_notes/csi-fuzzer-implementation.png b/doc/app_notes/csi-fuzzer-implementation.png new file mode 100644 index 0000000..cc3d9e9 Binary files /dev/null and b/doc/app_notes/csi-fuzzer-implementation.png differ diff --git a/doc/app_notes/csi-fuzzer-principle.png b/doc/app_notes/csi-fuzzer-principle.png new file mode 100644 index 0000000..a414c33 Binary files /dev/null and b/doc/app_notes/csi-fuzzer-principle.png differ diff --git a/doc/app_notes/csi-fuzzer-system-before-vs-now.png b/doc/app_notes/csi-fuzzer-system-before-vs-now.png new file mode 100644 index 0000000..2bb136b Binary files /dev/null and b/doc/app_notes/csi-fuzzer-system-before-vs-now.png differ diff --git a/doc/app_notes/csi-information-format.jpg.license b/doc/app_notes/csi-information-format.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/csi-information-format.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/csi-screen-shot.jpg b/doc/app_notes/csi-screen-shot.jpg new file mode 100644 index 0000000..6ec27ce Binary files /dev/null and b/doc/app_notes/csi-screen-shot.jpg differ diff --git a/doc/app_notes/csi-screen-shot.jpg.license b/doc/app_notes/csi-screen-shot.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/csi-screen-shot.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/csi.md b/doc/app_notes/csi.md index 187ed53..659c3ee 100644 --- a/doc/app_notes/csi.md +++ b/doc/app_notes/csi.md @@ -1,3 +1,10 @@ + + + We extend the **CSI** (Channel State Information) to **CSI** (Chip State Information)! ## Quick start @@ -22,14 +29,15 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa ``` If the second number (61, 99, ...) is not zero and keeps increasing, that means the CSI (Chip State Information) is going to the computer smoothly. -- Open another terminal on the computer, and run: +- On your computer (NOT in ssh!), run: ``` cd openwifi/user_space/side_ch_ctl_src python3 side_info_display.py ``` The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see 3 figures showing run-time **frequency offset**, **channel state/response** and **constellation form equalizer**. Meanwhile the python script prints the **timestamp**. + ![](./csi-screen-shot.jpg) - While running, all informations are also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline. + While running, all information is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline. ## Understand the CSI feature The CSI information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer. @@ -46,7 +54,7 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa The python and Matlab scripts are recommended for you to understand the CSI packet format precisely. ## Config the capture condition and interval - The quick start guide will monitor all CSI informations of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**". + The quick start guide will monitor all CSI information of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**". A quick example: Capture only CSI of those packets from the device with MAC address 56:5b:01:ec:e2:8f ``` @@ -93,7 +101,7 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa The interval will become N*1ms ## Config the num_eq - The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer informations. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m. + The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer information. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m. - When insert the kernel module, use: ``` insmod side_ch.ko num_eq_init=3 diff --git a/doc/app_notes/csi_fuzzer.md b/doc/app_notes/csi_fuzzer.md new file mode 100644 index 0000000..4cc08d6 --- /dev/null +++ b/doc/app_notes/csi_fuzzer.md @@ -0,0 +1,79 @@ + + +[ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255) + +CSI (Channel State Information) of WiFi systems is available in some WiFi chips and can be used for sensing the environment (keystrokes, people, object) passively and secretly. + +## Concept + +How could a CSI fuzzer stop unauthorized sensing? + +![](./csi-fuzzer-system-before-vs-now.png) + +CSI fuzzer implementation principle. + +![](./csi-fuzzer-principle.png) + +## Demo instructions + +Thanks to the full-duplex capability and CSI extraction feature of openwifi, you can monitor the artificial channel response via [side channel](./csi.md) by Tx-Rx over the air coupling without affecting the normal operation/traffic of openwifi. Before the self-monitoring, the auto-mute during Tx needs to be disabled. + +The full demo steps are: + +``` +ssh root@192.168.10.122 +(password: openwifi) + +cd openwifi + +./fosdem-11ag.sh +(setup openwifi AP) + +./sdrctl dev sdr0 set reg xpu 1 1 +(Disable auto-muting to listen self-TX) + +insmod side_ch.ko num_eq_init=0 + +./side_ch_ctl wh1h2001 +./side_ch_ctl wh6hffffffff +(Let's only monitor self-beacon-TX CSI over-the-air loopback) + +./side_ch_ctl g1 +``` +Go to openwifi/user_space/side_ch_ctl_src, and run `python3 side_info_display.py 0`. You should see the over-the-air loopback CSI when CSI fuzzer is not enabled. Then stop the python3 side_info_display.py script to ease the next step. + +Start another ssh session to the openwifi board: +``` +ssh root@192.168.10.122 +(password: openwifi) + +cd openwifi + +./csi_fuzzer_scan.sh 1 +(CSI fuzzer applies possible artificial CSI by scanning all values) +(csi_fuzzer.sh is called. Please read both scripts to understand these commands) +``` + +Go to openwifi/user_space/side_ch_ctl_src, and run `python3 side_info_display.py 0`. Now you should see that CSI keeps changing like in this [video](https://youtu.be/aOPYwT77Qdw). + +# Further explanation on parameters + +CSI fuzzer in openwifi system architecture and related commands. + +![](./csi-fuzzer-implementation.png) + +# Example fuzzed CSI + +CSI self-monitoring before fuzzing. + +![](./csi-fuzzer-beacon-ant-back-0.jpg) + +CSI self-monitoring after fuzzing command: `csi_fuzzer.sh 1 45 0 13` + +![](./csi-fuzzer-beacon-ant-back-1-45-0-13.jpg) + +`csi_fuzzer_scan.sh` can scan the c1 and c2 in different styles/modes by calling `csi_fuzzer.sh`. diff --git a/doc/app_notes/guard-interval.png.license b/doc/app_notes/guard-interval.png.license new file mode 100644 index 0000000..f556e06 --- /dev/null +++ b/doc/app_notes/guard-interval.png.license @@ -0,0 +1,4 @@ +# Author: Michael Mehari + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/ieee80211n.md b/doc/app_notes/ieee80211n.md index 92c05aa..cfa499a 100644 --- a/doc/app_notes/ieee80211n.md +++ b/doc/app_notes/ieee80211n.md @@ -1,3 +1,8 @@ + ## IEEE 802.11n (Wi-Fi 4) diff --git a/doc/app_notes/inject_80211.md b/doc/app_notes/inject_80211.md index 98595b1..aa0a637 100644 --- a/doc/app_notes/inject_80211.md +++ b/doc/app_notes/inject_80211.md @@ -1,19 +1,60 @@ + -## 802.11 packet injection +## 802.11 packet injection and fuzzing -The Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing. +The Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing and manual/total control mode (fuzzing). Ping and Iperf are well established performance measurement tools. However, using such tools to measure 802.11 PHY performance can be misleading, simply because they touch multiple layers in the network stack. -Luckily, the mac80211 Linux subsystem provides packet injection functionality and it allows us to have finer control over physical layer testing. +Luckily, the mac80211 Linux subsystem provides packet injection functionality when the NIC is in the monitor mode and it allows us to have finer control for physical layer testing and/or fuzzing. -To this end, we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application originally written by Andy Green and maintained by George Nychis . +Besides the traditional fuzzing tool (like scapy), we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application, which is originally written by Andy Green and maintained by George Nychis , to show how to inject packets and control the FPGA behavior. -### inject_80211 +### Build inject_80211 on board Userspace program to inject 802.11 packets through mac80211 supported (softmac) wireless devices. -### Options - ``` +Login/ssh to the board and setup internet connection according to the Quick Start. Then +``` +cd openwifi/inject_80211 +make +``` +### Customize the packet content +To customize the packet, following piece of the inject_80211.c needs to be changed: +``` +/* IEEE80211 header */ +static const u8 ieee_hdr[] = +{ + 0x08, 0x01, 0x00, 0x00, // FC 0x0801. 0--subtype; 8--type&version; 01--toDS1 fromDS0 (data packet to DS) + 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP + 0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Source address (STA) + 0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Destination address (another STA under the same AP) + 0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number +}; +``` +Note: The byte/bit order might not be intuitive when comparing with the standard. + +### FPGA behavior control +- ACK and retransmission after FPGA sends packet + +In openwifi_tx of sdr.c, many FPGA behaviors can be controled. Generally they are controled by the information from upper layer (Linux mac80211), but you can override them in driver (sdr.c) + +If 802.11 ACK is expected from the peer after the packet is sent by FPGA, variable **pkt_need_ack** should be overridden to 1. In this case, the FPGA will try to receive ACK, and report the sending status (ACK is received or not) to upper layer (Linux mac80211) + +The maximum times of transmission for the packet can be controled by variable **retry_limit_raw**. If no ACK is received after the packet is sent, FPGA will try retransmissions automatically if retry_limit_raw>1. + +- ACK after FPGA receives packet in monitor mode + +Even in monitor mode, openwifi FPGA still sends ACK after the packet is received, if the conditions are met: MAC address is matched, it is a data frame, etc. To disable this automatic ACK generation, the register 11 of xpu should be set to 16: +``` +sdrctl dev sdr0 set reg xpu 11 16 +``` + +### Options of program inject_80211 +``` -m/--hw_mode (a,g,n) -r/--rate_index (0,1,2,3,4,5,6,7) -i/--sgi_flag (0,1) @@ -21,12 +62,24 @@ Userspace program to inject 802.11 packets through mac80211 supported (softmac) -s/--payload_size -d/--delay -h this menu - ``` +``` ### Example: +Login/ssh to the board, Then ``` -iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up -inject_80211 -m n -r 0 -n 64 -s 100 mon0 # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size +cd openwifi +./wgd.sh +./monitor_ch.sh sdr0 11 +(Above will turn sdr0 into the monitor mode and monitor on channel 11) +./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 sdr0 +(Above will inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size via NIC sdr0) +``` +When above injection command is running, you could see the injected packets with wireshark (or other packet sniffer) on another WiFi device monitoring channel 11. + +Or add extra virtual monitor interface on top of sdr0, and inject packets: +``` +iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up +./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 mon0 # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size ``` ### Link performance test @@ -57,7 +110,7 @@ done On the receiver side, we can use tcpdump to collect the pcap traces. ``` -iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up +iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up tcpdump -i mon0 -w trace.pcap 'wlan addr1 ff:ff:ff:ff:ff:ff and wlan addr2 66:55:44:33:22:11' ``` diff --git a/doc/app_notes/iq-architecture.jpg.license b/doc/app_notes/iq-architecture.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq-architecture.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq-capture-parameter.jpg.license b/doc/app_notes/iq-capture-parameter.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq-capture-parameter.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq-information-format.jpg.license b/doc/app_notes/iq-information-format.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq-information-format.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq-screen-shot.jpg b/doc/app_notes/iq-screen-shot.jpg new file mode 100644 index 0000000..cb67f22 Binary files /dev/null and b/doc/app_notes/iq-screen-shot.jpg differ diff --git a/doc/app_notes/iq-screen-shot.jpg.license b/doc/app_notes/iq-screen-shot.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq-screen-shot.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq.md b/doc/app_notes/iq.md index e30f31f..bd11a4e 100644 --- a/doc/app_notes/iq.md +++ b/doc/app_notes/iq.md @@ -1,3 +1,10 @@ + + + We implement the **IQ sample capture** with interesting extensions: many **trigger conditions**; **RSSI**, RF chip **AGC** **status (lock/unlock)** and **gain**. ## Quick start @@ -34,8 +41,9 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg (for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095) ``` The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see 3 figures showing run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**. + ![](./iq-screen-shot.jpg) - While running, all informations are also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095. + While running, all information is also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095. ## Understand the IQ capture feature The IQ information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer. @@ -104,6 +112,12 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg 30|start tx, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th 31|start tx and need for ACK, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th + If free running is wanted (alway trigger), please use the following two commands together. + ``` + ./side_ch_ctl wh8d0 + ./side_ch_ctl wh5d1 + ``` + To set the RSSI threshold ``` ./side_ch_ctl wh9dY @@ -123,7 +137,7 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg The interval will become N*1ms ## Config the iq_len - The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independant from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m. + The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independent from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m. - When insert the kernel module, use: ``` insmod side_ch.ko iq_len_init=3000 diff --git a/doc/app_notes/iq_2ant-screen-shot.jpg b/doc/app_notes/iq_2ant-screen-shot.jpg new file mode 100644 index 0000000..3318a37 Binary files /dev/null and b/doc/app_notes/iq_2ant-screen-shot.jpg differ diff --git a/doc/app_notes/iq_2ant-screen-shot.jpg.license b/doc/app_notes/iq_2ant-screen-shot.jpg.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq_2ant-screen-shot.jpg.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq_2ant-setup.png b/doc/app_notes/iq_2ant-setup.png new file mode 100644 index 0000000..db140c9 Binary files /dev/null and b/doc/app_notes/iq_2ant-setup.png differ diff --git a/doc/app_notes/iq_2ant-setup.png.license b/doc/app_notes/iq_2ant-setup.png.license new file mode 100644 index 0000000..7545c3b --- /dev/null +++ b/doc/app_notes/iq_2ant-setup.png.license @@ -0,0 +1,4 @@ +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/app_notes/iq_2ant.md b/doc/app_notes/iq_2ant.md index 42504bf..a99a9d9 100644 --- a/doc/app_notes/iq_2ant.md +++ b/doc/app_notes/iq_2ant.md @@ -1,9 +1,22 @@ -Instead of [**normal IQ sample capture**](iq.md), this app note introduce how to enable the I/Q capture for dual antenna. In this dual antenna mode, the RSSI and AGC status won't be captured as in the normal mode. Instead, they are replaced by the I/Q samples from the other antenna. But you are suggested to read the [**normal IQ sample capture**](iq.md) to understand how do we use the side channel to capture I/Q sample by different trigger conditions. + -In this app note, we show how to use the dual antenna I/Q capture to capture the collision. -## Quick start - The currently selected antenna (rx0 by default if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1) will be also avaliable for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time. +Instead of [**normal IQ sample capture**](iq.md), this app note introduces how to enable the I/Q capture for dual antennas. Besides the I/Q from the main antenna (that is selected by baseband), the I/Q samples from the other antenna (monitoring antenna) is captured as well (coherently synchronized) in this dual antenna mode. You are suggested to read the [**normal IQ sample capture**](iq.md) to understand how we use the side channel to capture I/Q samples by different trigger conditions. + +This feature also support capturing TX I/Q (loopback) to test the baseband transmitter. + +- [[Quick start for collision capture](#Quick-start-for-collision-capture)] +- [[Quick start for TX IQ capture in trigger mode](#Quick-start-for-TX-IQ-capture-in-trigger-mode)] +- [[Quick start for TX IQ capture in free running mode](#Quick-start-for-TX-IQ-capture-in-free-running-mode)] + +## Quick start for collision capture +![](./iq_2ant-setup.png) + + The main antenna rx0 (by default selected by baseband if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1 -- monitoring antenna) will be also available for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time. The collision capture steps: - Change rx1 AGC to manual mode instead of fast_attack in rf_init.sh by: @@ -40,7 +53,10 @@ In this app note, we show how to use the dual antenna I/Q capture to capture the python3 iq_capture_2ant.py (if smaller FPGA, like z7020, is used, add a argument that equals to iq_len_init, like 4095) ``` - Above script will plot the real-time rx0 and rx1 I/Q captured each time trigger condition met. Meanwhile the script also prints the maximum amplitutde of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicate a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets). + Above script will plot the real-time rx0 and rx1 I/Q captured each time the trigger condition is met. . + ![](./iq_2ant-screen-shot.jpg) + In the above example, the upper half shows the signal received from the main antenna (self tx is not seen because of self muting in FPGA), the lower half shows not only the rx signal from the monitoring antenna but also the tx signal from the main antenna due to coupling. + Meanwhile the script also prints the maximum amplitude of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicates a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets). - Set trigger condition to 29, which means that rx1 I/Q is found larger than a threshold while SDR is transmitting -- this means a collision condition is captured because rx1 I/Q implies the transmitting from the peer WiFi node. The threshold value is decided in the previous step (2500 is assumed here). ``` (Quit side_ch_ctl by Ctrl+C) @@ -51,3 +67,50 @@ In this app note, we show how to use the dual antenna I/Q capture to capture the - Now the trigger condition can capture the case where both sides happen to transmit in an overlapped duration. If the printed "**side info count**" is increasing, it means the collision happens from time to time. - You can also see it via iq_capture_2ant.py or do offline analysis by test_iq_2ant_file_display.m - Check the **iq1** signal in FPGA ILA/probe (triggered by signal "iq_trigger") for further debug if you want to know what exactly happened when collision is captured. + +## Quick start for TX IQ capture in trigger mode + +To capture the TX I/Q (baseband loopback), a scenario where openwifi will do TX needs to be set up. Such as beacon TX when openwifi act as AP, or [packet injection](inject_80211.md). + +The example command sequence on board and explanations are as follows. +``` +cd openwifi +./fosdem.sh +insmod side_ch.ko iq_len_init=511 +(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case) +./side_ch_ctl wh11d1 +(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met) +./side_ch_ctl wh8d16 +(trigger condition 16: phy_tx_started signal from openofdm tx core) +./side_ch_ctl wh5h2 +(I/Q source selection: 2--openofdm_tx core; 4--tx_intf) +./side_ch_ctl wh3h11 +./side_ch_ctl g1 +``` +On computer: +``` +openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511 + +``` + +## Quick start for TX IQ capture in free running mode + +``` +cd openwifi +./fosdem.sh +insmod side_ch.ko iq_len_init=511 +(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case) +./side_ch_ctl wh11d1 +(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met) +./side_ch_ctl wh8d0 +(trigger condition 0 is needed for free running mode) +./side_ch_ctl wh5h3 +(I/Q source selection: 3--openofdm_tx core; 5--tx_intf) +./side_ch_ctl wh3h11 +./side_ch_ctl g1 +``` +On computer: +``` +openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511 + +``` diff --git a/doc/app_notes/mimo.png.license b/doc/app_notes/mimo.png.license new file mode 100644 index 0000000..294e3a7 --- /dev/null +++ b/doc/app_notes/mimo.png.license @@ -0,0 +1,5 @@ +# Author: Michael Mehari + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + diff --git a/doc/app_notes/mpdu-aggr.png.license b/doc/app_notes/mpdu-aggr.png.license new file mode 100644 index 0000000..294e3a7 --- /dev/null +++ b/doc/app_notes/mpdu-aggr.png.license @@ -0,0 +1,5 @@ +# Author: Michael Mehari + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + diff --git a/doc/app_notes/subcarriers.png.license b/doc/app_notes/subcarriers.png.license new file mode 100644 index 0000000..294e3a7 --- /dev/null +++ b/doc/app_notes/subcarriers.png.license @@ -0,0 +1,5 @@ +# Author: Michael Mehari + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + diff --git a/doc/asic/skywater-130-pdk-and-asic-considerations.md b/doc/asic/skywater-130-pdk-and-asic-considerations.md new file mode 100644 index 0000000..eac643b --- /dev/null +++ b/doc/asic/skywater-130-pdk-and-asic-considerations.md @@ -0,0 +1,45 @@ +Hello, + +The skywater PDK and free MPW shuttle are interesting. And indeed we are asked many times to consider sky130 or other ASIC process MPW. + +We do agree that building a real openwifi chip will probably (or not) mean a lot for the community, user and the world. + +But, due to our limited bandwidth, currently we are focusing on making the openwifi IP more stable/mature/as-good-as COTS WiFi chip by using the FPGA verification platform, so we haven’t found time to take a look at a real WiFi chip design yet. + +WiFi chips could be as cheap as 0.5USD, but it doesn't mean the WiFi chip is simple. This is contrary to many people’s minds. I tried to explain the complexity of the WiFi chip in some videos, such as the FOSDEM and Libreplanet videos on this page: https://github.com/open-sdr/openwifi/blob/master/doc/videos.md . The WiFi chip is cheap only because they are sold so many per year. From this perspective, the WiFi chip is really an essential tiny thing of the modern world. + +But we are definitely glad to support/answer-questions if someone else could jump in and do a solid analysis on the ASIC design effort. Some hints: + +1 . The info and communication hub is our github: https://github.com/open-sdr/openwifi . The FPGA code is in https://github.com/open-sdr/openwifi-hw . + +2 . The best way to get full picture and further info (resource/power/clock-speed/etc) of the openwifi FPGA design is downloading Xilinx Vivado (version is listed on our github) tool chain, and go through our full FPGA build procedure (README of openwifi-hw: https://github.com/open-sdr/openwifi-hw/blob/master/README.md ), where you will see the full system block diagram: not only the openwifi IP, but also all interfacing/peripheral IP around. Of course many of them are Xilinx/Analog-Devices specific. + +3 . You don’t need to pay any fee for Xilinx Vivado, if you chose the FPGA boards (the full list of supported FPGA board is in the README of openwifi: https://github.com/open-sdr/openwifi/blob/master/README.md ) that has 7020 FPGA, because Xilinx offer free offer for that small scale FPGA. + +4 . Try to find out all the vendor/3rd-part (Xilinx/Analog-Devices/etc) IPs, and evaluate/estimate how big the efforts will be if they need to be turned into sky130 or other ASIC design. As far as I remember (not full list), inside openwifi IP, we use these IP cores from Xilinx: +- FFT +- Viterbi decoder +- FIFO +- dual port RAM +- ROM +- FIR filter +- AXI stream DMA +- AXI lite bus +- integer divider +- integer multiplexer +- etc. + +I guess most of them need to be ported if we go for a real chip. + +5 . Also outside openwifi IP, there are interfacing/peripheral IPs from Xilinx/Analog-Devices, which can be seen if you create and open the openwifi project block diagram in Vivado (follow the openwifi-hw README). Two special things: RF and ARM processor interconnection. +- Currently the RF front-end is AD9361 (off-FPGA), which is not a dedicated WiFi front-end (2.4GH/5GHz only). Instead, AD9361 is a quite expensive front-end that supports 70M~6GHz for SDR (Software Defined Radio) applications. So of course, there will be dedicated AD9361 interfacing IPs from Analog Devices (open source as well: https://github.com/analogdevicesinc/hdl, but the license situation is complicated: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE ) +- Unlike usual WiFi chips that work with processors via USB/PCIe/SDIO/etc bus, openwifi IP interconnects to the ARM processor via AXI bus. This brings us some unique benefits, such as low latency, but it also makes the IP quite platform dependent. + +6 . Last but not least, considering the efforts (seems big) needed for a real openwifi ASIC, we believe that some bigger/stronger organizations (like foundation/company/person), that have rich experience on IP/licensing analysis and ASIC design, could set up an initiative to work on this openwifi chip activity. Of course, we will be more than happy to join and support it. But to be honest, the openwifi team has very limited ASIC design experiences, and we mainly focus on FPGA for now (due to the bandwidth: personal resource, funding, etc.) + +Further discussions/ideas? Feel free to reach out to us! + +Best regards, + +Xianjun + diff --git a/doc/cite-openwifi-github-code.md b/doc/cite-openwifi-github-code.md new file mode 100644 index 0000000..7a472e7 --- /dev/null +++ b/doc/cite-openwifi-github-code.md @@ -0,0 +1,8 @@ +``` +@electronic{openwifigithub, + author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael}, + title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design}, + url = {https://github.com/open-sdr/openwifi}, + year = {2019}, +} +``` diff --git a/doc/cite-openwifi-vtc-paper.md b/doc/cite-openwifi-vtc-paper.md new file mode 100644 index 0000000..f4d20ad --- /dev/null +++ b/doc/cite-openwifi-vtc-paper.md @@ -0,0 +1,10 @@ +``` +@inproceedings{jiao2020openwifi, + title={openwifi: a free and open-source IEEE802. 11 SDR implementation on SoC}, + author={Jiao, Xianjun and Liu, Wei and Mehari, Michael and Aslam, Muhammad and Moerman, Ingrid}, + booktitle={2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring)}, + pages={1--2}, + year={2020}, + organization={IEEE} +} +``` diff --git a/doc/openwifi-detail.jpg b/doc/openwifi-detail.jpg index 2527749..312277a 100644 Binary files a/doc/openwifi-detail.jpg and b/doc/openwifi-detail.jpg differ diff --git a/doc/openwifi-detail.jpg.license b/doc/openwifi-detail.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/doc/openwifi-detail.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/publications.md b/doc/publications.md new file mode 100644 index 0000000..16cdc13 --- /dev/null +++ b/doc/publications.md @@ -0,0 +1,28 @@ + + +If your work uses openwifi, please cite the first VTC2020 openwifi paper: [LaTex example](cite-openwifi-vtc-paper.md) + +You can also cite openwifi github code: [LaTex example](cite-openwifi-github-code.md). + +Other openwifi related publications: +- [VTC2020 spring Antwerp. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf) +- [ORCA project opencall: CSI MURDER](https://ans.unibs.it/projects/csi-murder/) +- [ELSEVIER Computer Networks, 2021. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X) +- [ICIT2021. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients](https://biblio.ugent.be/publication/8700714/file/8700715.pdf) +- [ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255) +- [Microwaves&RF, 2021. Wireless Time-Sensitive Networks: When Every Microsecond Counts](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts) +- [CNERT2021. High precision time synchronization on Wi-Fi based multi-hop network](https://biblio.ugent.be/publication/8709058/file/8709060.pdf) +- [Blackhat asia 2021, OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz) +- [UGent master thesis 2021. The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work by Cedric Den Haese](https://users.ugent.be/~xjiao/Cedric_Den_Haese_masterproef.pdf) +- [UGent master thesis 2021. IEEE 802.11 Physical Layer Fuzzing Using OpenWifi by Steven Heijse](https://users.ugent.be/~xjiao/Steven_Heijse_masterproef.pdf) +- [Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf) +- [Arxiv. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications](https://arxiv.org/abs/2109.03032) +- [Wireless Personal Communications (2021). Bringing Time-Sensitive Networking to Wireless Professional Private Networks](https://link.springer.com/article/10.1007/s11277-021-09056-0) +- [MethodsX. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks](https://www.sciencedirect.com/science/article/pii/S2215016121003368) +- [IEEE Transactions on Industrial Informatics. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP](https://ieeexplore.ieee.org/document/9573364) + +**Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).** diff --git a/doc/rf-digital-if-chain-config.jpg b/doc/rf-digital-if-chain-config.jpg index efbdae8..3211f82 100644 Binary files a/doc/rf-digital-if-chain-config.jpg and b/doc/rf-digital-if-chain-config.jpg differ diff --git a/doc/rf-digital-if-chain-config.jpg.license b/doc/rf-digital-if-chain-config.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/doc/rf-digital-if-chain-config.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/rf-digital-if-chain-spectrum.jpg.license b/doc/rf-digital-if-chain-spectrum.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/doc/rf-digital-if-chain-spectrum.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/doc/videos.md b/doc/videos.md new file mode 100644 index 0000000..ce46139 --- /dev/null +++ b/doc/videos.md @@ -0,0 +1,10 @@ +- The 1st public demo video [[Youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)] +- FOSDEM2020 presentation [[Youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)] +- Low latency for gaming and general introduction [[Youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)] +- CSI (Channel State Information) [[Youtube](https://youtu.be/DanB1ClVamU)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)] +- FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://mirror.as35701.net/video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)] +- FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)] +- Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)] +- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)] +- NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)] +- High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)] diff --git a/driver/ad9361/Makefile b/driver/ad9361/Makefile deleted file mode 100644 index 8aa0d05..0000000 --- a/driver/ad9361/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - -ad9361_drv-y := ad9361.o ad9361_conv.o -obj-m += ad9361_drv.o - -all: - make -C $(KDIR) M=$(PWD) modules - # ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- - -clean: - rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order diff --git a/driver/ad9361/README.md b/driver/ad9361/README.md new file mode 100644 index 0000000..0f3b2e5 --- /dev/null +++ b/driver/ad9361/README.md @@ -0,0 +1,6 @@ + +We don't maintain our own (modified) ad9361 driver anymore! The original ad9361 driver in the Linux kernel tree can be used with some extra EXPORT_SYMBOL. diff --git a/driver/ad9361/ad9361.c b/driver/ad9361/ad9361.c index dda1a9f..9dc720e 100644 --- a/driver/ad9361/ad9361.c +++ b/driver/ad9361/ad9361.c @@ -2,8 +2,6 @@ * AD9361 Agile RF Transceiver * * Copyright 2013-2015 Analog Devices Inc. - * - * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be * * Licensed under the GPL-2. */ @@ -1631,7 +1629,6 @@ static int ad9361_get_rx_gain(struct ad9361_rf_phy *phy, out: return rc; } -EXPORT_SYMBOL(ad9361_get_rx_gain); static u8 ad9361_ensm_get_state(struct ad9361_rf_phy *phy) { @@ -2009,7 +2006,6 @@ out: return rc; } -EXPORT_SYMBOL(ad9361_set_rx_gain); static int ad9361_gc_update(struct ad9361_rf_phy *phy) { @@ -2177,9 +2173,8 @@ static int ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, out: return rc; } -EXPORT_SYMBOL(ad9361_set_gain_ctrl_mode); -int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi) +static int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi) { struct spi_device *spi = phy->spi; u8 reg_val_buf[6]; @@ -2208,7 +2203,6 @@ int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi) return rc; } -EXPORT_SYMBOL(ad9361_read_rssi); static int ad9361_rx_adc_setup(struct ad9361_rf_phy *phy, unsigned long bbpll_freq, unsigned long adc_sampl_freq_Hz) @@ -3737,7 +3731,6 @@ int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable } EXPORT_SYMBOL(ad9361_ctrl_outs_setup); - //************************************************************ // Setup GPO //************************************************************ @@ -3783,7 +3776,7 @@ static int ad9361_gpo_setup(struct ad9361_rf_phy *phy, struct gpo_control *ctrl) return 0; } -int ad9361_rssi_setup(struct ad9361_rf_phy *phy, +static int ad9361_rssi_setup(struct ad9361_rf_phy *phy, struct rssi_control *ctrl, bool is_update) { @@ -3874,7 +3867,6 @@ int ad9361_rssi_setup(struct ad9361_rf_phy *phy, return 0; } -EXPORT_SYMBOL(ad9361_rssi_setup); static int ad9361_bb_clk_change_handler(struct ad9361_rf_phy *phy) { @@ -4078,12 +4070,6 @@ static int ad9361_validate_trx_clock_chain(struct ad9361_rf_phy *phy, return -EINVAL; } -int ad9361_clk_set_rate(struct clk *clk, unsigned long rate) { - clk_set_rate(clk, rate); - return 0; -} -EXPORT_SYMBOL(ad9361_clk_set_rate); - static int ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, unsigned long *rx_path_clks, unsigned long *tx_path_clks) @@ -5226,7 +5212,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg) return ret; } -int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, +static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, u32 rf_rx_bw, u32 rf_tx_bw) { struct ad9361_rf_phy_state *st = phy->state; @@ -5260,7 +5246,6 @@ int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, return 0; } -EXPORT_SYMBOL(ad9361_update_rf_bandwidth); static int ad9361_verify_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, diff --git a/driver/ad9361/ad9361.h b/driver/ad9361/ad9361.h deleted file mode 100644 index bb07759..0000000 --- a/driver/ad9361/ad9361.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * AD9361 - * - * Copyright 2013-2018 Analog Devices Inc. - * - * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - * - * Licensed under the GPL-2. - */ - -#ifndef IIO_FREQUENCY_AD9361_H_ -#define IIO_FREQUENCY_AD9361_H_ - -#include "ad9361_regs.h" - -enum ad9361_clocks { - BB_REFCLK, - RX_REFCLK, - TX_REFCLK, - BBPLL_CLK, - ADC_CLK, - R2_CLK, - R1_CLK, - CLKRF_CLK, - RX_SAMPL_CLK, - DAC_CLK, - T2_CLK, - T1_CLK, - CLKTF_CLK, - TX_SAMPL_CLK, - RX_RFPLL_INT, - TX_RFPLL_INT, - RX_RFPLL_DUMMY, - TX_RFPLL_DUMMY, - RX_RFPLL, - TX_RFPLL, - NUM_AD9361_CLKS, -}; - -enum debugfs_cmd { - DBGFS_NONE, - DBGFS_INIT, - DBGFS_LOOPBACK, - DBGFS_BIST_PRBS, - DBGFS_BIST_TONE, - DBGFS_BIST_DT_ANALYSIS, - DBGFS_RXGAIN_1, - DBGFS_RXGAIN_2, - DBGFS_MCS, - DBGFS_CAL_SW_CTRL, - DBGFS_DIGITAL_TUNE, - DBGFS_GPO_SET, -}; - -enum dig_tune_flags { - BE_VERBOSE = 1, - BE_MOREVERBOSE = 2, - DO_IDELAY = 4, - DO_ODELAY = 8, - SKIP_STORE_RESULT = 16, - RESTORE_DEFAULT = 32, -}; - -enum ad9361_bist_mode { - BIST_DISABLE, - BIST_INJ_TX, - BIST_INJ_RX, -}; - -enum { - ID_AD9361, - ID_AD9364, - ID_AD9361_2, - ID_AD9363A, -}; - -enum rx_port_sel { - RX_A_BALANCED, /* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */ - RX_B_BALANCED, /* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced */ - RX_C_BALANCED, /* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced */ - RX_A_N, /* 3 = RX1A_N and RX2A_N enabled; unbalanced */ - RX_A_P, /* 4 = RX1A_P and RX2A_P enabled; unbalanced */ - RX_B_N, /* 5 = RX1B_N and RX2B_N enabled; unbalanced */ - RX_B_P, /* 6 = RX1B_P and RX2B_P enabled; unbalanced */ - RX_C_N, /* 7 = RX1C_N and RX2C_N enabled; unbalanced */ - RX_C_P, /* 8 = RX1C_P and RX2C_P enabled; unbalanced */ - TX_MON1, /* 9 = TX_MON1 enabled */ - TX_MON2, /* 10 = TX_MON2 enabled */ - TX_MON1_2, /* 11 = TX_MON1 & TX_MON2 enabled */ -}; - -enum tx_port_sel { - TX_A, - TX_B, -}; - -enum digital_tune_skip_mode { - TUNE_RX_TX, - SKIP_TX, - SKIP_ALL, -}; - -enum rssi_restart_mode { - AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN, - EN_AGC_PIN_IS_PULLED_HIGH, - ENTERS_RX_MODE, - GAIN_CHANGE_OCCURS, - SPI_WRITE_TO_REGISTER, - GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH, -}; - -struct ctrl_outs_control { - u8 index; - u8 en_mask; -}; - -struct rssi_control { - enum rssi_restart_mode restart_mode; - bool rssi_unit_is_rx_samples; /* default unit is time */ - u32 rssi_delay; - u32 rssi_wait; - u32 rssi_duration; -}; - -struct rf_rssi { - u32 ant; /* Antenna number for which RSSI is reported */ - u32 symbol; /* Runtime RSSI */ - u32 preamble; /* Initial RSSI */ - s32 multiplier; /* Multiplier to convert reported RSSI */ - u8 duration; /* Duration to be considered for measuring */ -}; - -struct ad9361_rf_phy; -struct ad9361_debugfs_entry { - struct ad9361_rf_phy *phy; - const char *propname; - void *out_value; - u32 val; - u8 size; - u8 cmd; -}; - -struct ad9361_dig_tune_data { - u32 bist_loopback_mode; - u32 bist_config; - u32 ensm_state; - u8 skip_mode; -}; - -struct refclk_scale { - struct clk_hw hw; - struct spi_device *spi; - struct ad9361_rf_phy *phy; - unsigned long rate; - u32 mult; - u32 div; - enum ad9361_clocks source; -}; - -struct ad9361_rf_phy_state; -struct ad9361_ext_band_ctl; - -struct ad9361_rf_phy { - struct spi_device *spi; - struct clk *clk_refin; - struct clk *clk_ext_lo_rx; - struct clk *clk_ext_lo_tx; - struct clk *clks[NUM_AD9361_CLKS]; - struct notifier_block clk_nb_tx; - struct notifier_block clk_nb_rx; - struct refclk_scale clk_priv[NUM_AD9361_CLKS]; - struct clk_onecell_data clk_data; - struct ad9361_phy_platform_data *pdata; - struct ad9361_debugfs_entry debugfs_entry[182]; - struct bin_attribute bin; - struct bin_attribute bin_gt; - struct iio_dev *indio_dev; - struct work_struct work; - struct completion complete; - struct gain_table_info *gt_info; - char *bin_attr_buf; - u32 ad9361_debugfs_entry_index; - - struct ad9361_ext_band_ctl *ext_band_ctl; - struct ad9361_rf_phy_state *state; -}; - -int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl); -int ad9361_clk_set_rate(struct clk *clk, unsigned long rate); -int ad9361_rssi_setup(struct ad9361_rf_phy *phy, - struct rssi_control *ctrl, - bool is_update); -int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi); -int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,u32 rf_rx_bw, u32 rf_tx_bw); - -ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, - char *buf, unsigned buflen); -int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable); -int ad9361_register_axi_converter(struct ad9361_rf_phy *phy); -struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi); -int ad9361_spi_read(struct spi_device *spi, u32 reg); -int ad9361_spi_write(struct spi_device *spi, u32 reg, u32 val); -int ad9361_bist_loopback(struct ad9361_rf_phy *phy, unsigned mode); -int ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode); -int ad9361_find_opt(u8 *field, u32 size, u32 *ret_start); -int ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy); -int ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy); -void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, u8 ensm_state); -void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, u8 ensm_state); -void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy); -int ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, - unsigned long freq); -int ad9361_set_trx_clock_chain_default(struct ad9361_rf_phy *phy); -int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags); -int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state); -int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num); -int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed); -int ad9361_write_bist_reg(struct ad9361_rf_phy *phy, u32 val); -bool ad9361_uses_rx2tx2(struct ad9361_rf_phy *phy); -int ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy, - struct ad9361_dig_tune_data *data); -int ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy); -int ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy); -bool ad9361_uses_lvds_mode(struct ad9361_rf_phy *phy); -int ad9361_set_rx_port(struct ad9361_rf_phy *phy, enum rx_port_sel sel); -int ad9361_set_tx_port(struct ad9361_rf_phy *phy, enum tx_port_sel sel); - -#ifdef CONFIG_AD9361_EXT_BAND_CONTROL -int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy); -int ad9361_adjust_rx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq); -int ad9361_adjust_tx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq); -void ad9361_unregister_ext_band_control(struct ad9361_rf_phy *phy); -#else -static inline int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy) -{ - return 0; -} -static inline int ad9361_adjust_rx_ext_band_settings( - struct ad9361_rf_phy *phy, u64 freq) -{ - return 0; -} -static inline int ad9361_adjust_tx_ext_band_settings( - struct ad9361_rf_phy *phy, u64 freq) -{ - return 0; -} -static inline void ad9361_unregister_ext_band_control( - struct ad9361_rf_phy *phy) -{} -#endif - -#endif - diff --git a/driver/ad9361/ad9361_conv.c b/driver/ad9361/ad9361_conv.c deleted file mode 100644 index 8848cf3..0000000 --- a/driver/ad9361/ad9361_conv.c +++ /dev/null @@ -1,821 +0,0 @@ -/* - * AD9361 Agile RF Transceiver - * - * Copyright 2013-2017 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "ad9361.h" - -#if IS_ENABLED(CONFIG_CF_AXI_ADC) -#include "cf_axi_adc.h" - -static void ad9361_set_intf_delay(struct ad9361_rf_phy *phy, bool tx, - unsigned int clock_delay, - unsigned int data_delay, bool clock_changed) -{ - if (clock_changed) - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_spi_write(phy->spi, - REG_RX_CLOCK_DATA_DELAY + (tx ? 1 : 0), - RX_DATA_DELAY(data_delay) | - DATA_CLK_DELAY(clock_delay)); - if (clock_changed) - ad9361_ensm_force_state(phy, ENSM_STATE_FDD); -} - -static unsigned int ad9361_num_phy_chan(struct axiadc_converter *conv) -{ - if (conv->chip_info->num_channels > 4) - return 4; - return conv->chip_info->num_channels; -} - -static int ad9361_check_pn(struct axiadc_converter *conv, bool tx, - unsigned int delay) -{ - struct axiadc_state *st = iio_priv(conv->indio_dev); - unsigned int num_chan = ad9361_num_phy_chan(conv); - unsigned int chan; - - for (chan = 0; chan < num_chan; chan++) - axiadc_write(st, ADI_REG_CHAN_STATUS(chan), - ADI_PN_ERR | ADI_PN_OOS); - mdelay(delay); - - if (!tx && !(axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS)) - return 1; - - for (chan = 0; chan < num_chan; chan++) { - if (axiadc_read(st, ADI_REG_CHAN_STATUS(chan))) - return 1; - } - - return 0; -} - -ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, - char *buf, unsigned buflen) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct ad9361_dig_tune_data data; - int i, j, len = 0; - int ret; - u8 field[16][16]; - u8 rx; - - if (!conv) - return -ENODEV; - - ret = ad9361_get_dig_tune_data(phy, &data); - if (ret < 0) - return ret; - - dev_dbg(&phy->spi->dev, "%s:\n", __func__); - - rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); - - /* Mute TX, we don't want to transmit the PRBS */ - ad9361_tx_mute(phy, 1); - - ad9361_ensm_mode_disable_pinctrl(phy); - - ad9361_bist_loopback(phy, 0); - ad9361_bist_prbs(phy, BIST_INJ_RX); - - for (i = 0; i < 16; i++) { - for (j = 0; j < 16; j++) { - ad9361_set_intf_delay(phy, false, i, j, j == 0); - field[j][i] = ad9361_check_pn(conv, false, 1); - } - } - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx); - ad9361_bist_loopback(phy, data.bist_loopback_mode); - ad9361_write_bist_reg(phy, data.bist_config); - - ad9361_ensm_mode_restore_pinctrl(phy); - ad9361_ensm_restore_state(phy, data.ensm_state); - - ad9361_tx_mute(phy, 0); - - len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n", - clk_get_rate(phy->clks[RX_SAMPL_CLK])); - len += snprintf(buf + len, buflen, "DC"); - for (i = 0; i < 16; i++) - len += snprintf(buf + len, buflen, "%x:", i); - len += snprintf(buf + len, buflen, "\n"); - - for (i = 0; i < 16; i++) { - len += snprintf(buf + len, buflen, "%x:", i); - for (j = 0; j < 16; j++) { - len += snprintf(buf + len, buflen, "%c ", - (field[i][j] ? '.' : 'o')); - } - len += snprintf(buf + len, buflen, "\n"); - } - len += snprintf(buf + len, buflen, "\n"); - - return len; -} -EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis); - -static ssize_t samples_pps_read(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, char *buf) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - struct axiadc_state *st = iio_priv(conv->indio_dev); - u32 config, val, mode; - - config = axiadc_read(st, ADI_REG_CONFIG); - - if (!(config & ADI_PPS_RECEIVER_ENABLE)) - return -ENODEV; - - val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS_STATUS); - if (val & ADI_CLOCKS_PER_PPS_STAT_INVAL) - return -ETIMEDOUT; - - mode = axiadc_read(st, ADI_REG_CNTRL); - - /* - * Counts DATA_CLK cycles therefore needs to be corrected - * for 2rx2tx mode or for LVDS vs. CMOS mode. - */ - - val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS); - - if (!(mode & ADI_R1_MODE)) - val /= 2; - - if (!(config & ADI_CMOS_OR_LVDS_N)) - val /= 2; - - return sprintf(buf, "%u\n", val); -} - -/* - * Returns the number of samples during a 1PPS (Pulse Per Second) interval. - */ - -static struct iio_chan_spec_ext_info axiadc_ext_info[] = { - { - .name = "samples_pps", - .read = samples_pps_read, - .shared = IIO_SHARED_BY_TYPE, - }, - {}, -}; - -#define AIM_CHAN(_chan, _si, _bits, _sign) \ - { .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .channel = _chan, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ - BIT(IIO_CHAN_INFO_CALIBBIAS) | \ - BIT(IIO_CHAN_INFO_CALIBPHASE), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ - .ext_info = axiadc_ext_info, \ - .scan_index = _si, \ - .scan_type = { \ - .sign = _sign, \ - .realbits = _bits, \ - .storagebits = 16, \ - .shift = 0, \ - }, \ - } - -#define AIM_MC_CHAN(_chan, _si, _bits, _sign) \ - { .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .channel = _chan, \ - .scan_index = _si, \ - .scan_type = { \ - .sign = _sign, \ - .realbits = _bits, \ - .storagebits = 16, \ - .shift = 0, \ - }, \ - } - - -static const unsigned long ad9361_2x2_available_scan_masks[] = { - 0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, /* 1 & 2 chan */ - 0x10, 0x20, 0x40, 0x80, 0x30, 0xC0, /* 1 & 2 chan */ - 0x33, 0xCC, 0xC3, 0x3C, 0x0F, 0xF0, /* 4 chan */ - 0xFF, /* 8 chan */ - 0x00, -}; - -static const unsigned long ad9361_available_scan_masks[] = { - 0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, 0x0F, - 0x00, -}; - -static const struct axiadc_chip_info axiadc_chip_info_tbl[] = { - [ID_AD9361] = { - .name = "AD9361", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 4, - .scan_masks = ad9361_available_scan_masks, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - .channel[2] = AIM_CHAN(2, 2, 12, 'S'), - .channel[3] = AIM_CHAN(3, 3, 12, 'S'), - }, - [ID_AD9361_2] = { /* MCS/MIMO 2x AD9361 */ - .name = "AD9361-2", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 8, - .num_shadow_slave_channels = 4, - .scan_masks = ad9361_2x2_available_scan_masks, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - .channel[2] = AIM_CHAN(2, 2, 12, 'S'), - .channel[3] = AIM_CHAN(3, 3, 12, 'S'), - .channel[4] = AIM_MC_CHAN(4, 4, 12, 'S'), - .channel[5] = AIM_MC_CHAN(5, 5, 12, 'S'), - .channel[6] = AIM_MC_CHAN(6, 6, 12, 'S'), - .channel[7] = AIM_MC_CHAN(7, 7, 12, 'S'), - }, - [ID_AD9364] = { - .name = "AD9364", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 2, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - }, - -}; - -static int ad9361_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long m) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - - switch (m) { - case IIO_CHAN_INFO_SAMP_FREQ: - if (!conv->clk) - return -ENODEV; - - *val = conv->adc_clk = clk_get_rate(conv->clk); - - return IIO_VAL_INT; - - } - return -EINVAL; -} - -static int ad9361_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - unsigned long r_clk; - int ret; - - switch (mask) { - case IIO_CHAN_INFO_SAMP_FREQ: - if (!conv->clk) - return -ENODEV; - - if (chan->extend_name) - return -ENODEV; - - r_clk = clk_round_rate(conv->clk, val); - if (r_clk < 0 || r_clk > conv->chip_info->max_rate) { - dev_warn(&conv->spi->dev, - "Error setting ADC sample rate %ld", r_clk); - return -EINVAL; - } - - ret = clk_set_rate(conv->clk, r_clk); - if (ret < 0) - return ret; - - return 0; - break; - default: - return -EINVAL; - } - - return 0; -} - -int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st; - unsigned reg, addr, chan, version; - - if (!conv) - return -ENODEV; - - st = iio_priv(conv->indio_dev); - version = axiadc_read(st, 0x4000); - - /* Still there but implemented a bit different */ - if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) - addr = 0x4418; - else - addr = 0x4414; - - for (chan = 0; chan < conv->chip_info->num_channels; chan++) { - reg = axiadc_read(st, addr + (chan) * 0x40); - - if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) { - if (enable) { - if (reg != 0x8) { - conv->scratch_reg[chan] = reg; - reg = 0x8; - } - } else if (reg == 0x8) { - reg = conv->scratch_reg[chan]; - } - } else { - /* DAC_LB_ENB If set enables loopback of receive data */ - if (enable) - reg |= BIT(1); - else - reg &= ~BIT(1); - } - axiadc_write(st, addr + (chan) * 0x40, reg); - } - - return 0; -} -EXPORT_SYMBOL(ad9361_hdl_loopback); - -static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane, - unsigned val, bool tx) -{ - if (tx) { - if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8) - axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val); - else - return -ENODEV; - } else { - axiadc_idelay_set(st, lane, val); - } - - return 0; -} - -static int ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int ret = 0, i; - - for (i = 0; i < 7; i++) - ret |= ad9361_iodelay_set(st, i, 15, tx); - - return 0; -} - -static int ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int i, j; - u32 s0, c0; - u8 field[32]; - - for (i = 0; i < 7; i++) { - for (j = 0; j < 32; j++) { - ad9361_iodelay_set(st, i, j, tx); - mdelay(1); - field[j] = ad9361_check_pn(conv, tx, 10); - } - - c0 = ad9361_find_opt(&field[0], 32, &s0); - ad9361_iodelay_set(st, i, s0 + c0 / 2, tx); - - dev_info(&phy->spi->dev, - "%s Lane %d, window cnt %d , start %d, IODELAY set to %d\n", - tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2); - - } - - return 0; -} - -static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy, - u8 field[][16], bool tx, - int sel_clk, int sel_data) -{ - int i, j; - char c; - - pr_info("SAMPL CLK: %lu tuning: %s\n", - clk_get_rate(phy->clks[RX_SAMPL_CLK]), tx ? "TX" : "RX"); - pr_info(" "); - for (i = 0; i < 16; i++) - pr_cont("%x:", i); - pr_cont("\n"); - - for (i = 0; i < 2; i++) { - pr_info("%x:", i); - for (j = 0; j < 16; j++) { - if (field[i][j]) - c = '#'; - else if ((i == 0 && j == sel_data) || - (i == 1 && j == sel_clk)) - c = 'O'; - else - c = 'o'; - pr_cont("%c ", c); - } - pr_cont("\n"); - } -} - -static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy, - unsigned long max_freq, - enum dig_tune_flags flags, bool tx) -{ - //static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; //some low end FPGA, such as z7020, lvds ADC interface seems not stable enough to support 61.44Msps - static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U}; - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - unsigned int s0, s1, c0, c1; - unsigned int i, j, r; - bool half_data_rate; - u8 field[2][16]; - - if (ad9361_uses_lvds_mode(phy) || !ad9361_uses_rx2tx2(phy)) - half_data_rate = false; - else - half_data_rate = true; - - memset(field, 0, 32); - for (r = 0; r < (max_freq ? ARRAY_SIZE(rates) : 1); r++) { - if (max_freq) - ad9361_set_trx_clock_chain_freq(phy, - half_data_rate ? rates[r] / 2 : rates[r]); - - for (i = 0; i < 2; i++) { - for (j = 0; j < 16; j++) { - /* - * i == 0: clock delay = 0, data delay from 0 to 15 - * i == 1: clock delay = 15, data delay from 15 to 0 - */ - ad9361_set_intf_delay(phy, tx, i ? 15 : 0, - i ? 15 - j : j, j == 0); - field[i][j] |= ad9361_check_pn(conv, tx, 4); - } - } - - if ((flags & BE_MOREVERBOSE) && max_freq) { - ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1); - } - } - - c0 = ad9361_find_opt(&field[0][0], 16, &s0); - c1 = ad9361_find_opt(&field[1][0], 16, &s1); - - if (!c0 && !c1) { - ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1); - dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__, - tx ? "TX" : "RX"); - return -EIO; - } else if (flags & BE_VERBOSE) { - ad9361_dig_tune_verbose_print(phy, field, tx, - c1 > c0 ? (s1 + c1 / 2) : -1, - c1 > c0 ? -1 : (s0 + c0 / 2)); - } - - if (c1 > c0) - ad9361_set_intf_delay(phy, tx, s1 + c1 / 2, 0, true); - else - ad9361_set_intf_delay(phy, tx, 0, s0 + c0 / 2, true); - - return 0; -} - -static int ad9361_dig_tune_rx(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int ret; - - ad9361_bist_loopback(phy, 0); - ad9361_bist_prbs(phy, BIST_INJ_RX); - - ret = ad9361_dig_tune_delay(phy, max_freq, flags, false); - if (flags & DO_IDELAY) - ad9361_dig_tune_iodelay(phy, false); - - axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); - axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - return ret; -} - -static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - u32 saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4]; - unsigned int chan, num_chan; - unsigned int hdl_dac_version; - u32 tmp, saved = 0; - int ret; - - num_chan = ad9361_num_phy_chan(conv); - hdl_dac_version = axiadc_read(st, 0x4000); - - ad9361_bist_prbs(phy, BIST_DISABLE); - ad9361_bist_loopback(phy, 1); - axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - for (chan = 0; chan < num_chan; chan++) { - saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan)); - axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), - ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | - ADI_ENABLE | ADI_IQCOR_ENB); - axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM); - saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40); - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) { - saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40); - axiadc_write(st, 0x4418 + (chan) * 0x40, 9); - axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */ - axiadc_write(st, 0x4044, 1); - } else { - axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */ - } - } - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) { - saved = tmp = axiadc_read(st, 0x4048); - tmp &= ~0xF; - tmp |= 1; - axiadc_write(st, 0x4048, tmp); - } - - ret = ad9361_dig_tune_delay(phy, max_freq, flags, true); - if (flags & DO_ODELAY) - ad9361_dig_tune_iodelay(phy, true); - - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) - axiadc_write(st, 0x4048, saved); - - for (chan = 0; chan < num_chan; chan++) { - axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), - saved_chan_ctrl0[chan]); - axiadc_set_pnsel(st, chan, ADC_PN9); - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) { - axiadc_write(st, 0x4418 + chan * 0x40, - saved_dsel[chan]); - axiadc_write(st, 0x4044, 1); - } - - axiadc_write(st, 0x4414 + chan * 0x40, saved_chan_ctrl6[chan]); - } - - return ret; -} - -int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct ad9361_dig_tune_data data; - struct axiadc_state *st; - bool restore = false; - int ret = 0; - - if (!conv) - return -ENODEV; - - ret = ad9361_get_dig_tune_data(phy, &data); - if (ret < 0) - return ret; - - dev_dbg(&phy->spi->dev, "%s: freq %lu flags 0x%X\n", __func__, - max_freq, flags); - - st = iio_priv(conv->indio_dev); - - if ((data.skip_mode == SKIP_ALL) || - (flags & RESTORE_DEFAULT)) { - /* skip completely and use defaults */ - restore = true; - } else { - /* Mute TX, we don't want to transmit the PRBS */ - ad9361_tx_mute(phy, 1); - - ad9361_ensm_mode_disable_pinctrl(phy); - - if (flags & DO_IDELAY) - ad9361_midscale_iodelay(phy, false); - - if (flags & DO_ODELAY) - ad9361_midscale_iodelay(phy, true); - - ret = ad9361_dig_tune_rx(phy, max_freq, flags); - if (ret == 0 && (data.skip_mode == TUNE_RX_TX)) - ret = ad9361_dig_tune_tx(phy, max_freq, flags); - - ad9361_bist_loopback(phy, data.bist_loopback_mode); - ad9361_write_bist_reg(phy, data.bist_config); - - if (ret == -EIO) - restore = true; - if (!max_freq) - ret = 0; - } - - if (restore) { - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_write_clock_data_delays(phy); - } else if (!(flags & SKIP_STORE_RESULT)) { - ad9361_read_clock_data_delays(phy); - } - - ad9361_ensm_mode_restore_pinctrl(phy); - ad9361_ensm_restore_state(phy, data.ensm_state); - - axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); - axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - ad9361_tx_mute(phy, 0); - - return ret; -} -EXPORT_SYMBOL(ad9361_dig_tune); - -static int ad9361_post_setup(struct iio_dev *indio_dev) -{ - struct axiadc_state *st = iio_priv(indio_dev); - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - struct ad9361_rf_phy *phy = conv->phy; - bool rx2tx2 = ad9361_uses_rx2tx2(phy); - unsigned tmp, num_chan, flags; - int i, ret; - - num_chan = ad9361_num_phy_chan(conv); - - conv->indio_dev = indio_dev; - axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE); - tmp = axiadc_read(st, 0x4048); - - if (!rx2tx2) { - axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */ - axiadc_write(st, 0x404c, - ad9361_uses_lvds_mode(phy) ? 1 : 0); /* RATE */ - } else { - tmp &= ~BIT(5); - axiadc_write(st, 0x4048, tmp); - axiadc_write(st, 0x404c, - ad9361_uses_lvds_mode(phy) ? 3 : 1); /* RATE */ - } - - for (i = 0; i < num_chan; i++) { - axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i), - ADI_DCFILT_OFFSET(0)); - axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i), - (i & 1) ? 0x00004000 : 0x40000000); - axiadc_write(st, ADI_REG_CHAN_CNTRL(i), - ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | - ADI_ENABLE | ADI_IQCOR_ENB); - } - - flags = 0; - - ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ? - 0 : 61440000, flags); - if (ret < 0) - goto error; - - if (flags & (DO_IDELAY | DO_ODELAY)) { - ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ? - 0 : 61440000, flags & BE_VERBOSE); - if (ret < 0) - goto error; - } - - ret = ad9361_set_trx_clock_chain_default(phy); - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_ensm_restore_prev_state(phy); - - return 0; - -error: - spi_set_drvdata(phy->spi, NULL); - return ret; -} - -int ad9361_register_axi_converter(struct ad9361_rf_phy *phy) -{ - struct axiadc_converter *conv; - struct spi_device *spi = phy->spi; - int ret; - - conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL); - if (conv == NULL) - return -ENOMEM; - - conv->id = ad9361_spi_read(spi, REG_PRODUCT_ID) & PRODUCT_ID_MASK; - if (conv->id != PRODUCT_ID_9361) { - dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", conv->id); - ret = -ENODEV; - goto out; - } - - conv->chip_info = &axiadc_chip_info_tbl[ - (spi_get_device_id(spi)->driver_data == ID_AD9361_2) ? - ID_AD9361_2 : ad9361_uses_rx2tx2(phy) ? ID_AD9361 : ID_AD9364]; - conv->write_raw = ad9361_write_raw; - conv->read_raw = ad9361_read_raw; - conv->post_setup = ad9361_post_setup; - conv->spi = spi; - conv->phy = phy; - - conv->clk = phy->clks[RX_SAMPL_CLK]; - conv->adc_clk = clk_get_rate(conv->clk); - - spi_set_drvdata(spi, conv); /* Take care here */ - - return 0; -out: - spi_set_drvdata(spi, NULL); - return ret; -} -EXPORT_SYMBOL(ad9361_register_axi_converter); - -struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi) -{ - struct axiadc_converter *conv = spi_get_drvdata(spi); - return conv->phy; -} -EXPORT_SYMBOL(ad9361_spi_to_phy); - -#else /* CONFIG_CF_AXI_ADC */ - -int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - return -ENODEV; -} -EXPORT_SYMBOL(ad9361_dig_tune); - -ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, - char *buf, unsigned buflen) -{ - return 0; -} -EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis); - -int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) -{ - return -ENODEV; -} -EXPORT_SYMBOL(ad9361_hdl_loopback); - -int ad9361_register_axi_converter(struct ad9361_rf_phy *phy) -{ - struct spi_device *spi = phy->spi; - spi_set_drvdata(spi, phy); /* Take care here */ - - return 0; -} -EXPORT_SYMBOL(ad9361_register_axi_converter); - -struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi) -{ - return spi_get_drvdata(spi); -} -EXPORT_SYMBOL(ad9361_spi_to_phy); - -#endif /* CONFIG_CF_AXI_ADC */ diff --git a/driver/ad9361/ad9361_private.h b/driver/ad9361/ad9361_private.h deleted file mode 100644 index d63c17f..0000000 --- a/driver/ad9361/ad9361_private.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * AD9361 - Private definitions to be used only in the ad9361.c file - * - * Copyright 2013-2018 Analog Devices Inc. - * - * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - * - * Licensed under the GPL-2. - */ - -#ifndef IIO_AD9361_PRIVATE_H_ -#define IIO_AD9361_PRIVATE_H_ - -#ifndef IIO_AD9361_USE_PRIVATE_H_ -#error "Please do not include ad9361_private.h; use ad9361.h instead" -#endif - -#include "ad9361.h" - -/* - * Driver - */ - -enum rx_gain_table_type { - RXGAIN_FULL_TBL, - RXGAIN_SPLIT_TBL, -}; - -enum rx_gain_table_name { - TBL_200_1300_MHZ, - TBL_1300_4000_MHZ, - TBL_4000_6000_MHZ, - RXGAIN_TBLS_END, -}; - -enum fir_dest { - FIR_TX1 = 0x01, - FIR_TX2 = 0x02, - FIR_TX1_TX2 = 0x03, - FIR_RX1 = 0x81, - FIR_RX2 = 0x82, - FIR_RX1_RX2 = 0x83, - FIR_IS_RX = 0x80, -}; - -struct rf_gain_ctrl { - u32 ant; - u8 mode; -}; - -enum rf_gain_ctrl_mode { - RF_GAIN_MGC, - RF_GAIN_FASTATTACK_AGC, - RF_GAIN_SLOWATTACK_AGC, - RF_GAIN_HYBRID_AGC -}; - -enum f_agc_target_gain_index_type { - MAX_GAIN, - SET_GAIN, - OPTIMIZED_GAIN, - NO_GAIN_CHANGE, -}; - -struct gain_control { - enum rf_gain_ctrl_mode rx1_mode; - enum rf_gain_ctrl_mode rx2_mode; - - /* Common */ - u8 adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */ - u8 adc_small_overload_thresh; /* 0..255, 0x105 */ - u8 adc_large_overload_thresh; /* 0..255, 0x104 */ - - u16 lmt_overload_high_thresh; /* 16..800 mV, 0x107 */ - u16 lmt_overload_low_thresh; /* 16..800 mV, 0x108 */ - u16 dec_pow_measuremnt_duration; /* Samples, 0x15C */ - u8 low_power_thresh; /* -64..0 dBFS, 0x114 */ - bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */ - - bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */ - u8 max_dig_gain; /* 0..31 */ - - /* MGC */ - bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */ - bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */ - - u8 mgc_inc_gain_step; /* 1..8 */ - u8 mgc_dec_gain_step; /* 1..8 */ - u8 mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */ - - /* AGC */ - u8 agc_attack_delay_extra_margin_us; /* 0..31 us */ - - u8 agc_outer_thresh_high; - u8 agc_outer_thresh_high_dec_steps; - u8 agc_inner_thresh_high; - u8 agc_inner_thresh_high_dec_steps; - u8 agc_inner_thresh_low; - u8 agc_inner_thresh_low_inc_steps; - u8 agc_outer_thresh_low; - u8 agc_outer_thresh_low_inc_steps; - - u8 adc_small_overload_exceed_counter; /* 0..15, 0x122 */ - u8 adc_large_overload_exceed_counter; /* 0..15, 0x122 */ - u8 adc_large_overload_inc_steps; /* 0..15, 0x106 */ - - bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */ - - u8 lmt_overload_large_exceed_counter; /* 0..15, 0x121 */ - u8 lmt_overload_small_exceed_counter; /* 0..15, 0x121 */ - u8 lmt_overload_large_inc_steps; /* 0..7, 0x121 */ - - u8 dig_saturation_exceed_counter; /* 0..15, 0x128 */ - u8 dig_gain_step_size; /* 1..8, 0x100 */ - bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */ - - u32 gain_update_interval_us; /* in us */ - bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */ - bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */ - - /* - * Fast AGC - */ - u32 f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */ - u32 f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */ - /* Fast AGC - Low Power */ - bool f_agc_allow_agc_gain_increase; /* 0x110:1 */ - u8 f_agc_lp_thresh_increment_time; /* 0x11B RX samples */ - u8 f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */ - - /* Fast AGC - Lock Level */ - u8 f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */ - bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */ - u8 f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */ - /* Fast AGC - Peak Detectors and Final Settling */ - u8 f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/ - u8 f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/ - u8 f_agc_final_overrange_count; /* 0x116:5 0..7 */ - /* Fast AGC - Final Power Test */ - bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */ - /* Fast AGC - Unlocking the Gain */ - /* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */ - enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */ - bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */ - u8 f_agc_optimized_gain_offset; /*0x116 0..15 steps */ - bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */ - u8 f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */ - bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */ - bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */ - u8 f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */ - u8 f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */ - bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */ - bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */ - bool f_agc_rst_gla_en_agc_pulled_high_en; - /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */ - - enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */ - u8 f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/ - u8 f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */ - -}; - -struct auxdac_control { - u16 dac1_default_value; - u16 dac2_default_value; - - bool auxdac_manual_mode_en; - - bool dac1_in_rx_en; - bool dac1_in_tx_en; - bool dac1_in_alert_en; - - bool dac2_in_rx_en; - bool dac2_in_tx_en; - bool dac2_in_alert_en; - - u8 dac1_rx_delay_us; - u8 dac1_tx_delay_us; - u8 dac2_rx_delay_us; - u8 dac2_tx_delay_us; -}; - -#if 0 -enum rssi_restart_mode { - AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN, - EN_AGC_PIN_IS_PULLED_HIGH, - ENTERS_RX_MODE, - GAIN_CHANGE_OCCURS, - SPI_WRITE_TO_REGISTER, - GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH, -}; - -struct rssi_control { - enum rssi_restart_mode restart_mode; - bool rssi_unit_is_rx_samples; /* default unit is time */ - u32 rssi_delay; - u32 rssi_wait; - u32 rssi_duration; -}; -#endif - -struct rx_gain_info { - enum rx_gain_table_type tbl_type; - int starting_gain_db; - int max_gain_db; - int gain_step_db; - int max_idx; - int idx_step_offset; -}; - -struct port_control { - u8 pp_conf[3]; - u8 rx_clk_data_delay; - u8 tx_clk_data_delay; - u8 digital_io_ctrl; - u8 lvds_bias_ctrl; - u8 lvds_invert[2]; -}; - -#if 0 -struct ctrl_outs_control { - u8 index; - u8 en_mask; -}; -#endif - -struct elna_control { - u16 gain_mdB; - u16 bypass_loss_mdB; - u32 settling_delay_ns; - bool elna_1_control_en; /* GPO0 */ - bool elna_2_control_en; /* GPO1 */ - bool elna_in_gaintable_all_index_en; -}; - -struct auxadc_control { - s8 offset; - u32 temp_time_inteval_ms; - u32 temp_sensor_decimation; - bool periodic_temp_measuremnt; - u32 auxadc_clock_rate; - u32 auxadc_decimation; -}; - -struct gpo_control { - u32 gpo_manual_mode_enable_mask; - bool gpo_manual_mode_en; - bool gpo0_inactive_state_high_en; - bool gpo1_inactive_state_high_en; - bool gpo2_inactive_state_high_en; - bool gpo3_inactive_state_high_en; - bool gpo0_slave_rx_en; - bool gpo0_slave_tx_en; - bool gpo1_slave_rx_en; - bool gpo1_slave_tx_en; - bool gpo2_slave_rx_en; - bool gpo2_slave_tx_en; - bool gpo3_slave_rx_en; - bool gpo3_slave_tx_en; - u8 gpo0_rx_delay_us; - u8 gpo0_tx_delay_us; - u8 gpo1_rx_delay_us; - u8 gpo1_tx_delay_us; - u8 gpo2_rx_delay_us; - u8 gpo2_tx_delay_us; - u8 gpo3_rx_delay_us; - u8 gpo3_tx_delay_us; -}; - -struct tx_monitor_control { - bool tx_mon_track_en; - bool one_shot_mode_en; - u32 low_high_gain_threshold_mdB; - u8 low_gain_dB; - u8 high_gain_dB; - u16 tx_mon_delay; - u16 tx_mon_duration; - u8 tx1_mon_front_end_gain; - u8 tx2_mon_front_end_gain; - u8 tx1_mon_lo_cm; - u8 tx2_mon_lo_cm; -}; - -enum ad9361_pdata_rx_freq { - BBPLL_FREQ, - ADC_FREQ, - R2_FREQ, - R1_FREQ, - CLKRF_FREQ, - RX_SAMPL_FREQ, - NUM_RX_CLOCKS, -}; - -enum ad9361_pdata_tx_freq { - IGNORE, - DAC_FREQ, - T2_FREQ, - T1_FREQ, - CLKTF_FREQ, - TX_SAMPL_FREQ, - NUM_TX_CLOCKS, -}; - -enum ad9361_clkout { - CLKOUT_DISABLE, - BUFFERED_XTALN_DCXO, - ADC_CLK_DIV_2, - ADC_CLK_DIV_3, - ADC_CLK_DIV_4, - ADC_CLK_DIV_8, - ADC_CLK_DIV_16, -}; - -enum synth_pd_ctrl { - LO_DONTCARE, - LO_OFF, - LO_ON, -}; - -struct ad9361_phy_platform_data { - bool rx2tx2; - bool fdd; - bool fdd_independent_mode; - bool split_gt; - bool use_extclk; - bool ensm_pin_pulse_mode; - bool ensm_pin_ctrl; - bool debug_mode; - bool tdd_use_dual_synth; - bool tdd_skip_vco_cal; - bool use_ext_rx_lo; - bool use_ext_tx_lo; - bool rx1rx2_phase_inversion_en; - bool qec_tracking_slow_mode_en; - bool dig_interface_tune_fir_disable; - bool lo_powerdown_managed_en; - u8 dc_offset_update_events; - u8 dc_offset_attenuation_high; - u8 dc_offset_attenuation_low; - u8 rf_dc_offset_count_high; - u8 rf_dc_offset_count_low; - u8 dig_interface_tune_skipmode; - u32 dcxo_coarse; - u32 dcxo_fine; - bool rf_rx_input_sel_lock; - bool rf_tx_output_sel_lock; - u32 rx1tx1_mode_use_rx_num; - u32 rx1tx1_mode_use_tx_num; - unsigned long rx_path_clks[NUM_RX_CLOCKS]; - unsigned long tx_path_clks[NUM_TX_CLOCKS]; - u32 trx_synth_max_fref; - u64 rx_synth_freq; - u64 tx_synth_freq; - u32 rf_rx_bandwidth_Hz; - u32 rf_tx_bandwidth_Hz; - int tx_atten; - bool update_tx_gain_via_alert; - u32 rx_fastlock_delay_ns; - u32 tx_fastlock_delay_ns; - bool trx_fastlock_pinctrl_en[2]; - - enum ad9361_clkout ad9361_clkout_mode; - - struct gain_control gain_ctrl; - struct rssi_control rssi_ctrl; - u32 rssi_lna_err_tbl[4]; - u32 rssi_mixer_err_tbl[16]; - u32 rssi_gain_step_calib_reg_val[5]; - bool rssi_skip_calib; - struct port_control port_ctrl; - struct ctrl_outs_control ctrl_outs_ctrl; - struct elna_control elna_ctrl; - struct auxadc_control auxadc_ctrl; - struct auxdac_control auxdac_ctrl; - struct gpo_control gpo_ctrl; - struct tx_monitor_control txmon_ctrl; - - struct gpio_desc *reset_gpio; - /* MCS SYNC */ - struct gpio_desc *sync_gpio; - struct gpio_desc *cal_sw1_gpio; - struct gpio_desc *cal_sw2_gpio; - -}; - -struct rf_rx_gain { - u32 ant; /* Antenna number to read gain */ - s32 gain_db; /* gain value in dB */ - u32 fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */ - u32 lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/ - u32 lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/ - u32 digital_gain; /* Digital gain in dB / index */ - /* Debug only */ - u32 lna_index; /* LNA Index (Split GT mode only) */ - u32 tia_index; /* TIA Index (Split GT mode only) */ - u32 mixer_index; /* MIXER Index (Split GT mode only) */ - -}; -#if 0 -struct rf_rssi { - u32 ant; /* Antenna number for which RSSI is reported */ - u32 symbol; /* Runtime RSSI */ - u32 preamble; /* Initial RSSI */ - s32 multiplier; /* Multiplier to convert reported RSSI */ - u8 duration; /* Duration to be considered for measuring */ -}; -#endif - -struct SynthLUT { - u16 VCO_MHz; - u8 VCO_Output_Level; - u8 VCO_Varactor; - u8 VCO_Bias_Ref; - u8 VCO_Bias_Tcf; - u8 VCO_Cal_Offset; - u8 VCO_Varactor_Reference; - u8 Charge_Pump_Current; - u8 LF_C2; - u8 LF_C1; - u8 LF_R1; - u8 LF_C3; - u8 LF_R3; -}; - -#define SYNTH_LUT_SIZE 53 - -enum { - LUT_FTDD_40, - LUT_FTDD_60, - LUT_FTDD_80, - LUT_FTDD_ENT, -}; - -struct ad9361_fastlock_entry { -#define FASTLOOK_INIT 1 - u8 flags; - u8 alc_orig; - u8 alc_written; -}; - -struct ad9361_fastlock { - u8 save_profile; - u8 current_profile[2]; - struct ad9361_fastlock_entry entry[2][8]; -}; - -struct ad9361_rf_phy_state { - u8 prev_ensm_state; - u8 curr_ensm_state; - u8 cached_rx_rfpll_div; - u8 cached_tx_rfpll_div; - u8 cached_synth_pd[2]; - int tx_quad_lpf_tia_match; - int current_table; - int rx_sampl_freq_avail[3]; - int tx_sampl_freq_avail[3]; - int rx_gain_avail[3]; - - bool ensm_pin_ctl_en; - - bool auto_cal_en; - bool manual_tx_quad_cal_en; - u64 last_tx_quad_cal_freq; - u32 last_tx_quad_cal_phase; - u64 current_tx_lo_freq; - u64 current_rx_lo_freq; - bool current_tx_use_tdd_table; - bool current_rx_use_tdd_table; - unsigned long current_rx_path_clks[NUM_RX_CLOCKS]; - unsigned long current_tx_path_clks[NUM_TX_CLOCKS]; - unsigned long flags; - unsigned long cal_threshold_freq; - u32 current_rx_bw_Hz; - u32 current_tx_bw_Hz; - u32 rxbbf_div; - u32 rate_governor; - bool bypass_rx_fir; - bool bypass_tx_fir; - bool rx_eq_2tx; - bool filt_valid; - unsigned long filt_rx_path_clks[NUM_RX_CLOCKS]; - unsigned long filt_tx_path_clks[NUM_TX_CLOCKS]; - u32 filt_rx_bw_Hz; - u32 filt_tx_bw_Hz; - u8 tx_fir_int; - u8 tx_fir_ntaps; - u8 rx_fir_dec; - u8 rx_fir_ntaps; - u8 agc_mode[2]; - bool rfdc_track_en; - bool bbdc_track_en; - bool quad_track_en; - bool txmon_tdd_en; - u16 auxdac1_value; - u16 auxdac2_value; - u32 tx1_atten_cached; - u32 tx2_atten_cached; - u8 bist_loopback_mode; - u8 bist_config; - u32 rf_rx_input_sel; - u32 rf_tx_output_sel; - - struct ad9361_fastlock fastlock; -}; - -#endif - diff --git a/driver/ad9361/ad9361_regs.h b/driver/ad9361/ad9361_regs.h deleted file mode 100644 index 6c01098..0000000 --- a/driver/ad9361/ad9361_regs.h +++ /dev/null @@ -1,2831 +0,0 @@ -/* - * AD9361 - * - * Copyright 2013-2018 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#ifndef IIO_AD9361_REGS_H_ -#define IIO_AD9361_REGS_H_ - -#define REG_SPI_CONF 0x000 /* SPI Configuration */ -#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001 /* Multi-Chip Sync and Tx Mon Control */ -#define REG_TX_ENABLE_FILTER_CTRL 0x002 /* Tx Enable & Filter Control */ -#define REG_RX_ENABLE_FILTER_CTRL 0x003 /* Rx Enable & Filter Control */ -#define REG_INPUT_SELECT 0x004 /* Input Select */ -#define REG_RFPLL_DIVIDERS 0x005 /* RFPLL Dividers */ -#define REG_RX_CLOCK_DATA_DELAY 0x006 /* Rx Clock & Data Delay */ -#define REG_TX_CLOCK_DATA_DELAY 0x007 /* Tx Clock & Data Delay */ -#define REG_CLOCK_ENABLE 0x009 /* Clock Enable */ -#define REG_BBPLL 0x00A /* BBPLL */ -#define REG_TEMP_OFFSET 0x00B /* Offset */ -#define REG_START_TEMP_READING 0x00C /* Start Temp Reading */ -#define REG_TEMP_SENSE2 0x00D /* Temp Sense2 */ -#define REG_TEMPERATURE 0x00E /* Temperature */ -#define REG_TEMP_SENSOR_CONFIG 0x00F /* Temp Sensor Config */ -#define REG_PARALLEL_PORT_CONF_1 0x010 /* Parallel Port Configuration 1 */ -#define REG_PARALLEL_PORT_CONF_2 0x011 /* Parallel Port Configuration 2 */ -#define REG_PARALLEL_PORT_CONF_3 0x012 /* Parallel Port Configuration 3 */ -#define REG_ENSM_MODE 0x013 /* ENSM Mode */ -#define REG_ENSM_CONFIG_1 0x014 /* ENSM Config 1 */ -#define REG_ENSM_CONFIG_2 0x015 /* ENSM Config 2 */ -#define REG_CALIBRATION_CTRL 0x016 /* Calibration Control */ -#define REG_STATE 0x017 /* State */ -#define REG_AUXDAC_1_WORD 0x018 /* AuxDAC 1 Word */ -#define REG_AUXDAC_2_WORD 0x019 /* AuxDAC 2 Word */ -#define REG_AUXDAC_1_CONFIG 0x01A /* AuxDAC 1 Config */ -#define REG_AUXDAC_2_CONFIG 0x01B /* AuxDAC 2 Config */ -#define REG_AUXADC_CLOCK_DIVIDER 0x01C /* AuxADC Clock Divider */ -#define REG_AUXADC_CONFIG 0x01D /* Aux ADC Config */ -#define REG_AUXADC_WORD_MSB 0x01E /* AuxADC Word MSB */ -#define REG_AUXADC_LSB 0x01F /* AuxADC LSB */ -#define REG_AUTO_GPO 0x020 /* Auto GPO */ -#define REG_AGC_GAIN_LOCK_DELAY 0x021 /* AGC Gain Lock Delay */ -#define REG_AGC_ATTACK_DELAY 0x022 /* AGC Attack Delay */ -#define REG_AUXDAC_ENABLE_CTRL 0x023 /* AuxDAC Enable Control */ -#define REG_RX_LOAD_SYNTH_DELAY 0x024 /* RX Load Synth Delay */ -#define REG_TX_LOAD_SYNTH_DELAY 0x025 /* TX Load Synth Delay */ -#define REG_EXTERNAL_LNA_CTRL 0x026 /* External LNA control */ -#define REG_GPO_FORCE_AND_INIT 0x027 /* GPO Force and Init */ -#define REG_GPO0_RX_DELAY 0x028 /* GPO0 Rx delay */ -#define REG_GPO1_RX_DELAY 0x029 /* GPO1 Rx delay */ -#define REG_GPO2_RX_DELAY 0x02A /* GPO2 Rx delay */ -#define REG_GPO3_RX_DELAY 0x02B /* GPO3 Rx delay */ -#define REG_GPO0_TX_DELAY 0x02C /* GPO0 Tx Delay */ -#define REG_GPO1_TX_DELAY 0x02D /* GPO1 Tx Delay */ -#define REG_GPO2_TX_DELAY 0x02E /* GPO2 Tx Delay */ -#define REG_GPO3_TX_DELAY 0x02F /* GPO3 Tx Delay */ -#define REG_AUXDAC1_RX_DELAY 0x030 /* AuxDAC1 Rx Delay */ -#define REG_AUXDAC1_TX_DELAY 0x031 /* AuxDAC1 Tx Delay */ -#define REG_AUXDAC2_RX_DELAY 0x032 /* AuxDAC2 Rx Delay */ -#define REG_AUXDAC2_TX_DELAY 0x033 /* AuxDAC2 Tx Delay */ -#define REG_CTRL_OUTPUT_POINTER 0x035 /* Control Output Pointer */ -#define REG_CTRL_OUTPUT_ENABLE 0x036 /* Control Output Enable */ -#define REG_PRODUCT_ID 0x037 /* Product ID */ -#define REG_REFERENCE_CLOCK_CYCLES 0x03A /* Reference Clock Cycles */ -#define REG_DIGITAL_IO_CTRL 0x03B /* Digital I/O Control */ -#define REG_LVDS_BIAS_CTRL 0x03C /* LVDS Bias control */ -#define REG_LVDS_INVERT_CTRL1 0x03D /* LVDS Invert control1 */ -#define REG_LVDS_INVERT_CTRL2 0x03E /* LVDS Invert control2 */ -#define REG_SDM_CTRL_1 0x03F /* SDM Control 1 */ -#define REG_FRACT_BB_FREQ_WORD_1 0x041 /* Fractional BB Freq Word 1 */ -#define REG_FRACT_BB_FREQ_WORD_2 0x042 /* Fractional BB Freq Word 2 */ -#define REG_FRACT_BB_FREQ_WORD_3 0x043 /* Fractional BB Freq Word 3 */ -#define REG_INTEGER_BB_FREQ_WORD 0x044 /* Integer BB Freq Word */ -#define REG_CLOCK_CTRL 0x045 /* Clock Control */ -#define REG_CP_CURRENT 0x046 /* CP Current */ -#define REG_CP_BLEED_CURRENT 0x047 /* CP Bleed Current */ -#define REG_LOOP_FILTER_1 0x048 /* Loop Filter 1 */ -#define REG_LOOP_FILTER_2 0x049 /* Loop Filter 2 */ -#define REG_LOOP_FILTER_3 0x04A /* Loop Filter 3 */ -#define REG_VCO_CTRL 0x04B /* VCO Control */ -#define REG_VCO_PROGRAM_1 0x04C -#define REG_VCO_PROGRAM_2 0x04D -#define REG_SDM_CTRL 0x04E /* SDM Control */ -#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050 /* Rx Synth Power Down Override */ -#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051 /* TX Synth Power Down Override */ -#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052 /* Rx Analog Power Down Override 1 */ -#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053 /* Rx Analog Power Down Override 2 */ -#define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054 /* Rx1 ADC Power Down Override */ -#define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055 /* Rx2 ADC Power Down Override */ -#define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056 /* Tx Analog Power Down Override 1 */ -#define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057 /* Analog Power Down Override */ -#define REG_MISC_POWER_DOWN_OVERRIDE 0x058 /* Misc Power Down Override */ -#define REG_CH_1_OVERFLOW 0x05E /* CH 1 Overflow */ -#define REG_CH_2_OVERFLOW 0x05F /* CH 2 Overflow */ -#define REG_TX_FILTER_COEF_ADDR 0x060 /* TX Filter Coefficient Address */ -#define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061 /* TX Filter Coefficient Write Data 1 */ -#define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062 /* TX Filter Coefficient Write Data 2 */ -#define REG_TX_FILTER_COEF_READ_DATA_1 0x063 /* TX Filter Coefficient Read Data 1 */ -#define REG_TX_FILTER_COEF_READ_DATA_2 0x064 /* TX Filter Coefficient Read Data 2 */ -#define REG_TX_FILTER_CONF 0x065 /* TX Filter Configuration */ -#define REG_TX_MON_LOW_GAIN 0x067 /* Tx Mon Low Gain */ -#define REG_TX_MON_HIGH_GAIN 0x068 /* Tx Mon High Gain */ -#define REG_TX_MON_DELAY 0x069 /* Tx Mon Delay */ -#define REG_TX_LEVEL_THRESH 0x06A /* Tx Level Threshold */ -#define REG_TX_RSSI1 0x06B /* TX RSSI1 */ -#define REG_TX_RSSI2 0x06C /* TX RSSI2 */ -#define REG_TX_RSSI_LSB 0x06D /* TX RSSI LSB */ -#define REG_TPM_MODE_ENABLE 0x06E /* TPM Mode Enable */ -#define REG_TX_MON_TEMP_GAIN_COEF 0x06F /* Temp Gain Coefficient */ -#define REG_TX_MON_1_CONFIG 0x070 /* Tx Mon 1 Config */ -#define REG_TX_MON_2_CONFIG 0x071 /* Tx Mon 2 Config */ -#define REG_TX1_ATTEN_0 0x073 /* Tx1 Atten 0 */ -#define REG_TX1_ATTEN_1 0x074 /* Tx1 Atten 1 */ -#define REG_TX2_ATTEN_0 0x075 /* Tx2 Atten 0 */ -#define REG_TX2_ATTEN_1 0x076 /* Tx2 Atten 1 */ -#define REG_TX_ATTEN_OFFSET 0x077 /* Tx Atten Offset */ -#define REG_TX_ATTEN_THRESH 0x078 /* Tx Atten Threshold */ -#define REG_TX1_DIG_ATTEN 0x079 /* Tx1 Dig Attenuation */ -#define REG_TX2_DIG_ATTEN 0x07C /* Tx2 Dig Attenuation */ -#define REG_TX1_SYMBOL_ATTEN 0x07F /* TX1 Symbol Attenuation */ -#define REG_TX2_SYMBOL_ATTEN 0x080 /* TX2 Symbol Attenuation */ -#define REG_TX_SYMBOL_ATTEN_CONFIG 0x081 /* TX Symbol Atten Config */ -#define REG_TX1_OUT_1_PHASE_CORR 0x08E /* Tx1 Out 1 Phase Corr */ -#define REG_TX1_OUT_1_GAIN_CORR 0x08F /* Tx1 Out 1 Gain Corr */ -#define REG_TX2_OUT_1_PHASE_CORR 0x090 /* Tx2 Out 1 Phase Corr */ -#define REG_TX2_OUT_1_GAIN_CORR 0x091 /* Tx2 Out 1 Gain Corr */ -#define REG_TX1_OUT_1_OFFSET_I 0x092 /* Tx1 Out 1 Offset I */ -#define REG_TX1_OUT_1_OFFSET_Q 0x093 /* Tx1 Out 1 Offset Q */ -#define REG_TX2_OUT_1_OFFSET_I 0x094 /* Tx2 Out 1 Offset I */ -#define REG_TX2_OUT_1_OFFSET_Q 0x095 /* Tx2 Out 1 Offset Q */ -#define REG_TX1_OUT_2_PHASE_CORR 0x096 /* Tx1 Out 2 Phase Corr */ -#define REG_TX1_OUT_2_GAIN_CORR 0x097 /* Tx1 Out 2 Gain Corr */ -#define REG_TX2_OUT_2_PHASE_CORR 0x098 /* Tx2 Out 2 Phase Corr */ -#define REG_TX2_OUT_2_GAIN_CORR 0x099 /* Tx2 Out 2 Gain Corr */ -#define REG_TX1_OUT_2_OFFSET_I 0x09A /* Tx1 Out 2 Offset I */ -#define REG_TX1_OUT_2_OFFSET_Q 0x09B /* Tx1 Out 2 Offset Q */ -#define REG_TX2_OUT_2_OFFSET_I 0x09C /* Tx2 Out 2 Offset I */ -#define REG_TX2_OUT_2_OFFSET_Q 0x09D /* Tx2 Out 2 Offset Q */ -#define REG_TX_FORCE_BITS 0x09F /* Force Bits */ -#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0 /* Quad Cal NCO Freq & Phase Offset */ -#define REG_QUAD_CAL_CTRL 0x0A1 /* Quad Cal Control */ -#define REG_KEXP_1 0x0A2 /* Kexp 1 */ -#define REG_KEXP_2 0x0A3 /* Kexp 2 */ -#define REG_QUAD_SETTLE_COUNT 0x0A4 /* QUAD Settle count */ -#define REG_MAG_FTEST_THRESH 0x0A5 /* Mag. Ftest Thresh */ -#define REG_MAG_FTEST_THRESH_2 0x0A6 /* Mag. Ftest Thresh 2 */ -#define REG_QUAD_CAL_STATUS_TX1 0x0A7 /* Quad cal status Tx1 */ -#define REG_QUAD_CAL_STATUS_TX2 0x0A8 /* Quad cal status Tx2 */ -#define REG_QUAD_CAL_COUNT 0x0A9 /* Quad cal Count */ -#define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA /* Tx Quad Full/LMT Gain */ -#define REG_SQUARER_CONFIG 0x0AB /* Squarer Config */ -#define REG_TX_QUAD_CAL_ATTEN 0x0AC /* TX Quad Cal Atten */ -#define REG_THRESH_ACCUM 0x0AD /* Thresh Accum */ -#define REG_TX_QUAD_LPF_GAIN 0x0AE /* Tx Quad LPF Gain */ -#define REG_TXDAC_VDS_I 0x0B0 /* TxDAC Vds I */ -#define REG_TXDAC_VDS_Q 0x0B1 /* TxDAC Vds Q */ -#define REG_TXDAC_GN_I 0x0B2 /* TxDAC gn I */ -#define REG_TXDAC_GN_Q 0x0B3 /* TxDAC gn Q */ -#define REG_TXBBF_OPAMP_A 0x0C0 /* TxBBF OpAmp A */ -#define REG_TXBBF_OPAMP_B 0x0C1 /* TxBBF OpAmp B */ -#define REG_TX_BBF_R1 0x0C2 /* Tx BBF R1 */ -#define REG_TX_BBF_R2 0x0C3 /* Tx BBF R2 */ -#define REG_TX_BBF_R3 0x0C4 /* Tx BBF R3 */ -#define REG_TX_BBF_R4 0x0C5 /* Tx BBF R4 */ -#define REG_TX_BBF_RP 0x0C6 /* Tx BBF RP */ -#define REG_TX_BBF_C1 0x0C7 /* Tx BBF C1 */ -#define REG_TX_BBF_C2 0x0C8 /* Tx BBF C2 */ -#define REG_TX_BBF_CP 0x0C9 /* Tx BBF Cp */ -#define REG_TX_TUNE_CTRL 0x0CA /* Tx Tune Control */ -#define REG_TX_BBF_R2B 0x0CB /* Tx BBF R2b */ -#define REG_TX_BBF_TUNE 0x0CC /* Tx BBF Tune */ -#define REG_CONFIG0 0x0D0 /* Config0 */ -#define REG_RESISTOR 0x0D1 /* Resistor */ -#define REG_CAPACITOR 0x0D2 /* Capacitor */ -#define REG_LO_CM 0x0D3 /* LO CM */ -#define REG_TX_BBF_TUNE_DIVIDER 0x0D6 /* TX BBF Tune Divider */ -#define REG_TX_BBF_TUNE_MODE 0x0D7 /* TX BBF Tune Mode */ -#define REG_RX_FILTER_COEF_ADDR 0x0F0 /* Rx Filter Coeff Addr */ -#define REG_RX_FILTER_COEF_DATA_1 0x0F1 /* Rx Filter Coeff Data 1 */ -#define REG_RX_FILTER_COEF_DATA_2 0x0F2 /* Rx Filter Coeff Data 2 */ -#define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3 /* Rx Filter Coeff Read Data 1 */ -#define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4 /* Rx Filter Coeff Read Data 2 */ -#define REG_RX_FILTER_CONFIG 0x0F5 /* Rx Filter Config */ -#define REG_RX_FILTER_GAIN 0x0F6 /* Rx Filter Gain */ -#define REG_AGC_CONFIG_1 0x0FA /* AGC Config1 */ -#define REG_AGC_CONFIG_2 0x0FB /* AGC config2 */ -#define REG_AGC_CONFIG_3 0x0FC /* AGC Config3 */ -#define REG_MAX_LMT_FULL_GAIN 0x0FD /* Max LMT/Full Gain */ -#define REG_PEAK_WAIT_TIME 0x0FE /* Peak Wait Time */ -#define REG_DIGITAL_GAIN 0x100 /* Digital Gain */ -#define REG_AGC_LOCK_LEVEL 0x101 /* AGC Lock Level */ -#define REG_ADC_NOISE_CORRECTION_FACTOR 0x102 /* ADC noise Correction Factor */ -#define REG_GAIN_STP_CONFIG1 0x103 /* Gain Step Config1 */ -#define REG_ADC_SMALL_OVERLOAD_THRESH 0x104 /* ADC Small Overload Threshold */ -#define REG_ADC_LARGE_OVERLOAD_THRESH 0x105 /* ADC Large Overload Threshold */ -#define REG_GAIN_STP_CONFIG_2 0x106 /* Gain Step Config 2 */ -#define REG_SMALL_LMT_OVERLOAD_THRESH 0x107 /* Small LMT Overload Threshold */ -#define REG_LARGE_LMT_OVERLOAD_THRESH 0x108 /* Large LMT Overload Threshold */ -#define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109 /* Rx1 Manual LMT/Full Gain */ -#define REG_RX1_MANUAL_LPF_GAIN 0x10A /* Rx1 Manual LPF gain */ -#define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B /* Rx1 Manual Digital/Forced Gain */ -#define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C /* Rx2 Manual LMT/Full Gain */ -#define REG_RX2_MANUAL_LPF_GAIN 0x10D /* Rx2 Manual LPF Gain */ -#define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E /* Rx2 Manual Digital/Forced Gain */ -#define REG_FAST_CONFIG_1 0x110 /* Config 1 */ -#define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111 /* Config 2 & Settling Delay */ -#define REG_FAST_ENERGY_LOST_THRESH 0x112 /* Energy Lost Threshold */ -#define REG_FAST_STRONGER_SIGNAL_THRESH 0x113 /* Stronger Signal Threshold */ -#define REG_FAST_LOW_POWER_THRESH 0x114 /* Low Power Threshold */ -#define REG_FAST_STRONG_SIGNAL_FREEZE 0x115 /* Strong Signal Freeze */ -#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116 /* Final Over Range and Opt Gain */ -#define REG_FAST_ENERGY_DETECT_COUNT 0x117 /* Energy Detect Count */ -#define REG_FAST_AGCLL_UPPER_LIMIT 0x118 /* AGCLL Upper Limit */ -#define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119 /* Gain Lock Exit Count */ -#define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A /* Initial LMT Gain Limit */ -#define REG_FAST_INCREMENT_TIME 0x11B /* Increment Time */ -#define REG_AGC_INNER_LOW_THRESH 0x120 /* AGC Inner Low Threshold */ -#define REG_LMT_OVERLOAD_COUNTERS 0x121 /* LMT Overload Counters */ -#define REG_ADC_OVERLOAD_COUNTERS 0x122 /* ADC Overload Counters */ -#define REG_GAIN_STP1 0x123 /* Gain Step1 */ -#define REG_GAIN_UPDATE_COUNTER1 0x124 /* Gain Update Counter1 */ -#define REG_GAIN_UPDATE_COUNTER2 0x125 /* Gain Update Counter2 */ -#define REG_DIGITAL_SAT_COUNTER 0x128 /* Digital Sat Counter */ -#define REG_OUTER_POWER_THRESHS 0x129 /* Outer Power Thresholds */ -#define REG_GAIN_STP_2 0x12A /* Gain Step 2 */ -#define REG_EXT_LNA_HIGH_GAIN 0x12C /* Ext LNA High Gain */ -#define REG_EXT_LNA_LOW_GAIN 0x12D /* Ext LNA Low Gain */ -#define REG_GAIN_TABLE_ADDRESS 0x130 /* Gain Table Address */ -#define REG_GAIN_TABLE_WRITE_DATA1 0x131 /* Gain Table Write Data1 */ -#define REG_GAIN_TABLE_WRITE_DATA2 0x132 /* Gain Table Write Data2 */ -#define REG_GAIN_TABLE_WRITE_DATA3 0x133 /* Gain Table Write Data 3 */ -#define REG_GAIN_TABLE_READ_DATA1 0x134 /* Gain Table Read Data 1 */ -#define REG_GAIN_TABLE_READ_DATA2 0x135 /* Gain Table Read Data 2 */ -#define REG_GAIN_TABLE_READ_DATA3 0x136 /* Gain Table Read Data 3 */ -#define REG_GAIN_TABLE_CONFIG 0x137 /* Gain Table Config */ -#define REG_GM_SUB_TABLE_ADDRESS 0x138 /* Gm Sub Table Address */ -#define REG_GM_SUB_TABLE_GAIN_WRITE 0x139 /* Gm Sub Table Gain Word Write */ -#define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A /* Gm Sub Table Bias Word Write */ -#define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B /* Gm Sub Table Control Word Write */ -#define REG_GM_SUB_TABLE_GAIN_READ 0x13C /* Gm Sub Table Gain Word Read */ -#define REG_GM_SUB_TABLE_BIAS_READ 0x13D /* Gm Sub Table Bias Word Read */ -#define REG_GM_SUB_TABLE_CTRL_READ 0x13E /* Gm Sub Table Control Word Read */ -#define REG_GM_SUB_TABLE_CONFIG 0x13F /* Gm Sub Table Config */ -#define REG_WORD_ADDRESS 0x140 /* Word Address */ -#define REG_GAIN_DIFF_WORDERROR_WRITE 0x141 /* Gain Diff Word/Error Write */ -#define REG_GAIN_ERROR_READ 0x142 /* Gain Error Read */ -#define REG_CONFIG 0x143 /* Config */ -#define REG_LNA_GAIN_DIFF_READ_BACK 0x144 /* LNA Gain Diff Read Back */ -#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145 /* Max Mixer Calibration Gain Index */ -#define REG_TEMP_GAIN_COEF 0x146 /* Temp Gain Coefficient */ -#define REG_SETTLE_TIME 0x147 /* Settle Time */ -#define REG_MEASURE_DURATION 0x148 /* Measure Duration */ -#define REG_CAL_TEMP_SENSOR_WORD 0x149 /* Cal Temp sensor word */ -#define REG_MEASURE_DURATION_01 0x150 /* Measure Duration 0&1 */ -#define REG_MEASURE_DURATION_23 0x151 /* Measure Duration 2&3 */ -#define REG_RSSI_WEIGHT_0 0x152 /* RSSI Weight 0 */ -#define REG_RSSI_WEIGHT_1 0x153 /* RSSI Weight 1 */ -#define REG_RSSI_WEIGHT_2 0x154 /* RSSI Weight 2 */ -#define REG_RSSI_WEIGHT_3 0x155 /* RSSI Weight 3 */ -#define REG_RSSI_DELAY 0x156 /* RSSI delay */ -#define REG_RSSI_WAIT_TIME 0x157 /* RSSI wait time */ -#define REG_RSSI_CONFIG 0x158 /* RSSI Config */ -#define REG_ADC_MEASURE_DURATION_01 0x159 /* ADC Measure Duration 0&1 */ -#define REG_ADC_WEIGHT_0 0x15A /* ADC Weight 0 */ -#define REG_ADC_WEIGHT_1 0x15B /* ADC Weight 1 */ -#define REG_DEC_POWER_MEASURE_DURATION_0 0x15C /* Dec Power Measure Duration 0 */ -#define REG_LNA_GAIN 0x15D /* LNA Gain */ -#define REG_CH1_ADC_POWER 0x160 /* CH1 ADC Power */ -#define REG_CH1_RX_FILTER_POWER 0x161 /* CH1 Rx filter Power */ -#define REG_CH2_ADC_POWER 0x162 /* CH2 ADC Power */ -#define REG_CH2_RX_FILTER_POWER 0x163 /* CH2 Rx filter Power */ -#define REG_RX_QUAD_CAL_LEVEL 0x168 /* Rx Quad Cal Level */ -#define REG_CALIBRATION_CONFIG_1 0x169 /* Calibration Config 1 */ -#define REG_CALIBRATION_CONFIG_2 0x16A /* Calibration config2 */ -#define REG_CALIBRATION_CONFIG_3 0x16B /* Calibration config3 */ -#define REG_CALIB_COUNT 0x16C /* Calib count */ -#define REG_SETTLE_COUNT 0x16D /* Settle count */ -#define REG_RX_QUAD_GAIN1 0x16E /* Rx Quad gain1 */ -#define REG_RX_QUAD_GAIN2 0x16F /* Rx Quad gain2 */ -#define REG_RX1_INPUT_A_PHASE_CORR 0x170 /* Rx1 Input A Phase Corr */ -#define REG_RX1_INPUT_A_GAIN_CORR 0x171 /* Rx1 Input A Gain Corr */ -#define REG_RX2_INPUT_A_PHASE_CORR 0x172 /* Rx2 Input A Phase Corr */ -#define REG_RX2_INPUT_A_GAIN_CORR 0x173 /* Rx2 Input A Gain Corr */ -#define REG_RX1_INPUT_A_Q_OFFSET 0x174 /* Rx1 Input A Q" Offset */ -#define REG_RX1_INPUT_A_OFFSETS 0x175 /* Rx1 Input A Offsets */ -#define REG_INPUT_A_OFFSETS_1 0x176 /* Input A Offsets 1 */ -#define REG_RX2_INPUT_A_OFFSETS 0x177 /* Rx2 Input A Offsets */ -#define REG_RX2_INPUT_A_I_OFFSET 0x178 /* Rx2 Input A "I" Offset */ -#define REG_RX1_INPUT_BC_PHASE_CORR 0x179 /* Rx1 Input B&C Phase Corr */ -#define REG_RX1_INPUT_BC_GAIN_CORR 0x17A /* Rx1 Input B&C Gain Corr */ -#define REG_RX2_INPUT_BC_PHASE_CORR 0x17B /* Rx2 Input B&C Phase Corr */ -#define REG_RX2_INPUT_BC_GAIN_CORR 0x17C /* Rx2 Input B&C Gain Corr */ -#define REG_RX1_INPUT_BC_Q_OFFSET 0x17D /* Rx1 Input B&C "Q" Offset */ -#define REG_RX1_INPUT_BC_OFFSETS 0x17E /* Rx1 Input B&C Offsets */ -#define REG_INPUT_BC_OFFSETS_1 0x17F /* Input B&C Offsets 1 */ -#define REG_RX2_INPUT_BC_OFFSETS 0x180 /* Rx2 Input B&C Offsets */ -#define REG_RX2_INPUT_BC_I_OFFSET 0x181 /* Rx2 Input B&C "I" Offset */ -#define REG_FORCE_BITS 0x182 /* Force Bits */ -#define REG_WAIT_COUNT 0x185 /* Wait Count */ -#define REG_RF_DC_OFFSET_COUNT 0x186 /* RF DC Offset Count */ -#define REG_RF_DC_OFFSET_CONFIG_1 0x187 /* RF DC Offset Config1 */ -#define REG_RF_DC_OFFSET_ATTEN 0x188 /* RF DC Offset Attenuation */ -#define REG_INVERT_BITS 0x189 /* Invert Bits */ -#define REG_DC_OFFSET_CONFIG2 0x18B /* DC Offset Config2 */ -#define REG_RF_CAL_GAIN_INDEX 0x18C /* RF Cal Gain Index */ -#define REG_SOI_THRESH 0x18D /* SOI Threshold */ -#define REG_BB_DC_OFFSET_SHIFT 0x190 /* BB DC Offset Shift */ -#define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191 /* BB DC Offset Fast Settle Shift */ -#define REG_BB_FAST_SETTLE_DUR 0x192 /* BB Fast Settle Dur */ -#define REG_BB_DC_OFFSET_COUNT 0x193 /* BB DC Offset Count */ -#define REG_BB_DC_OFFSET_ATTEN 0x194 /* BB DC Offset Attenuation */ -#define REG_RX1_BB_DC_WORD_I_MSB 0x19A /* RX1 BB DC word I MSB */ -#define REG_RX1_BB_DC_WORD_I_LSB 0x19B /* RX1 BB DC word I LSB */ -#define REG_RX1_BB_DC_WORD_Q_MSB 0x19C /* RX1 BB DC word Q MSB */ -#define REG_RX1_BB_DC_WORD_Q_LSB 0x19D /* RX1 BB DC word Q LSB */ -#define REG_RX2_BB_DC_WORD_I_MSB 0x19E /* RX2 BB DC word I MSB */ -#define REG_RX2_BB_DC_WORD_I_LSB 0x19F /* RX2 BB DC word I LSB */ -#define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0 /* RX2 BB DC word Q MSB */ -#define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1 /* RX2 BB DC word Q LSB */ -#define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2 /* BB Track corr word I MSB */ -#define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3 /* BB Track corr word I LSB */ -#define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4 /* BB Track corr word Q MSB */ -#define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5 /* BB Track corr word Q LSB */ -#define REG_RX1_RSSI_SYMBOL 0x1A7 /* Rx1 RSSI Symbol */ -#define REG_RX1_RSSI_PREAMBLE 0x1A8 /* Rx1 RSSI preamble */ -#define REG_RX2_RSSI_SYMBOL 0x1A9 /* Rx2 RSSI symbol */ -#define REG_RX2_RSSI_PREAMBLE 0x1AA /* Rx2 RSSI preamble */ -#define REG_SYMBOL_LSB 0x1AB /* Symbol LSB */ -#define REG_PREAMBLE_LSB 0x1AC /* Preamble LSB */ -#define REG_RX_PATH_GAIN_MSB 0x1AD /* Rx Path Gain */ -#define REG_RX_PATH_GAIN_LSB 0x1AE /* Rx Path Gain */ -#define REG_RX_DIFF_LNA_FORCE 0x1B0 /* Rx Diff LNA Force */ -#define REG_RX_LNA_BIAS_COARSE 0x1B1 /* Rx LNA Bias Coarse */ -#define REG_RX_LNA_BIAS_FINE_0 0x1B2 /* Rx LNA Bias Fine 0 */ -#define REG_RX_LNA_BIAS_FINE_1 0x1B3 /* Rx LNA Bias Fine 1 */ -#define REG_RX_MIX_GM_CONFIG 0x1C0 /* Rx Mix Gm Config */ -#define REG_RX1_MIX_GM_FORCE 0x1C1 /* Rx1 Mix Gm Force */ -#define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2 /* Rx1 Mix Gm Bias (Force) */ -#define REG_RX2_MIX_GM_FORCE 0x1C3 /* Rx2 Mix Gm Force */ -#define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4 /* Rx2 Mix Gm Bias (Force) */ -#define REG_INPUT_A_MSBS 0x1C8 /* Input A MSBs */ -#define REG_INPUT_A_RX1_I 0x1C9 /* Input A RX1 I */ -#define REG_INPUT_A_RX1_Q 0x1CA /* Input A RX1 Q */ -#define REG_INPUT_A_RX2_I 0x1CB /* Input A RX2 I */ -#define REG_INPUT_A_RX2_Q 0x1CC /* Input A RX2 Q */ -#define REG_INPUTS_BC_RX1_I 0x1CD /* Inputs B&C RX1 I */ -#define REG_BAND1_RX1_Q 0x1CE /* Band1 RX1 Q */ -#define REG_INPUTS_BC_RX2_I 0x1CF /* Inputs B&C RX2 I */ -#define REG_INPUTS_BC_RX2_Q 0x1D0 /* Inputs B&C RX2 Q */ -#define REG_INPUTS_BC_MSBS 0x1D1 /* Inputs B&C MSBs */ -#define REG_FORCE_OS_DAC 0x1D2 /* Force OS DAC */ -#define REG_RX_MIX_LO_CM 0x1D5 /* Rx Mix LO CM */ -#define REG_RX_CGB_SEG_ENABLE 0x1D6 /* Rx CGB Seg Enable */ -#define REG_RX_MIX_INPUTBIAS 0x1D7 /* Rx Mix Input/Bias */ -#define REG_RX_TIA_CONFIG 0x1DB /* Rx TIA Config */ -#define REG_TIA1_C_LSB 0x1DC /* TIA1 C LSB */ -#define REG_TIA1_C_MSB 0x1DD /* TIA1 C MSB */ -#define REG_TIA2_C_LSB 0x1DE /* TIA2 C LSB */ -#define REG_TIA2_C_MSB 0x1DF /* TIA2 C MSB */ -#define REG_RX1_BBF_R1A 0x1E0 /* Rx1 BBF R1A */ -#define REG_RX2_BBF_R1A 0x1E1 /* Rx2 BBF R1A */ -#define REG_RX1_TUNE_CTRL 0x1E2 /* Rx1 Tune Control */ -#define REG_RX2_TUNE_CTRL 0x1E3 /* Rx2 Tune Control */ -#define REG_RX1_BBF_R5 0x1E4 /* Rx1 BBF R5 */ -#define REG_RX2_BBF_R5 0x1E5 /* Rx2 BBF R5 */ -#define REG_RX_BBF_R2346 0x1E6 /* Rx BBF R2346 */ -#define REG_RX_BBF_C1_MSB 0x1E7 /* Rx BBF C1 MSB */ -#define REG_RX_BBF_C1_LSB 0x1E8 /* Rx BBF C1 LSB */ -#define REG_RX_BBF_C2_MSB 0x1E9 /* Rx BBF C2 MSB */ -#define REG_RX_BBF_C2_LSB 0x1EA /* Rx BBF C2 LSB */ -#define REG_RX_BBF_C3_MSB 0x1EB /* Rx BBF C3 MSB */ -#define REG_RX_BBF_C3_LSB 0x1EC /* Rx BBF C3 LSB */ -#define REG_RX_BBF_CC1_CTR 0x1ED /* Rx BBF CC1 Ctr */ -#define REG_RX_BBF_POW_RZ_BYTE0 0x1EE /* Rx BBF Pow Rz Byte0 */ -#define REG_RX_BBF_CC2_CTR 0x1EF /* Rx BBF CC2 Ctr */ -#define REG_RX_BBF_POW_RZ_BYTE1 0x1F0 /* Rx BBF Pow Rz Byte1 */ -#define REG_RX_BBF_CC3_CTR 0x1F1 /* Rx BBF CC3 Ctr */ -#define REG_RX_BBF_R5_TUNE 0x1F2 /* Rx BBF R5 Tune */ -#define REG_RX_BBF_TUNE 0x1F3 /* Rx BBF Tune */ -#define REG_RX1_BBF_MAN_GAIN 0x1F4 /* Rx1 BBF Man Gain */ -#define REG_RX2_BBF_MAN_GAIN 0x1F5 /* Rx2 BBF Man Gain */ -#define REG_RX_BBF_TUNE_DIVIDE 0x1F8 /* RX BBF Tune Divide */ -#define REG_RX_BBF_TUNE_CONFIG 0x1F9 /* RX BBF Tune Config */ -#define REG_POLE_GAIN 0x1FA /* Pole gain */ -#define REG_RX_BBBW_MHZ 0x1FB /* Rx BBBW MHz */ -#define REG_RX_BBBW_KHZ 0x1FC /* Rx BBBW kHz */ -#define REG_FB_DAC_CLK_DELAY1 0x201 /* FB DAC Clk Delay1 */ -#define REG_FB_DAC_CLK_DELAY2 0x202 /* FB DAC Clk Delay2 */ -#define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203 /* Flash Sample Clk Delay 3p */ -#define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204 /* Flash Sample Clk Delay 3n */ -#define REG_TEST_MUX_2I 0x205 /* Test MUX 2i */ -#define REG_TEST_MUX_2Q 0x206 /* Test MUX 2q */ -#define REG_INTEGRATOR_1_RESISTANCE 0x207 /* Integrator 1 Resistance */ -#define REG_INTEGRATOR_1_CAPACITANCE 0x208 /* Integrator 1 Capacitance */ -#define REG_INTEGRATOR_23_RESISTANCE 0x209 /* Integrator 23 Resistance */ -#define REG_INTEGRATOR_2_RESISTANCE 0x20A /* Integrator 2 Resistance */ -#define REG_INTEGRATOR_2_CAPACITANCE 0x20B /* Integrator 2 Capacitance */ -#define REG_INTEGRATOR_3_RESISTANCE 0x20C /* Integrator 3 Resistance */ -#define REG_INTEGRATOR_3_CAPACITANCE 0x20D /* Integrator 3 Capacitance */ -#define REG_INTEGRATOR_AMP_CC 0x20E /* Integrator Amp Cc */ -#define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F /* Int 1 FB DAC NMOS Current Source */ -#define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */ -#define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211 /* Int 1 FB DAC PMOS Current Source */ -#define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212 /* Int 2 FB DAC NMOS Current Source */ -#define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */ -#define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214 /* Int 2 FB DAC PMOS Current Source */ -#define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215 /* Int 3 FB DAC NMOS Current Source */ -#define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */ -#define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217 /* Int 3 FB DAC PMOS Current Source */ -#define REG_FB_DAC_BIAS_CURRENT 0x218 /* FB DAC Bias Current */ -#define REG_INT_1_1ST_STAGE_CURRENT 0x219 /* Int 1 1st Stage Current */ -#define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A /* Int 1 1st Stage Cascode Current */ -#define REG_INT_1_2ND_STAGE_CURRENT 0x21B /* Int 1 2nd Stage Current */ -#define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C /* Integrator 2 1st Stage Current */ -#define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D /* Int 2 1st Stage Cascode Current */ -#define REG_INT_2_2ND_STAGE_CURRENT 0x21E /* Int 2 2nd Stage Current */ -#define REG_INT_3_1ST_STAGE_CURRENT 0x21F /* Int 3 1st Stage Current */ -#define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220 /* Int 3 1st Stage Cascode Current */ -#define REG_INT_3_2ND_STAGE_CURRENT 0x221 /* Int 3 2nd Stage Current */ -#define REG_FLASH_BIAS_CURRENT 0x222 /* Flash Bias Current */ -#define REG_FLASH_LADDER_BIAS 0x223 /* Flash Ladder Bias */ -#define REG_FLASH_LADDER_CASCODE_CURRENT 0x224 /* Flash Ladder Cascode Current */ -#define REG_FLASH_LADDER_BIAS2 0x225 /* Flash Ladder Bias2 */ -#define REG_RESET 0x226 /* Reset */ -#define REG_RX_PFD_CONFIG 0x230 /* RX PFD Config */ -#define REG_RX_INTEGER_BYTE_0 0x231 /* RX Integer Byte 0 */ -#define REG_RX_INTEGER_BYTE_1 0x232 /* RX Integer Byte 1 */ -#define REG_RX_FRACT_BYTE_0 0x233 /* RX Fractional Byte 0 */ -#define REG_RX_FRACT_BYTE_1 0x234 /* RX Fractional Byte 1 */ -#define REG_RX_FRACT_BYTE_2 0x235 /* RX Fractional Byte 2 */ -#define REG_RX_FORCE_ALC 0x236 /* RX Force ALC */ -#define REG_RX_FORCE_VCO_TUNE_0 0x237 /* RX Force VCO Tune 0 */ -#define REG_RX_FORCE_VCO_TUNE_1 0x238 /* RX Force VCO Tune 1 */ -#define REG_RX_ALC_VARACTOR 0x239 /* RX ALC/Varactor */ -#define REG_RX_VCO_OUTPUT 0x23A /* RX VCO Output */ -#define REG_RX_CP_CURRENT 0x23B /* RX CP Current */ -#define REG_RX_CP_OFFSET 0x23C /* RX CP Offset */ -#define REG_RX_CP_CONFIG 0x23D /* RX CP Config */ -#define REG_RX_LOOP_FILTER_1 0x23E /* RX Loop Filter 1 */ -#define REG_RX_LOOP_FILTER_2 0x23F /* RX Loop Filter 2 */ -#define REG_RX_LOOP_FILTER_3 0x240 /* RX Loop Filter 3 */ -#define REG_RX_DITHERCP_CAL 0x241 /* RX Dither/CP Cal */ -#define REG_RX_VCO_BIAS_1 0x242 /* RX VCO Bias 1 */ -#define REG_RX_CAL_STATUS 0x244 /* RX Cal Status */ -#define REG_RX_VCO_CAL_REF 0x245 /* RX VCO Cal Ref */ -#define REG_RX_VCO_PD_OVERRIDES 0x246 /* RX VCO Pd Overrides */ -#define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247 /* RX CP Over Range/VCO Lock */ -#define REG_RX_VCO_LDO 0x248 /* RX VCO LDO */ -#define REG_RX_VCO_CAL 0x249 /* RX VCO Cal */ -#define REG_RX_LOCK_DETECT_CONFIG 0x24A /* RX Lock Detect Config */ -#define REG_RX_CP_LEVEL_DETECT 0x24B /* RX CP Level Detect */ -#define REG_RX_DSM_SETUP_0 0x24C /* RX DSM Setup 0 */ -#define REG_RX_DSM_SETUP_1 0x24D /* RX DSM Setup 1 */ -#define REG_RX_CORRECTION_WORD0 0x24E /* RX Correction Word0 */ -#define REG_RX_CORRECTION_WORD1 0x24F /* RX Correction Word1 */ -#define REG_RX_VCO_VARACTOR_CTRL_0 0x250 /* RX VCO Varactor Control 0 */ -#define REG_RX_VCO_VARACTOR_CTRL_1 0x251 /* RX VCO Varactor Control 1 */ -#define REG_RX_FAST_LOCK_SETUP 0x25A /* Rx Fast Lock Setup */ -#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B /* Rx Fast Lock Setup Init Delay */ -#define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C /* Rx Fast Lock Program Addr */ -#define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D /* Rx Fast Lock Program Data */ -#define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E /* Rx Fast Lock Program Read */ -#define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F /* Rx Fast Lock Program Control */ -#define REG_RX_LO_GEN_POWER_MODE 0x261 /* Rx LO Gen Power Mode */ -#define REG_TX_PFD_CONFIG 0x270 /* TX PFD Config */ -#define REG_TX_INTEGER_BYTE_0 0x271 /* TX Integer Byte 0 */ -#define REG_TX_INTEGER_BYTE_1 0x272 /* TX Integer Byte 1 */ -#define REG_TX_FRACT_BYTE_0 0x273 /* TX Fractional Byte 0 */ -#define REG_TX_FRACT_BYTE_1 0x274 /* TX Fractional Byte 1 */ -#define REG_TX_FRACT_BYTE_2 0x275 /* TX Fractional Byte 2 */ -#define REG_TX_FORCE_ALC 0x276 /* TX Force ALC */ -#define REG_TX_FORCE_VCO_TUNE_0 0x277 /* TX Force VCO Tune 0 */ -#define REG_TX_FORCE_VCO_TUNE_1 0x278 /* TX Force VCO Tune 1 */ -#define REG_TX_ALCVARACT_OR 0x279 /* TX ALC/Varact or */ -#define REG_TX_VCO_OUTPUT 0x27A /* TX VCO Output */ -#define REG_TX_CP_CURRENT 0x27B /* TX CP Current */ -#define REG_TX_CP_OFFSET 0x27C /* TX CP Offset */ -#define REG_TX_CP_CONFIG 0x27D /* TX CP Config */ -#define REG_TX_LOOP_FILTER_1 0x27E /* TX Loop Filter 1 */ -#define REG_TX_LOOP_FILTER_2 0x27F /* TX Loop Filter 2 */ -#define REG_TX_LOOP_FILTER_3 0x280 /* TX Loop Filter 3 */ -#define REG_TX_DITHERCP_CAL 0x281 /* TX Dither/CP Cal */ -#define REG_TX_VCO_BIAS_1 0x282 /* TX VCO Bias 1 */ -#define REG_TX_VCO_BIAS_2 0x283 /* TX VCO Bias 2 */ -#define REG_TX_CAL_STATUS 0x284 /* TX Cal Status */ -#define REG_TX_VCO_CAL_REF 0x285 /* TX VCO Cal Ref */ -#define REG_TX_VCO_PD_OVERRIDES 0x286 /* TX VCO Pd Overrides */ -#define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287 /* TX CP Over Range/VCO Lock */ -#define REG_TX_VCO_LDO 0x288 /* TX VCO LDO */ -#define REG_TX_VCO_CAL 0x289 /* TX VCO Cal */ -#define REG_TX_LOCK_DETECT_CONFIG 0x28A /* TX Lock Detect Config */ -#define REG_TX_CP_LEVEL_DETECT 0x28B /* TX CP Level Detect */ -#define REG_TX_DSM_SETUP_0 0x28C /* TX DSM Setup 0 */ -#define REG_TX_DSM_SETUP_1 0x28D /* TX DSM Setup 1 */ -#define REG_TX_CORRECTION_WORD0 0x28E /* TX Correction Word0 */ -#define REG_TX_CORRECTION_WORD1 0x28F /* TX Correction Word1 */ -#define REG_TX_VCO_VARACTOR_CTRL_0 0x290 /* TX VCO Varactor Control 0 */ -#define REG_TX_VCO_VARACTOR_CTRL_1 0x291 /* TX VCO Varactor Control 1 */ -#define REG_DCXO_COARSE_TUNE 0x292 /* DCXO Coarse Tune */ -#define REG_DCXO_FINE_TUNE_HIGH 0x293 /* DCXO Fine Tune2 */ -#define REG_DCXO_FINE_TUNE_LOW 0x294 /* DCXO Fine Tune1 */ -#define REG_DCXO_CONFIG 0x295 /* DCXO Config */ -#define REG_DCXO_TEMPCO_WRITE 0x296 /* DCXO Tempco Write */ -#define REG_DCXO_TEMPCO_READ 0x297 /* DCXO Tempco Read */ -#define REG_DCXO_TEMPCO_ADDR 0x298 /* DCXO Tempco Addr */ -#define REG_DELTA_T_READ 0x299 /* Delta T Read */ -#define REG_TX_FAST_LOCK_SETUP 0x29A /* Tx Fast Lock Setup */ -#define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B /* Tx Fast Lock Setup Init Delay */ -#define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C /* Tx Fast Lock Program Addr */ -#define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D /* Tx Fast Lock Program Data */ -#define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E /* Tx Fast Lock Program Read */ -#define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F /* Tx Fast Lock Program Ctrl */ -#define REG_TX_LO_GEN_POWER_MODE 0x2A1 /* Tx LO Gen Power Mode */ -#define REG_BANDGAP_CONFIG0 0x2A6 /* Bandgap Config0 */ -#define REG_BANDGAP_CONFIG1 0x2A8 /* Bandgap Config1 */ -#define REG_REF_DIVIDE_CONFIG_1 0x2AB /* Ref Divide Config 1 */ -#define REG_REF_DIVIDE_CONFIG_2 0x2AC /* Ref Divide Config 2 */ -#define REG_GAIN_RX1 0x2B0 /* Gain Rx1 */ -#define REG_LPF_GAIN_RX1 0x2B1 /* LPF Gain Rx1 */ -#define REG_DIG_GAIN_RX1 0x2B2 /* Dig gain Rx1 */ -#define REG_FAST_ATTACK_STATE 0x2B3 /* Fast Attack State */ -#define REG_SLOW_LOOP_STATE 0x2B4 /* Slow Loop State */ -#define REG_GAIN_RX2 0x2B5 /* Gain Rx2 */ -#define REG_LPF_GAIN_RX2 0x2B6 /* LPF Gain Rx2 */ -#define REG_DIG_GAIN_RX2 0x2B7 /* Dig Gain Rx2 */ -#define REG_OVRG_SIGS_RX1 0x2B8 /* Ovrg Sigs Rx1 */ -#define REG_OVRG_SIGS_RX2 0x2B9 /* Ovrg Sigs Rx2 */ -#define REG_CTRL 0x3DF /* Control */ -#define REG_BIST_CONFIG 0x3F4 /* BIST Config */ -#define REG_OBSERVE_CONFIG 0x3F5 /* Observe Config */ -#define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6 /* BIST and Data Port Test Config */ -#define REG_DAC_TEST_0 0x3FC /* DAC Test 0 */ -#define REG_DAC_TEST_1 0x3FD /* DAC Test 1 */ -#define REG_DAC_TEST_2 0x3FE /* DAC Test 2 */ - -/* - * REG_SPI_CONF - */ -#define SOFT_RESET (1 << 7) /* Soft Reset */ -#define WIRE3_SPI (1 << 6) /* 3-Wire SPI */ -#define LSB_FIRST (1 << 5) /* LSB First */ -#define _LSB_FIRST (1 << 2) /* LSB First */ -#define _WIRE3_SPI (1 << 1) /* 3-Wire SPI */ -#define _SOFT_RESET (1 << 0) /* Soft reset */ - -/* - * REG_MULTICHIP_SYNC_AND_TX_MON_CTRL - */ -#define TX2_MONITOR_ENABLE (1 << 6) /* Tx2 Monitor Enable */ -#define TX1_MONITOR_ENABLE (1 << 5) /* Tx1 Monitor Enable */ -#define MCS_RF_ENABLE (1 << 3) /* MCS RF Enable */ -#define MCS_BBPLL_ENABLE (1 << 2) /* MCS BBPLL enable */ -#define MCS_DIGITAL_CLK_ENABLE (1 << 1) /* MCS Digital CLK Enable */ -#define MCS_BB_ENABLE (1 << 0) /* MCS BB Enable */ - -/* - * REG_TX_ENABLE_FILTER_CTRL - */ -#define THB2_EN (1 << 3) /* THB2 Enable */ -#define THB1_EN (1 << 2) /* THB1 Enable */ -#define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Tx channel Enable<1:0> */ -#define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */ -#define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */ -#define TX_1 1 -#define TX_2 2 -#define TX_ENABLE 1 -#define TX_DISABLE 0 - -/* - * REG_RX_ENABLE_FILTER_CTRL - */ -#define RHB2_EN (1 << 3) /* RHB2 Enable */ -#define RHB1_EN (1 << 2) /* RHB1 Enable */ -#define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Rx channel Enable<1:0> */ -#define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */ -#define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */ -#define RX_1 1 -#define RX_2 2 -#define RX_ENABLE 1 -#define RX_DISABLE 0 - -/* - * REG_INPUT_SELECT - */ -#define TX_OUTPUT (1 << 6) /* TX Output */ -#define RX_INPUT(x) (((x) & 0x3F) << 0) /* RX Input <5:0> */ - -/* - * REG_RFPLL_DIVIDERS - */ -#define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4) /* TX VCO Divider<3:0> */ -#define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0) /* RX VCO Divider<3:0> */ - -/* - * REG_RX_CLOCK_DATA_DELAY - */ -#define DATA_CLK_DELAY(x) (((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */ -#define RX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Rx Data Delay <3:0> */ - -/* - * REG_TX_CLOCK_DATA_DELAY - */ -#define FB_CLK_DELAY(x) (((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */ -#define TX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Tx Data Delay <3:0> */ - -/* - * REG_CLOCK_ENABLE - */ -#define XO_BYPASS (1 << 4) /* XO Bypass */ -#define DIGITAL_POWER_UP (1 << 2) /* Digital Power Up */ -#define CLOCK_ENABLE_DFLT (1 << 1) /* Set to 1 */ -#define BBPLL_ENABLE (1 << 0) /* BBPLL Enable */ - -/* - * REG_BBPLL - */ -#define CLKOUT_ENABLE (1 << 4) /* CLKOUT Enable */ -#define DAC_CLK_DIV2 (1 << 3) /* DAC Clk div2 */ -#define CLKOUT_SELECT(x) (((x) & 0x7) << 5) /* CLKOUT Select<2:0> */ -#define BBPLL_DIVIDER(x) (((x) & 0x7) << 0) /* BBPLL Divider <2:0> */ - -/* - * REG_START_TEMP_READING - */ -#define START_TEMP_READING (1 << 0) /* Start Temp Reading */ - -/* - * REG_TEMP_SENSE2 - */ -#define TEMP_SENSE_PERIODIC_ENABLE (1 << 0) /* Temp Sense Periodic Enable */ -#define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */ - -/* - * REG_TEMP_SENSOR_CONFIG - */ -#define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */ - -/* - * REG_PARALLEL_PORT_CONF_1 - */ -#define PP_TX_SWAP_IQ (1 << 7) /* PP Tx Swap IQ */ -#define PP_RX_SWAP_IQ (1 << 6) /* PP Rx Swap IQ */ -#define TX_CHANNEL_SWAP (1 << 5) /* Tx Channel swap */ -#define RX_CHANNEL_SWAP (1 << 4) /* Rx Channel swap */ -#define RX_FRAME_PULSE_MODE (1 << 3) /* Rx Frame Pulse Mode */ -#define R2T2_TIMING (1 << 2) /* 2R2T Timing */ -#define INVERT_DATA_BUS (1 << 1) /* Invert data bus */ -#define INVERT_DATA_CLK (1 << 0) /* Invert DATA CLK */ - -/* - * REG_PARALLEL_PORT_CONF_2 - */ -#define FDD_ALT_WORD_ORDER (1 << 7) /* FDD Alt Word Order */ -#define INVERT_RX1 (1 << 6) /* Invert Rx1 */ -#define INVERT_RX2 (1 << 5) /* Invert Rx2 */ -#define INVERT_TX1 (1 << 4) /* Invert Tx1 */ -#define INVERT_TX2 (1 << 3) /* Invert Tx2 */ -#define INVERT_RX_FRAME (1 << 2) /* Invert Rx Frame */ -#define DELAY_RX_DATA(x) (((x) & 0x3) << 0) /* Delay Rx Data<1:0> */ - -/* - * REG_PARALLEL_PORT_CONF_3 - */ -#define FDD_RX_RATE_2TX_RATE (1 << 7) /* FDD Rx Rate = 2*Tx Rate */ -#define SWAP_PORTS (1 << 6) /* Swap Ports */ -#define SINGLE_DATA_RATE (1 << 5) /* Single Data Rate */ -#define LVDS_MODE (1 << 4) /* LVDS Mode */ -#define HALF_DUPLEX_MODE (1 << 3) /* Half Duplex Mode */ -#define SINGLE_PORT_MODE (1 << 2) /* Single Port Mode */ -#define FULL_PORT (1 << 1) /* Full Port */ -#define FULL_DUPLEX_SWAP_BITS (1 << 0) /* Full Duplex Swap Bits */ - -/* - * REG_ENSM_MODE - */ -#define FDD_MODE (1 << 0) /* FDD Mode */ - -/* - * REG_ENSM_CONFIG_1 - */ -#define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7) /* Enable Rx Data Port for Cal */ -#define FORCE_RX_ON (1 << 6) /* Force Rx On */ -#define FORCE_TX_ON (1 << 5) /* Force Tx On */ -#define ENABLE_ENSM_PIN_CTRL (1 << 4) /* Enable ENSM Pin Control */ -#define LEVEL_MODE (1 << 3) /* Level Mode */ -#define FORCE_ALERT_STATE (1 << 2) /* Force Alert State */ -#define AUTO_GAIN_LOCK (1 << 1) /* Auto Gain Lock */ -#define TO_ALERT (1 << 0) /* To Alert */ - -/* - * REG_ENSM_CONFIG_2 - */ -#define FDD_EXTERNAL_CTRL_ENABLE (1 << 7) /* FDD External Control Enable */ -#define POWER_DOWN_RX_SYNTH (1 << 6) /* Power Down Rx Synth */ -#define POWER_DOWN_TX_SYNTH (1 << 5) /* Power Down Tx Synth */ -#define TXNRX_SPI_CTRL (1 << 4) /* TXNRX SPI Control */ -#define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3) /* Synth Enable Pin Control Mode */ -#define DUAL_SYNTH_MODE (1 << 2) /* Dual Synth Mode */ -#define RX_SYNTH_READY_MASK (1 << 1) /* Rx Synth Ready Mask */ -#define TX_SYNTH_READY_MASK (1 << 0) /* Tx Synth Ready Mask */ - -/* - * REG_CALIBRATION_CTRL - */ -#define RX_BB_TUNE_CAL (1 << 7) /* Rx BB Tune */ -#define TX_BB_TUNE_CAL (1 << 6) /* Tx BB Tune */ -#define RX_QUAD_CAL (1 << 5) /* Rx Quad Cal */ -#define TX_QUAD_CAL (1 << 4) /* Tx Quad Cal */ -#define RX_GAIN_STEP_CAL (1 << 3) /* Rx Gain Step Cal */ -#define TXMON_CAL (1 << 2) -#define RFDC_CAL (1 << 1) /* DC Cal RF Start */ -#define BBDC_CAL (1 << 0) /* DC cal BB Start */ - - -/* - * REG_STATE - */ -#define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */ -#define ENSM_STATE(x) (((x) & 0xF) << 0) /* ENSM State<3:0> */ -#define ENSM_STATE_SLEEP_WAIT 0x0 -#define ENSM_STATE_ALERT 0x5 -#define ENSM_STATE_TX 0x6 -#define ENSM_STATE_TX_FLUSH 0x7 -#define ENSM_STATE_RX 0x8 -#define ENSM_STATE_RX_FLUSH 0x9 -#define ENSM_STATE_FDD 0xA -#define ENSM_STATE_FDD_FLUSH 0xB -#define ENSM_STATE_INVALID 0xFF -#define ENSM_STATE_SLEEP 0x80 - -/* - * REG_AUXDAC_2_WORD - */ -#define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */ -#define AUXDAC_1_WORD(x) (((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */ - -/* - * REG_AUXDAC_1_CONFIG - */ -#define COMP_CTRL_1 (1 << 5) /* Comp Ctrl 1 */ -#define AUXDAC1_STP_FACTOR (1 << 4) /* AuxDAC1 Step Factor */ -#define AUXDAC_1_VREF(x) (((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */ -#define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */ - -/* - * REG_AUXDAC_2_CONFIG - */ -#define COMP_CTRL_2 (1 << 5) /* Comp Ctrl 2 */ -#define AUXDAC2_STP_FACTOR (1 << 4) /* AuxDAC2 Step Factor */ -#define AUXDAC_2_VREF(x) (((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */ -#define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */ - -/* - * REG_AUXADC_CLOCK_DIVIDER - */ -#define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */ - -/* - * REG_AUXADC_CONFIG - */ -#define AUXADC_POWER_DOWN (1 << 0) /* AuxADC Power Down */ -#define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */ - -/* - * REG_AUXADC_LSB - */ -#define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */ - -/* - * REG_AUTO_GPO - */ -#define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */ -#define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */ - -/* - * REG_AGC_ATTACK_DELAY - */ -#define INVERT_BYPASSED_LNA_POLARITY (1 << 6) /* Invert Bypassed LNA Polarity */ -#define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */ - -/* - * REG_AUXDAC_ENABLE_CTRL - */ -#define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */ -#define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */ -#define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */ -#define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */ - -/* - * REG_EXTERNAL_LNA_CTRL - */ -#define AUXDAC_MANUAL_SELECT (1 << 7) /* AuxDAC Manual Select */ -#define EXTERNAL_LNA2_CTRL (1 << 6) /* External LNA2 control */ -#define EXTERNAL_LNA1_CTRL (1 << 5) /* External LNA1 control */ -#define GPO_MANUAL_SELECT (1 << 4) /* GPO manual select */ -#define OPEN(x) (((x) & 0xF) << 0) /* Open<3:0> */ - -/* - * REG_GPO_FORCE_AND_INIT - */ -#define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4) /* GPO Manual Control<3:0> */ -#define GPO_INIT_STATE(x) (((x) & 0xF) << 0) /* GPO Init State<3:0> */ - -/* - * REG_CTRL_OUTPUT_ENABLE - */ -#define EN_CTRL7 (1 << 7) /* En ctrl7 */ -#define EN_CTRL6 (1 << 6) /* En ctrl6 */ -#define EN_CTRL5 (1 << 5) /* En ctrl5 */ -#define EN_CTRL4 (1 << 4) /* En ctrl4 */ -#define EN_CTRL3 (1 << 3) /* En ctrl3 */ -#define EN_CTRL2 (1 << 2) /* En ctrl2 */ -#define EN_CTRL1 (1 << 1) /* En ctrl1 */ -#define EN_CTRL0 (1 << 0) /* En ctrl0 */ - -/* - * REG_PRODUCT_ID - */ -#define PRODUCT_ID_MASK 0xF8 -#define PRODUCT_ID_9361 0x08 -#define REV_MASK 0x07 - -/* - * REG_REFERENCE_CLOCK_CYCLES - */ -#define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */ - -/* - * REG_DIGITAL_IO_CTRL - */ -#define CLK_OUT_DRIVE (1 << 7) /* CLK Out Drive */ -#define DATACLK_DRIVE (1 << 6) /* DATACLK drive */ -#define DATA_PORT_DRIVE (1 << 2) /* Data Port Drive */ -#define DATACLK_SLEW(x) (((x) & 0x3) << 4) /* DATACLK slew <1:0> */ -#define DATA_PORT_SLEW(x) (((x) & 0x3) << 0) /* Data Port Slew<1:0> */ - -/* - * REG_LVDS_BIAS_CTRL - */ -#define RX_ON_CHIP_TERM (1 << 5) /* Rx On Chip Term */ -#define LVDS_BYPASS_BIAS_R (1 << 4) /* Bypass Bias R */ -#define LVDS_TX_LO_VCM (1 << 3) /* LVDS Tx LO VCM */ -#define CLK_OUT_SLEW(x) (((x) & 0x3) << 6) /* CLK Out Slew<1:0> */ -#define LVDS_BIAS(x) (((x) & 0x7) << 0) /* LVDS Bias <2:0> */ - -/* - * REG_SDM_CTRL_1 - */ -#define INIT_BB_FO_CAL (1 << 2) /* Init BB FO CAL */ -#define BBPLL_RESET_BAR (1 << 0) /* BBPLL Reset Bar */ - -/* - * REG_CLOCK_CTRL - */ -#define REF_FREQ_SCALER(x) (((x) & 0x3) << 0) /* Ref Frequency Scaler */ - -/* - * REG_CP_CURRENT - */ -#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ - -/* - * REG_CP_BLEED_CURRENT - */ -#define MCS_REFCLK_SCALE_EN (1 << 7) /* MCS refclk Scale En */ - -/* - * REG_LOOP_FILTER_1 - */ -#define C1_WORD(x) (((x) & 0x7) << 5) /* C1 Word<2:0> */ -#define R1_WORD(x) (((x) & 0x1F) << 0) /* R1 Word<4:0> */ - -/* - * REG_LOOP_FILTER_2 - */ -#define R2_WORD (1 << 7) /* R2 Word<0> */ -#define C2_WORD(x) (((x) & 0x1F) << 2) /* C2 Word<4:0> */ -#define C1_WORD_LSB(x) (((x) & 0x3) << 0) /* C1 Word<4:3> */ - -/* - * REG_LOOP_FILTER_3 - */ -#define BYPASS_C3 (1 << 7) /* Bypass C3 */ -#define BYPASS_R2 (1 << 6) /* Bypass R2 */ -#define C3_WORD(x) (((x) & 0xF) << 2) /* C3 Word<3:0> */ -#define R2_WORD_LSB(x) (((x) & 0x3) << 0) /* R2 Word<2:1> */ - -/* - * REG_VCO_CTRL - */ -#define FREQ_CAL_ENABLE (1 << 7) /* Freq Cal Enable */ -#define FREQ_CAL_RESET (1 << 4) /* Freq Cal Reset */ -#define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */ - -/* - * REG_SDM_CTRL - */ -#define CAL_CLOCK_DIV_4 (1 << 4) /* Cal Clock div 4 */ - -/* - * REG_RX_SYNTH_POWER_DOWN_OVERRIDE - */ -#define RX_LO_POWER_DOWN (1 << 4) /* Rx LO Power Down */ -#define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Rx Synth VCO ALC Power Down */ -#define RX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Rx Synth PTAT Power Down */ -#define RX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Rx Synth VCO Power Down */ -#define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Rx Synth VCO LDO Power Down */ - -/* - * REG_TX_SYNTH_POWER_DOWN_OVERRIDE - */ -#define TX_LO_POWER_DOWN (1 << 4) /* Tx LO Power Down */ -#define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Tx Synth VCO ALC Power Down */ -#define TX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Tx Synth PTAT Power Down */ -#define TX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Tx Synth VCO Power Down */ -#define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Tx Synth VCO LDO Power Down */ - -/* - * REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 - */ -#define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */ -#define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */ -#define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */ -#define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */ - -/* - * REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 - */ -#define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */ -#define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */ -#define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */ -#define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */ - -/* - * REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 - */ -#define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */ -#define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */ -#define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */ -#define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */ - -/* - * REG_ANALOG_POWER_DOWN_OVERRIDE - */ -#define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5) /* Rx Ext VCO Buffer Power Down */ -#define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4) /* Tx Ext VCO Buffer Power Down */ -#define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */ -#define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */ - -/* - * REG_MISC_POWER_DOWN_OVERRIDE - */ -#define RX_LNA_POWER_DOWN (1 << 6) /* Rx LNA Power Down */ -#define DCXO_POWER_DOWN (1 << 1) /* DCXO Power Down */ -#define MASTER_BIAS_POWER_DOWN (1 << 0) /* Master Bias Power Down */ -#define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */ - -/* - * REG_CH_1_OVERFLOW - */ -#define BBPLL_LOCK (1 << 7) /* BBPLL Lock */ -#define CH_1_INT3 (1 << 6) /* CH 1 INT3 */ -#define CH1_HB3 (1 << 5) /* CH1 HB3 */ -#define CH1_HB2 (1 << 4) /* CH1 HB2 */ -#define CH1_QEC (1 << 3) /* CH1 QEC */ -#define CH1_HB1 (1 << 2) /* CH1 HB1 */ -#define CH1_TFIR (1 << 1) /* CH1 TFIR */ -#define CH1_RFIR (1 << 0) /* CH1 RFIR */ - -/* - * REG_CH_2_OVERFLOW - */ -#define CH2_INT3 (1 << 6) /* CH2 INT3 */ -#define CH2_HB3 (1 << 5) /* CH2 HB3 */ -#define CH2_HB2 (1 << 4) /* CH2 HB2 */ -#define CH2_QEC (1 << 3) /* CH2 QEC */ -#define CH2_HB1 (1 << 2) /* CH2 HB1 */ -#define CH2_TFIR (1 << 1) /* CH2 TFIR */ -#define CH2_RFIR (1 << 0) /* CH2 RFIR */ - -/* - * REG_TX_FILTER_CONF - */ -#define TX_FIR_GAIN_6DB (1 << 0) /* Filter Gain */ -#define FIR_START_CLK (1 << 1) /* Start Tx/Rx Clock */ -#define FIR_WRITE (1 << 2) /* Write Tx/Rx */ -#define FIR_SELECT(x) (((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */ -#define FIR_NUM_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps<2:0> */ - -/* - * REG_TX_MON_LOW_GAIN - */ -#define TX_MON_TRACK (1 << 5) /* Tx Mon Track */ -#define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */ - -/* - * REG_TX_MON_HIGH_GAIN - */ -#define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */ - -/* - * REG_TX_LEVEL_THRESH - */ -#define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */ -#define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */ - -/* - * REG_TX_RSSI_LSB - */ -#define TX_RSSI_2 (1 << 1) /* Tx RSSI 2<0> */ -#define TX_RSSI_1 (1 << 0) /* TX RSSI 1<0> */ - -/* - * REG_TPM_MODE_ENABLE - */ -#define TX2_MON_ENABLE (1 << 7) /* Tx2 Monitor Enable */ -#define TX1_MON_ENABLE (1 << 5) /* Tx1 Monitor Enable */ -#define ONE_SHOT_MODE (1 << 6) /* One Shot Mode */ -#define TX_MON_DURATION(x) (((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */ - -/* - * REG_TX_MON_1_CONFIG - */ -#define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */ -#define TX_MON_1_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */ - -/* - * REG_TX_MON_2_CONFIG - */ -#define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */ -#define TX_MON_2_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */ - -/* - * REG_TX1_ATTEN_1 - */ -#define TX_1_ATTEN (1 << 0) /* Tx 1 Atten <8> */ - -/* - * REG_TX2_ATTEN_1 - */ -#define TX_2_ATTEN (1 << 0) /* Tx 2 Atten <8> */ - -/* - * REG_TX_ATTEN_OFFSET - */ -#define MASK_CLR_ATTEN_UPDATE (1 << 6) /* Mask Clr Atten Update */ -#define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */ - -/* - * REG_TX1_DIG_ATTEN - */ -#define SEL_TX1_TX2 (1 << 6) /* Sel Tx1 & Ttx2 */ - -/* - * REG_TX2_DIG_ATTEN - */ -#define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6) /* Immediately Update TPC Atten */ - -/* - * REG_TX1_SYMBOL_ATTEN - */ -#define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */ - -/* - * REG_TX2_SYMBOL_ATTEN - */ -#define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */ - -/* - * REG_TX_SYMBOL_ATTEN_CONFIG - */ -#define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3) /* Use Tx1 Pin & Symbol Atten */ -#define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1) /* Use CTRL IN for symbol Atten */ -#define ENABLE_SYMBOL_ATTEN (1 << 0) /* Enable Symbol Atten */ - -/* - * REG_TX_FORCE_BITS - */ -#define FORCE_OUT_2_TX2_OFFSET (1 << 7) /* Force Out 2 Tx2 Offset */ -#define FORCE_OUT_2_TX1_OFFSET (1 << 6) /* Force Out 2 Tx1 Offset */ -#define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5) /* Force Out 2 Tx2 Phase & Gain */ -#define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4) /* Force Out 2 Tx1 Phase & Gain */ -#define FORCE_OUT_1_TX2_OFFSET (1 << 3) /* Force Out 1 Tx2 Offset */ -#define FORCE_OUT_1_TX1_OFFSET (1 << 2) /* Force Out 1 Tx1 Offset */ -#define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1) /* Force Out 1 Tx2 Phase & Gain */ -#define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0) /* Force Out 1 Tx1 Phase & Gain */ - -/* - * REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET - */ -#define RX_NCO_FREQ(x) (((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */ -#define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */ - -/* - * REG_QUAD_CAL_CTRL - */ -#define FREE_RUN_ENABLE (1 << 7) /* Free Run Enable */ -#define SETTLE_MAIN_ENABLE (1 << 6) /* Settle Main Enable */ -#define DC_OFFSET_ENABLE (1 << 5) /* DC Offset Enable */ -#define GAIN_ENABLE (1 << 4) /* Gain Enable */ -#define PHASE_ENABLE (1 << 3) /* Phase Enable */ -#define QUAD_CAL_SOFT_RESET (1 << 2) /* Quad Cal Soft Reset */ -#define M_DECIM(x) (((x) & 0x3) << 0) /* M<1:0> */ - -/* - * REG_KEXP_1 - */ -#define KEXP_TX(x) (((x) & 0x3) << 6) /* Kexp Tx<1:0> */ -#define KEXP_TX_COMP(x) (((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */ -#define KEXP_DC_I(x) (((x) & 0x3) << 2) /* Kexp DC I <1:0> */ -#define KEXP_DC_Q(x) (((x) & 0x3) << 0) /* Kexp DC Q <1:0> */ - -/* - * REG_KEXP_2 - */ -#define INVERT_I_DATA (1 << 5) /* Invert I data */ -#define INVERT_Q_DATA (1 << 4) /* Invert Q data */ -#define TX_NCO_FREQ(x) (((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */ -#define KEXP_PHASE(x) (((x) & 0x3) << 2) /* Kexp Phase <1:0> */ -#define KEXP_AMP(x) (((x) & 0x3) << 0) /* Kexp Amp <1:0> */ - -/* - * REG_QUAD_CAL_STATUS_TX1 - */ -#define TX1_LO_CONV (1 << 1) /* Tx1 LO Conv */ -#define TX1_SSB_CONV (1 << 0) /* Tx1 SSB Conv */ -#define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */ - -/* - * REG_QUAD_CAL_STATUS_TX2 - */ -#define TX2_LO_CONV (1 << 1) /* Tx2 LO Conv */ -#define TX2_SSB_CONV (1 << 0) /* Tx2 SSB Conv */ -#define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */ - -/* - * REG_TX_QUAD_FULL_LMT_GAIN - */ -#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */ - -/* - * REG_SQUARER_CONFIG - */ -#define GM_STAGE_TIME_CON_OVERRIDE (1 << 5) /* Gm Stage Time Con Override */ -#define GM_STAGE_MV_HP_POLE (1 << 4) /* Gm Stage MV HP Pole */ -#define GM_STAGE_LOWER_CM (1 << 3) /* Gm Stage Lower CM */ -#define BYPASS_BIAS_R (1 << 0) /* Bypass Bias R */ -#define VBIAS_CTRL(x) (((x) & 0x3) << 1) /* Vbias Control<1:0> */ - -/* - * REG_THRESH_ACCUM - */ -#define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */ - -/* - * REG_TX_QUAD_LPF_GAIN - */ -#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* RX LPF gain<4:0> */ - -/* - * REG_TXDAC_VDS_I - */ -#define TXDAC_VDS_I(x) (((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */ - -/* - * REG_TXDAC_VDS_Q - */ -#define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */ - -/* - * REG_TXDAC_GN_I - */ -#define TXDAC_GN_I(x) (((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */ - -/* - * REG_TXDAC_GN_Q - */ -#define TXDAC_GN_Q(x) (((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */ - -/* - * REG_TXBBF_OPAMP_A - */ -#define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */ -#define OPAMPA_RZ(x) (((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */ -#define OPAMP_A_CC(x) (((x) & 0x7) << 0) /* OpAmp A CC<2:0> */ - -/* - * REG_TXBBF_OPAMP_B - */ -#define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */ -#define OPAMPB_RZ(x) (((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */ -#define OPAMP_B_CC(x) (((x) & 0x7) << 0) /* OpAmp B CC<2:0> */ - -/* - * REG_TX_BBF_R1 - */ -#define OVERRIDE_ENABLE (1 << 7) /* Override enable */ -#define R1(x) (((x) & 0x1F) << 0) /* R1<4:0> */ - -/* - * REG_TX_BBF_R2 - */ -#define R2(x) (((x) & 0x1F) << 0) /* R2<4:0> */ - -/* - * REG_TX_BBF_R3 - */ -#define R3(x) (((x) & 0x1F) << 0) /* R3<4:0> */ - -/* - * REG_TX_BBF_R4 - */ -#define R4(x) (((x) & 0x1F) << 0) /* R4<4:0> */ - -/* - * REG_TX_BBF_RP - */ -#define RP(x) (((x) & 0x1F) << 0) /* Rp<4:0> */ - -/* - * REG_TX_BBF_C1 - */ -#define C1(x) (((x) & 0x3F) << 0) /* C1<5:0> */ - -/* - * REG_TX_BBF_C2 - */ -#define C2(x) (((x) & 0x3F) << 0) /* C2<5:0> */ - -/* - * REG_TX_BBF_CP - */ -#define CP(x) (((x) & 0x3F) << 0) /* Cp<5:0> */ - -/* - * REG_TX_TUNE_CTRL - */ -#define PD_TUNE (1 << 2) /* PD Tune */ -#define TUNER_RESAMPLE (1 << 1) /* Tuner Resample */ -#define TUNER_RESAMPLE_PHASE (1 << 0) /* Tuner Resample Phase */ -#define TUNE_CTRL(x) (((x) & 0x3) << 5) /* Tune Control<1:0> */ - -/* - * REG_TX_BBF_R2B - */ -#define TX_BBF_BYPASS_BIAS_R (1 << 7) /* Bypass Bias R */ -#define R2B_OVR (1 << 5) /* R2b Ovr */ -#define R2B(x) (((x) & 0x1F) << 0) /* R2b<4:0> */ - -/* - * REG_TX_BBF_TUNE - */ -#define BBF1_COMP_I (1 << 3) /* BBF1 Comp I */ -#define BBF1_COMP_Q (1 << 2) /* BBF1 Comp Q */ -#define BBF2_COMP_I (1 << 1) /* BBF2 Comp I */ -#define BBF2_COMP_Q (1 << 0) /* BBF2 Comp Q */ - -/* - * REG_CONFIG0 - */ -#define BIAS(x) (((x) & 0x3) << 6) /* Bias<1:0> */ -#define RGM(x) (((x) & 0x3) << 4) /* Rgm<1:0> */ -#define CC(x) (((x) & 0x3) << 2) /* Cc<1:0> */ -#define AMPBIAS(x) (((x) & 0x3) << 0) /* AmpBias<1:0> */ - -/* - * REG_RESISTOR - */ -#define RESISTOR(x) (((x) & 0xF) << 0) /* Resistor<3:0> */ - -/* - * REG_CAPACITOR - */ -#define CAPACITOR(x) (((x) & 0x3F) << 0) /* Capacitor<5:0> */ - -/* - * REG_LO_CM - */ -#define LO_COMMON_MODE(x) (((x) & 0x3) << 5) /* LO Common Mode<1:0> */ - -/* - * REG_TX_BBF_TUNE_MODE - */ -#define EVALTIME (1 << 4) /* EvalTime */ -#define TX_BBF_TUNE_DIVIDER (1 << 0) /* TX BBF Tune Divider<8> */ -#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */ -#define TUNER_MODE(x) (((x) & 0x7) << 1) /* Tuner Mode<2:0> */ - -/* - * REG_RX_FILTER_CONFIG - */ -#define WRITE_RX (1 << 2) /* Write Rx */ -#define START_RX_CLOCK (1 << 1) /* Start Rx Clock */ -#define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps */ -#define SELECT_RX_CH(x) (((x) & 0x3) << 3) /* Select Rx Ch<1:0> */ - -/* - * REG_RX_FILTER_GAIN - */ -#define FILTER_GAIN(x) (((x) & 0x3) << 0) /* Filter gain<1:0> */ - -/* - * REG_AGC_CONFIG_1 - */ -#define DEC_PWR_FOR_LOW_PWR (1 << 7) /* Dec Pwr for Low Pwr */ -#define DEC_PWR_FOR_LOCK_LEVEL (1 << 6) /* Dec Pwr for Lock Level */ -#define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5) /* Dec Pwr for Gain Lock Exit */ -#define SLOW_ATTACK_HYBRID_MODE (1 << 4) /* Slow Attack Hybrid Mode */ -#define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */ -#define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */ -#define RX_GAIN_CTL_MASK 0x03 -#define RX2_GAIN_CTRL_SHIFT 2 -#define RX1_GAIN_CTRL_SHIFT 0 -#define RX_GAIN_CTL_MGC 0x00 -#define RX_GAIN_CTL_AGC_FAST_ATK 0x01 -#define RX_GAIN_CTL_AGC_SLOW_ATK 0x02 -#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03 - -/* - * REG_AGC_CONFIG_2 - */ -#define AGC_SOFT_RESET (1 << 7) /* Soft Reset */ -#define AGC_GAIN_UNLOCK_CTRL (1 << 6) /* Gain Unlock Control */ -#define AGC_USE_FULL_GAIN_TABLE (1 << 3) /* Use Full Gain Table */ -#define DIG_GAIN_EN (1 << 2) /* Enable Digital Gain */ -#define MAN_GAIN_CTRL_RX2 (1 << 1) /* Manual Gain Control Rx 2 */ -#define MAN_GAIN_CTRL_RX1 (1 << 0) /* Manual Gain Control Rx 1 */ - -/* - * REG_AGC_CONFIG_3 - */ -#define INCDEC_LMT_GAIN (1 << 4) /* Inc/Dec LMT Gain */ -#define USE_AGC_FOR_LMTLPF_GAIN (1 << 3) /* Use AGC for LMT/LPF Gain */ -#define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */ -#define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */ - -/* - * REG_MAX_LMT_FULL_GAIN - */ -#define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */ - -/* - * REG_PEAK_WAIT_TIME - */ -#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */ -#define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */ - -/* - * REG_DIGITAL_GAIN - */ -#define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */ -#define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */ - -/* - * REG_AGC_LOCK_LEVEL - */ -#define ENABLE_DIG_SAT_OVRG (1 << 7) /* Enable Dig Sat Ovrg */ -#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */ - -/* - * REG_GAIN_STP_CONFIG1 - */ -#define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */ -#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */ -#define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */ - -/* - * REG_GAIN_STP_CONFIG_2 - */ -#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */ -#define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */ - -/* - * REG_SMALL_LMT_OVERLOAD_THRESH - */ -#define FORCE_PD_RESET_RX2 (1 << 7) /* Force PD Reset Rx2 */ -#define FORCE_PD_RESET_RX1 (1 << 6) /* Force PD Reset Rx1 */ -#define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */ - -/* - * REG_LARGE_LMT_OVERLOAD_THRESH - */ -#define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */ - -/* - * REG_RX1_MANUAL_LMT_FULL_GAIN - */ -#define POWER_MEAS_IN_STATE_5_MSB (1 << 7) /* Power Meas in State 5 <3> */ -#define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */ -#define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0) - -/* - * REG_RX1_MANUAL_LPF_GAIN - */ -#define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */ -#define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */ -#define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0) - -/* - * REG_RX1_MANUAL_DIGITALFORCED_GAIN - */ -#define FORCE_RX1_DIGITAL_GAIN (1 << 5) /* Force Rx1 Digital Gain */ -#define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */ -#define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0) -/* - * REG_RX2_MANUAL_LMT_FULL_GAIN - */ -#define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */ - -/* - * REG_RX2_MANUAL_LPF_GAIN - */ -#define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */ - -/* - * REG_RX2_MANUAL_DIGITALFORCED_GAIN - */ -#define FORCE_RX2_DIGITAL_GAIN (1 << 5) /* Force Rx2 Digital Gain */ -#define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */ - -/* - * REG_FAST_CONFIG_1 - */ -#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7) /* Enable Gain Inc after Gain Lock */ -#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */ -#define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Set Gain if EN_AGC High */ -#define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4) /* Goto Set Gain if Exit Rx State */ -#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3) /* Don't Unlock Gain if Energy Lost */ -#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2) /* Goto Optimized Gain if Exit Rx State */ -#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */ -#define ENABLE_INCR_GAIN (1 << 0) /* Enable Incr Gain */ - -/* - * REG_FAST_CONFIG_2_SETTLING_DELAY - */ -#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7) /* Use Last Lock Level for Set Gain */ -#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6) /* Enable LMT Gain Inc for Lock Level */ -#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */ -#define SETTLING_DELAY(x) (((x) & 0x1F) << 0) /* Settling Delay<4:0> */ - -/* - * REG_FAST_ENERGY_LOST_THRESH - */ -#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */ -#define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */ - -/* - * REG_FAST_STRONGER_SIGNAL_THRESH - */ -#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step for LMT Table <1:0> */ -#define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */ - -/* - * REG_FAST_LOW_POWER_THRESH - */ -#define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7) /* Don't unlock gain if ADC Ovrg */ -#define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */ - -/* - * REG_FAST_STRONG_SIGNAL_FREEZE - */ -#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7) /* Don't unlock gain if Stronger Signal */ - -/* - * REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN - */ -#define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5) /* Final Over Range Count<2:0> */ -#define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */ - -/* - * REG_FAST_ENERGY_DETECT_COUNT - */ -#define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */ -#define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0) /* Energy Detect count<4:0> */ - -/* - * REG_FAST_AGCLL_UPPER_LIMIT - */ -#define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */ - -/* - * REG_FAST_GAIN_LOCK_EXIT_COUNT - */ -#define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */ - -/* - * REG_FAST_INITIAL_LMT_GAIN_LIMIT - */ -#define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */ - -/* - * REG_AGC_INNER_LOW_THRESH - */ -#define PREVENT_GAIN_INC (1 << 7) /* Prevent Gain Inc */ -#define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */ - -/* - * REG_LMT_OVERLOAD_COUNTERS - */ -#define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */ -#define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */ - -/* - * REG_ADC_OVERLOAD_COUNTERS - */ -#define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */ -#define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */ - -/* - * REG_GAIN_STP1 - */ -#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7) /* Immed. Gain Change if Lg LMT Overload */ -#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3) /* Immed. Gain Change if Lg ADC Overload */ -#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */ -#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */ - -/* - * REG_DIGITAL_SAT_COUNTER - */ -#define DOUBLE_GAIN_COUNTER (1 << 5) /* Double Gain Counter */ -#define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4) /* Enable Sync for Gain Counter */ -#define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */ - -/* - * REG_OUTER_POWER_THRESHS - */ -#define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */ -#define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */ - -/* - * REG_GAIN_STP_2 - */ -#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */ -#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */ - -/* - * REG_EXT_LNA_HIGH_GAIN - */ -#define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */ - -/* - * REG_EXT_LNA_LOW_GAIN - */ -#define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */ - -/* - * REG_GAIN_TABLE_ADDRESS - */ -#define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0) /* Gain Table Address<6:0> */ - -/* - * REG_GAIN_TABLE_WRITE_DATA1 - */ -#define EXT_LNA_CTRL (1 << 7) /* Ext LNA Ctrl */ -#define LNA_GAIN(x) (((x) & 0x3) << 5) /* LNA Gain <1:0> */ -#define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */ - -/* - * REG_GAIN_TABLE_WRITE_DATA2 - */ -#define TIA_GAIN (1 << 5) /* TIA Gain */ -#define LPF_GAIN(x) (((x) & 0x1F) << 0) /* LPF Gain <4:0> */ - -/* - * REG_GAIN_TABLE_WRITE_DATA_3 - */ -#define RF_DC_CAL (1 << 5) /* RF DC Cal */ -#define DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Digital Gain <4:0> */ - -/* - * REG_GAIN_TABLE_READ_DATA_1 - */ -#define TO_LNA_GAIN(x) (((x) >> 5) & 0x3) /* LNA Gain <1:0> */ -#define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */ - -/* - * REG_GAIN_TABLE_READ_DATA_2 - */ -#define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F) /* LPF Gain <4:0> */ - -/* - * REG_GAIN_TABLE_READ_DATA_3 - */ -#define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F) /* Digital Gain <4:0> */ - -/* - * REG_GAIN_TABLE_CONFIG - */ -#define WRITE_GAIN_TABLE (1 << 2) /* Write Gain Table */ -#define START_GAIN_TABLE_CLOCK (1 << 1) /* Start Gain Table Clock */ -#define RECEIVER_SELECT(x) (((x) & 0x3) << 3) /* Receiver Select<1:0> */ -#define GT_RX1 1 -#define GT_RX2 2 - - -/* - * REG_GM_SUB_TABLE_GAIN_WRITE - */ -#define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */ - -/* - * REG_GM_SUB_TABLE_BIAS_WRITE - */ -#define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */ - -/* - * REG_GM_SUB_TABLE_CTRL_WRITE - */ -#define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */ - -/* - * REG_GM_SUB_TABLE_GAIN_READ - */ -#define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */ - -/* - * REG_GM_SUB_TABLE_BIAS_READ - */ -#define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */ - -/* - * REG_GM_SUB_TABLE_CTRL_READ - */ -#define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */ - -/* - * REG_GM_SUB_TABLE_CONFIG - */ -#define WRITE_GM_SUB_TABLE (1 << 2) /* Write Gm Sub Table */ -#define START_GM_SUB_TABLE_CLOCK (1 << 1) /* Start Gm Sub Table Clock */ - -/* - * REG_GAIN_DIFF_WORDERROR_WRITE - */ -#define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */ - -/* - * REG_GAIN_ERROR_READ - */ -#define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */ - -/* - * REG_CONFIG - */ -#define READ_SELECT (1 << 4) /* Read Select */ -#define WRITE_MIXER_ERROR_TABLE (1 << 3) /* Write Mixer Error Table */ -#define WRITE_LNA_ERROR_TABLE (1 << 2) /* Write LNA Error Table */ -#define WRITE_LNA_GAIN_DIFF (1 << 1) /* Write LNA Gain Diff */ -#define START_CALIB_TABLE_CLOCK (1 << 0) /* Start Calib Table Clock */ -#define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5) /* Calib Table Select<1:0> */ - -/* - * REG_LNA_GAIN_DIFF_READ_BACK - */ -#define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */ - -/* - * REG_MAX_MIXER_CALIBRATION_GAIN_INDEX - */ -#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */ - -/* - * REG_SETTLE_TIME - */ -#define ENABLE_DIG_GAIN_CORR (1 << 7) /* Enable Dig Gain Corr */ -#define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6) /* Force Temp Sensor for Cal */ -#define SETTLE_TIME(x) (((x) & 0x3F) << 0) /* Settle Time<5:0> */ - -/* - * REG_MEASURE_DURATION - */ -#define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */ - -/* - * REG_MEASURE_DURATION_01 - */ -#define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */ -#define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */ - -/* - * REG_MEASURE_DURATION_23 - */ -#define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */ -#define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */ - -/* - * REG_RSSI_CONFIG - */ -#define START_RSSI_MEAS (1 << 5) /* Start RSSI Meas (Mode 4) */ -#define ENABLE_ADC_POWER_MEAS (1 << 1) /* Enable ADC Power Meas. */ -#define DEFAULT_RSSI_MEAS_MODE (1 << 0) /* Default RSSI Meas Mode */ -#define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */ -#define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */ - -/* - * REG_ADC_MEASURE_DURATION_01 - */ -#define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */ -#define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */ - -/* - * REG_DEC_POWER_MEASURE_DURATION_0 - */ -#define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7) /* Use HB3 Out for ADC Pwr Meas */ -#define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6) /* Use HB1 Out for Dec pwr Meas */ -#define ENABLE_DEC_PWR_MEAS (1 << 5) /* Enable Dec Pwr Meas */ -#define DEFAULT_MODE_ADC_POWER (1 << 4) /* Default Mode ADC Power */ -#define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */ - -/* - * REG_LNA_GAIN - */ -#define DB_GAIN_READBACK_CHANNEL (1 << 0) /* dB Gain Read-back Channel */ -#define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */ - -/* - * REG_RX_QUAD_CAL_LEVEL - */ -#define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */ - -/* - * REG_CALIBRATION_CONFIG_1 - */ -#define ENABLE_PHASE_CORR (1 << 7) /* Enable Phase Corr */ -#define ENABLE_GAIN_CORR (1 << 6) /* Enable Gain Corr */ -#define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5) /* Use Settle Count for DC Cal Wait */ -#define FIXED_DC_CAL_WAIT_TIME (1 << 4) /* Fixed DC Cal Wait Time */ -#define FREE_RUN_MODE (1 << 3) /* Free Run Mode */ -#define ENABLE_CORR_WORD_DECIMATION (1 << 2) /* Enable Corr Word Decimation */ -#define ENABLE_TRACKING_MODE_CH2 (1 << 1) /* Enable Tracking Mode CH2 */ -#define ENABLE_TRACKING_MODE_CH1 (1 << 0) /* Enable Tracking Mode CH1 */ - -/* - * REG_CALIBRATION_CONFIG_2 - */ -#define SOFT_RESET (1 << 7) /* Soft Reset */ -#define CALIBRATION_CONFIG2_DFLT (0x3 << 5) /* Must be 2'b11 */ -#define K_EXP_PHASE(x) (((x) & 0x1F) << 0) /* K exp Phase<4:0> */ - -/* - * REG_CALIBRATION_CONFIG_3 - */ -#define PREVENT_POS_LOOP_GAIN (1 << 7) /* Prevent Pos Loop Gain */ -#define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */ - -/* - * REG_RX_QUAD_GAIN1 - */ -#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */ - -/* - * REG_RX_QUAD_GAIN2 - */ -#define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */ -#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */ - -/* - * REG_RX1_INPUT_A_OFFSETS - */ -#define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */ -#define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */ - -/* - * REG_INPUT_A_OFFSETS_1 - */ -#define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */ -#define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */ - -/* - * REG_RX2_INPUT_A_OFFSETS - */ -#define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */ -#define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */ - -/* - * REG_RX1_INPUT_BC_OFFSETS - */ -#define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */ -#define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */ - -/* - * REG_INPUT_BC_OFFSETS_1 - */ -#define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */ -#define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */ - -/* - * REG_RX2_INPUT_BC_OFFSETS - */ -#define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */ -#define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */ - -/* - * REG_FORCE_BITS - */ -#define RX2_INPUT_BC_FORCE_OFFSET (1 << 7) /* Rx2 Input B&C Force offset */ -#define RX1_INPUT_BC_FORCE_OFFSET (1 << 6) /* Rx1 Input B&C Force offset */ -#define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5) /* Rx2 Input B&C Force Ph/Gain */ -#define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4) /* Rx1 Input B&C Force Ph/Gain */ -#define RX2_INPUT_A_FORCE_OFFSET (1 << 3) /* Rx2 Input A Force offset */ -#define RX1_INPUT_A_FORCE_OFFSET (1 << 2) /* Rx1 Input A Force offset */ -#define RX2_INPUT_A_FORCE_PHGAIN (1 << 1) /* Rx2 Input A Force Ph/Gain */ -#define RX1_INPUT_A_FORCE_PHGAIN (1 << 0) /* Rx1 Input A Force Ph/Gain */ - -/* - * REG_RF_DC_OFFSET_CONFIG_1 - */ -#define DAC_FS(x) (((x) & 0x3) << 4) /* DAC FS<1:0> */ -#define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */ - -/* - * REG_RF_DC_OFFSET_ATTEN - */ -#define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */ -#define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */ - -/* - * REG_INVERT_BITS - */ -#define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7) /* Invert Rx2 RF DC CGin Word */ -#define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6) /* Invert Rx1 RF DC CGin Word */ -#define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5) /* Invert Rx2 RF DC CGout Word */ -#define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4) /* Invert Rx1 RF DC CGout Word */ - -/* - * REG_DC_OFFSET_CONFIG2 - */ -#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7) /* Use Wait Counter for RF DC Init Cal */ -#define ENABLE_FAST_SETTLE_MODE (1 << 6) /* Enable Fast Settle Mode */ -#define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5) /* Enable BB DC Offset Tracking */ -#define RESET_ACC_ON_GAIN_CHANGE (1 << 4) /* Reset Acc on Gain Change */ -#define ENABLE_RF_OFFSET_TRACKING (1 << 3) /* Enable RF Offset Tracking */ -#define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0) /* DC Offset Update<2:0> */ - -/* - * REG_RF_CAL_GAIN_INDEX - */ -#define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */ - -/* - * REG_SOI_THRESH - */ -#define RF_SOI_THRESH(x) (((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */ - -/* - * REG_BB_DC_OFFSET_SHIFT - */ -#define INCREASE_COUNT_DURATION (1 << 7) /* Increase Count Duration */ -#define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */ -#define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC M Shift<4:0> */ - -/* - * REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT - */ -#define READ_BACK_CH_SEL (1 << 7) /* Read Back CH Sel */ -#define UPDATE_TRACKING_WORD (1 << 6) /* Update Tracking Word */ -#define FORCE_RX_NULL (1 << 5) /* Force Rx Null */ -#define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */ - -/* - * REG_BB_DC_OFFSET_ATTEN - */ -#define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */ - -/* - * REG_RX1_BB_DC_WORD_I_MSB - */ -#define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */ - -/* - * REG_RX1_BB_DC_WORD_Q_MSB - */ -#define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */ - -/* - * REG_RX2_BB_DC_WORD_I_MSB - */ -#define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */ - -/* - * REG_RX2_BB_DC_WORD_Q_MSB - */ -#define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */ - -/* - * REG_BB_TRACK_CORR_WORD_I_MSB - */ -#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */ - -/* - * REG_BB_TRACK_CORR_WORD_Q_MSB - */ -#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */ - -/* - * REG_SYMBOL_LSB - */ -#define RX2_RSSI_SYMBOL (1 << 1) /* Rx2 RSSI symbol <0> */ -#define RX1_RSSI_SYMBOL (1 << 0) /* Rx1 RSSI symbol <0> */ - -/* - * REG_PREAMBLE_LSB - */ -#define RX2_RSSI_PREAMBLE (1 << 1) /* Rx2 RSSI preamble <0> */ -#define RX1_RSSI_PREAMBLE (1 << 0) /* Rx1 RSSI preamble <0> */ - -/* - * REG_RX1_RSSI_SYMBOL, REG_RX1_RSSI_PREAMBLE, - * REG_RX2_RSSI_SYMBOL, REG_RX2_RSSI_PREAMBLE - */ -#define RSSI_LSB_SHIFT 1 -#define RSSI_LSB_MASK1 0x01 -#define RSSI_LSB_MASK2 0x02 - -/* - * REG_RX_PATH_GAIN_LSB - */ -#define RX_PATH_GAIN (1 << 0) /* Rx Path Gain<0> */ - -/* - * REG_RX_DIFF_LNA_FORCE - */ -#define FORCE_RX2_LNA_GAIN (1 << 7) /* Force Rx2 LNA Gain */ -#define RX2_LNA_BYPASS (1 << 6) /* Rx2 LNA Bypass */ -#define FORCE_RX1_LNA_GAIN (1 << 3) /* Force Rx1 LNA Gain */ -#define RX1_LNA_BYPASS (1 << 2) /* Rx1 LNA Bypass */ -#define RX2_LNA_GAIN(x) (((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */ -#define RX1_LNA_GAIN(x) (((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */ - -/* - * REG_RX_LNA_BIAS_COARSE - */ -#define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */ - -/* - * REG_RX_LNA_BIAS_FINE_0 - */ -#define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */ -#define RX_LNA_BIAS(x) (((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */ - -/* - * REG_RX_LNA_BIAS_FINE_1 - */ -#define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */ - -/* - * REG_RX_MIX_GM_CONFIG - */ -#define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */ -#define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */ - -/* - * REG_RX1_MIX_GM_FORCE - */ -#define FORCE_RX1_MIX_GM (1 << 6) /* Force Rx1 Mix Gm */ -#define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */ - -/* - * REG_RX1_MIX_GM_BIAS_FORCE - */ -#define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */ - -/* - * REG_RX2_MIX_GM_FORCE - */ -#define FORCE_RX2_MIX_GM (1 << 6) /* Force Rx2 Mix Gm */ -#define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */ - -/* - * REG_RX2_MIX_GM_BIAS_FORCE - */ -#define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */ - -/* - * REG_INPUT_A_MSBS - */ -#define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */ -#define INPUT_A_RX1_I(x) (((x) & 0x3) << 4) /* Input A RX1 I<9:8> */ -#define INPUT_A_RX2_I(x) (((x) & 0x3) << 2) /* Input A RX2 I<9:8> */ -#define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */ - -/* - * REG_INPUTS_BC_MSBS - */ -#define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */ -#define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */ -#define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */ -#define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */ - -/* - * REG_FORCE_OS_DAC - */ -#define FORCE_CGIN_DAC (1 << 2) /* Force CGin DAC */ - -/* - * REG_RX_MIX_LO_CM - */ -#define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */ - -/* - * REG_RX_CGB_SEG_ENABLE - */ -#define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */ - -/* - * REG_RX_MIX_INPUTBIAS - */ -#define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */ -#define RX_CGB_BIAS(x) (((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */ - -/* - * REG_RX_TIA_CONFIG - */ -#define TIA2_OVERRIDE_C (1 << 3) /* TIA2 Override C */ -#define TIA2_OVERRIDE_R (1 << 2) /* TIA2 Override R */ -#define TIA1_OVERRIDE_C (1 << 1) /* TIA1 Override C */ -#define TIA1_OVERRIDE_R (1 << 0) /* TIA1 Override R */ -#define TIA_SEL_CC(x) (((x) & 0x7) << 5) /* TIA Sel CC<2:0> */ - -/* - * REG_TIA1_C_LSB - */ -#define TIA1_RF(x) (((x) & 0x3) << 6) /* TIA1 RF<1:0> */ -#define TIA1_C_LSB(x) (((x) & 0x3F) << 0) /* TIA1 C LSB<5:0> */ - -/* - * REG_TIA1_C_MSB - */ -#define TIA1_C_MSB(x) (((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */ - -/* - * REG_TIA2_C_LSB - */ -#define TIA2_RF(x) (((x) & 0x3) << 6) /* TIA2 RF<1:0> */ -#define TIA2_C_LSB(x) (((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */ - -/* - * REG_TIA2_C_MSB - */ -#define TIA2_C_MSB(x) (((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */ - -/* - * REG_RX1_BBF_R1A - */ -#define FORCE_RX1_RESISTORS (1 << 7) /* Force Rx1 Resistors */ -#define RX1_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */ - -/* - * REG_RX2_BBF_R1A - */ -#define FORCE_RX2_RESISTORS (1 << 7) /* Force Rx2 Resistors */ -#define RX2_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */ - -/* - * REG_RX1_TUNE_CTRL - */ -#define RX1_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx1 Tune Resample Phase */ -#define RX1_TUNE_RESAMPLE (1 << 1) /* Rx1 Tune Resample */ -#define RX1_PD_TUNE (1 << 0) /* Rx1 PD Tune */ - -/* - * REG_RX2_TUNE_CTRL - */ -#define RX2_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx2 Tune Resam ple Phase */ -#define RX2_TUNE_RESAMPLE (1 << 1) /* Rx2 Tune Resample */ -#define RX2_PD_TUNE (1 << 0) /* Rx2 PD Tune */ - -/* - * REG_RX_BBF_R2346 - */ -#define TUNE_OVERRIDE (1 << 7) /* Tune Override */ -#define RX_BBF_R2346(x) (((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */ - -/* - * REG_RX_BBF_C1_MSB - */ -#define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */ - -/* - * REG_RX_BBF_C1_LSB - */ -#define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */ - -/* - * REG_RX_BBF_C2_MSB - */ -#define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */ - -/* - * REG_RX_BBF_C2_LSB - */ -#define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */ - -/* - * REG_RX_BBF_C3_MSB - */ -#define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */ - -/* - * REG_RX_BBF_C3_LSB - */ -#define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */ - -/* - * REG_RX_BBF_CC1_CTR - */ -#define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */ - -/* - * REG_RX_BBF_POW_RZ_BYTE0 - */ -#define MUST_BE_ZERO (1 << 7) /* Must be zero */ -#define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */ -#define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */ - -/* - * REG_RX_BBF_CC2_CTR - */ -#define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */ - -/* - * REG_RX_BBF_POW_RZ_BYTE1 - */ -#define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */ -#define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */ -#define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */ -#define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */ - -/* - * REG_RX_BBF_CC3_CTR - */ -#define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */ - -/* - * REG_RX_BBF_TUNE - */ -#define RXBBF_BYPASS_BIAS_R (1 << 7) /* RxBBF Bypass Bias R */ -#define RX_BBF_R5_TUNE (1 << 4) /* Rx BBF R5 Tune */ -#define RX1_BBF_TUNE_COMP_I (1 << 3) /* Rx1 BBF Tune Comp I */ -#define RX1_BBF_TUNE_COMP_Q (1 << 2) /* Rx1 BBF Tune Comp Q */ -#define RX2_BBF_TUNE_COMP_I (1 << 1) /* Rx2 BBF Tune Comp I */ -#define RX2_BBF_TUNE_COMP_Q (1 << 0) /* Rx2 BBF Tune Comp Q */ -#define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */ - -/* - * REG_RX1_BBF_MAN_GAIN - */ -#define RX1_BBF_FORCE_GAIN (1 << 5) /* Rx1 BBF Force Gain */ -#define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */ -#define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */ - -/* - * REG_RX2_BBF_MAN_GAIN - */ -#define RX2_BBF_FORCE_GAIN (1 << 5) /* Rx2 BBF Force Gain */ -#define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */ -#define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */ - -/* - * REG_RX_BBF_TUNE_CONFIG - */ -#define RX_TUNE_EVALTIME (1 << 4) /* Rx Tune Evaltime */ -#define RX_BBF_TUNE_DIVIDE (1 << 0) /* RX BBF Tune Divide<8> */ -#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */ -#define RX_TUNE_MODE(x) (((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */ - -/* - * REG_POLE_GAIN - */ -#define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */ - -/* - * REG_RX_BBBW_MHZ - */ -#define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */ - -/* - * REG_RX_BBBW_KHZ - */ -#define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */ - -/* - * REG_RX_PFD_CONFIG - */ -#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */ - -/* - * REG_RX_INTEGER_BYTE_1 - */ -#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */ - -/* - * REG_RX_FRACT_BYTE_2 - */ -#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */ - -/* - * REG_RX_FORCE_VCO_TUNE_1 - */ -#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */ - -/* - * REG_RX_ALC_VARACTOR - */ -#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */ -#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */ - -/* - * REG_RX_VCO_OUTPUT - */ -#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */ -#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */ - -/* - * REG_RX_CP_CURRENT - */ -#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ - -/* - * REG_RX_CP_OFFSET - */ -#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */ - -/* - * REG_RX_CP_CONFIG - */ -#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */ -#define CP_OFFSET_OFF (1 << 4) /* CP Offset Off */ -#define F_CPCAL (1 << 3) /* F Cpcal */ -#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */ - -/* - * REG_RX_LOOP_FILTER_1 - */ -#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */ -#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */ - -/* - * REG_RX_LOOP_FILTER_2 - */ -#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */ -#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */ - -/* - * REG_RX_LOOP_FILTER_3 - */ -#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */ -#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */ -#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */ -#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */ -#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */ - -/* - * REG_RX_DITHERCP_CAL - */ -#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */ - -/* - * REG_RX_VCO_BIAS_1 - */ -#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */ -#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */ - -/* - * REG_RX_CAL_STATUS - */ -#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */ -#define CP_CAL_DONE (1 << 5) /* CP Cal Done */ -#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */ -#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */ - -/* - * REG_RX_VCO_CAL_REF - */ -#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */ - -/* - * REG_RX_VCO_PD_OVERRIDES - */ -#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */ -#define PWR_DOWN_VARACT_REF_TCF (1 << 2) /* Pwr Down Varact Ref Tcf */ -#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */ -#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */ - -/* - * REG_RX_CP_OVERRANGE_VCO_LOCK - */ -#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */ -#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */ -#define VCO_LOCK (1 << 1) /* Lock */ - -/* - * REG_RX_VCO_LDO - */ -#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */ -#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */ -#define VCO_LDO_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */ -#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */ - -/* - * REG_RX_VCO_CAL - */ -#define VCO_CAL_EN (1 << 7) /* VCO Cal En */ -#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */ -#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count <1:0> */ - -/* - * REG_RX_LOCK_DETECT_CONFIG - */ -#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */ -#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */ - -/* - * REG_RX_CP_LEVEL_DETECT - */ -#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */ -#define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */ -#define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */ - -/* - * REG_RX_DSM_SETUP_0 - */ -#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */ - -/* - * REG_RX_DSM_SETUP_1 - */ -#define SIF_CLOCK (1 << 6) /* SIF clock */ -#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */ -#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */ - -/* - * REG_RX_CORRECTION_WORD0 - */ -#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ -#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */ -#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */ - -/* - * REG_RX_CORRECTION_WORD1 - */ -#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ -#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */ - -/* - * REG_RX_VCO_VARACTOR_CTRL_0 - */ -#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */ -#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */ - -/* - * REG_RX_VCO_VARACTOR_CTRL_1 - */ -#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */ - -/* - * REG_RX_FAST_LOCK_SETUP - */ -#define RX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Rx Fast Lock Load Synth */ -#define RX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Rx Fast Lock Profile Init */ -#define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Rx Fast Lock Profile Pin Select */ -#define RX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Rx Fast Lock Mode Enable */ -#define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */ - -/* - * REG_RX_FAST_LOCK_PROGRAM_ADDR - */ -#define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */ -#define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0) /* Configuration Word <3:0> */ - - -/* - * REG_RX_FAST_LOCK_PROGRAM_CTRL - */ -#define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Rx Fast Lock Program Write */ -#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Rx Fast Lock Program Clock Enable */ - -#define RX_FAST_LOCK_CONFIG_WORD_NUM 16 - -/* - * REG_RX_LO_GEN_POWER_MODE - */ -#define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4) /* Power Mode<3:0> */ - -/* - * REG_TX_PFD_CONFIG - */ -#define DIV_TEST_EN (1 << 5) /* Div Test En */ -#define PFD_CLK_EDGE (1 << 1) /* PFD Clk Edge */ -#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */ -#define PFD_WIDTH(x) (((x) & 0x3) << 2) /* PFD Width <1:0> */ - -/* - * REG_TX_INTEGER_BYTE_1 - */ -#define SDM_BYPASS (1 << 7) /* SDM Bypass */ -#define SDM_POWER_DOWN (1 << 6) /* SDM Power Down */ -#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */ - -/* - * REG_TX_FRACT_BYTE_2 - */ -#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */ - -/* - * REG_TX_FORCE_ALC - */ -#define FORCE_ALC_ENABLE (1 << 7) /* Force ALC Enable */ -#define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0) /* Force ALC Word<6:0> */ - -/* - * REG_TX_FORCE_VCO_TUNE_1 - */ -#define BYPASS_LOAD_DELAY (1 << 7) /* Bypass Load Delay */ -#define FORCE_VCO_TUNE_ENABLE (1 << 1) /* Force VCO Tune Enable */ -#define FORCE_VCO_TUNE (1 << 0) /* Force VCO Tune */ -#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */ - -/* - * REG_TX_ALCVARACT_OR - */ -#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */ -#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */ - -/* - * REG_TX_VCO_OUTPUT - */ -#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */ -#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */ - -/* - * REG_TX_CP_CURRENT - */ -#define TX_CP_CURRENT_DFLT (1 << 7) /* Set to 1 */ -#define VTUNE_FORCE (1 << 6) /* Vtune Force */ -#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */ - -/* - * REG_TX_CP_OFFSET - */ -#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */ -#define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */ - -/* - * REG_TX_CP_CONFIG - */ -#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */ -#define DITHER_MODE (1 << 6) /* Dither Mode */ -#define CP_OFFSET_OFF (1 << 4) /* Cp Offset Off */ -#define F_CPCAL (1 << 3) /* F Cpcal */ -#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */ -#define CP_TEST(x) (((x) & 0x3) << 0) /* Cp Test <1:0> */ - -/* - * REG_TX_LOOP_FILTER_1 - */ -#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */ -#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */ - -/* - * REG_TX_LOOP_FILTER_2 - */ -#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */ -#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */ - -/* - * REG_TX_LOOP_FILTER_3 - */ -#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */ -#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */ -#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */ -#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */ -#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */ - -/* - * REG_TX_DITHERCP_CAL - */ -#define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */ -#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */ - -/* - * REG_TX_VCO_BIAS_1 - */ -#define MUST_BE_ZEROS(x) (((x) & 0x3) << 5) /* Must be zeros */ -#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */ -#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */ - -/* - * REG_TX_VCO_BIAS_2 - */ -#define VCO_BYPASS_BIAS_DAC_R (1 << 7) /* VCO Bypass Bias DAC R */ -#define VCO_COMP_BYPASS_BIAS_R (1 << 4) /* VCO Comp Bypass Bias R */ -#define BYPASS_PRESCALE_R (1 << 3) /* Bypass Prescale R */ -#define LAST_ALC_ENABLE (1 << 2) /* Last ALC Enable */ -#define PRESCALE_BIAS(x) (((x) & 0x3) << 0) /* Prescale Bias <1:0> */ - -/* - * REG_TX_CAL_STATUS - */ -#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */ -#define COMP_OUT (1 << 6) /* Comp Out */ -#define CP_CAL_DONE (1 << 5) /* CP Cal Done */ -#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */ -#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */ - -/* - * REG_TX_VCO_CAL_REF - */ -#define VCO_CAL_REF_MONITOR (1 << 3) /* VCO Cal Ref Monitor */ -#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */ - -/* - * REG_TX_VCO_PD_OVERRIDES - */ -#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */ -#define POWER_DOWN_VARACT_REF_TCF (1 << 2) /* Power Down Varact Ref Tcf */ -#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */ -#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */ - -/* - * REG_TX_CP_OVERRANGE_VCO_LOCK - */ -#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */ -#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */ -#define VCO_LOCK (1 << 1) /* Lock */ - -/* - * REG_TX_VCO_LDO - */ -#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */ -#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */ -#define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */ -#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */ - -/* - * REG_TX_VCO_CAL - */ -#define VCO_CAL_EN (1 << 7) /* VCO Cal En */ -#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */ -#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count<1:0> */ -#define FB_CLOCK_ADV(x) (((x) & 0x3) << 0) /* FB Clock Adv<1:0> */ - -/* - * REG_TX_LOCK_DETECT_CONFIG - */ -#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */ -#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */ - -/* - * REG_TX_CP_LEVEL_DETECT - */ -#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */ -#define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */ -#define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */ - -/* - * REG_TX_DSM_SETUP_0 - */ -#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */ - -/* - * REG_TX_DSM_SETUP_1 - */ -#define SIF_CLOCK (1 << 6) /* SIF clock */ -#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */ -#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */ - -/* - * REG_TX_CORRECTION_WORD0 - */ -#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ -#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */ -#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */ - -/* - * REG_TX_CORRECTION_WORD1 - */ -#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */ -#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */ - -/* - * REG_TX_VCO_VARACTOR_CTRL_0 - */ -#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */ -#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */ - -/* - * REG_TX_VCO_VARACTOR_CTRL_1 - */ -#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */ - -/* - * REG_DCXO_COARSE_TUNE - */ -#define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */ - -/* - * REG_DCXO_FINE_TUNE_LOW - */ -#define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */ - -/* - * REG_DCXO_FINE_TUNE_HIGH - */ -#define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5) /* DCXO Tune Fine<12:5> */ - -/* - * REG_DCXO_CONFIG - */ -#define MUST_BE_ZERO (1 << 7) /* Must be zero */ -#define DCXO_RTAIL(x) (((x) & 0x7) << 4) /* DCXO Rtail<2:0> */ -#define DCXO_RD(x) (((x) & 0x3) << 2) /* DCXO Rd<1:0> */ - -/* - * REG_DCXO_TEMPCO_ADDR - */ -#define DCXO_TEMPCO_EN (1 << 7) /* DCXO Tempco En */ -#define DCXO_TEMPCO_CLK (1 << 6) /* DCXO Tempco Clk */ -#define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */ - -/* - * REG_TX_FAST_LOCK_SETUP - */ -#define TX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Tx Fast Lock Load Synth */ -#define TX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Tx Fast Lock Profile Init */ -#define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Tx Fast Lock Profile Pin Select */ -#define TX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Tx Fast Lock Mode Enable */ -#define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */ - -/* - * REG_TX_FAST_LOCK_PROGRAM_CTRL - */ -#define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Tx Fast Lock Program Write */ -#define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Tx Fast Lock Program Clock Enable */ - -/* - * REG_TX_LO_GEN_POWER_MODE - */ -#define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4) /* Power Mode<3:0> */ - -/* - * REG_BANDGAP_CONFIG0 - */ -#define POWER_DOWN_BANDGAP_REF (1 << 7) /* Power Down Bandgap Ref */ -#define MASTER_BIAS_FILTER_BYPASS (1 << 6) /* Master Bias Filter Bypass */ -#define MASTER_BIAS_REF_SEL (1 << 5) /* Master Bias Ref Sel */ -#define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */ - -/* - * REG_BANDGAP_CONFIG1 - */ -#define VCO_LDO_FILTER_BYPASS (1 << 7) /* VCO LDO Filter Bypass */ -#define VCO_LDO_REF_SEL (1 << 6) /* VCO LDO Ref Sel */ -#define BANDGAP_REF_RESET (1 << 5) /* Bandgap Ref Reset */ -#define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */ - -/* - * REG_REF_DIVIDE_CONFIG_1 - */ -#define REF_DIVIDE_CONFIG_1_DFLT (1 << 2) /* Set to 1 */ -#define RX_REF_RESET_BAR (1 << 1) /* Rx Ref Reset Bar */ -#define RX_REF_DIVIDER_MSB (1 << 0) /* Rx Ref Divider<1> */ - -/* - * REG_REF_DIVIDE_CONFIG_2 - */ -#define RX_REF_DIVIDER_LSB (1 << 7) /* Rx Ref Divider< 0> */ -#define TX_REF_RESET_BAR (1 << 4) /* Tx Ref Reset Bar */ -#define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */ -#define TX_REF_DIVIDER(x) (((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */ -#define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */ - -/* - * REG_GAIN_RX1,2 - */ -#define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */ - -/* - * REG_LPF_GAIN_RX1,2 - */ -#define LPF_GAIN_RX(x) (((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */ - -/* - * REG_DIG_GAIN_RX1,2 - */ -#define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */ - -/* - * REG_FAST_ATTACK_STATE - */ -#define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */ -#define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */ -#define FAST_ATK_MASK 0x7 -#define RX1_FAST_ATK_SHIFT 0 -#define RX2_FAST_ATK_SHIFT 4 -#define FAST_ATK_RESET 0 -#define FAST_ATK_PEAK_DETECT 1 -#define FAST_ATK_PWR_MEASURE 2 -#define FAST_ATK_FINAL_SETTELING 3 -#define FAST_ATK_FINAL_OVER 4 -#define FAST_ATK_GAIN_LOCKED 5 - -/* - * REG_SLOW_LOOP_STATE - */ -#define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */ -#define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */ - - -/* - * REG_OVRG_SIGS_RX1,2 - */ -#define GAIN_LOCK_1 (1 << 6) /* Gain Lock 1 */ -#define LOW_POWER_1 (1 << 5) /* Low Power 1 */ -#define LARGE_LMT_OL (1 << 4) /* Large LMT OL */ -#define SMALL_LMT_OL (1 << 3) /* Small LMT OL */ -#define LARGE_ADC_OL (1 << 2) /* Large ADC OL */ -#define SMALL_ADC_OL (1 << 1) /* Small ADC OL */ -#define DIG_SAT (1 << 0) /* Dig Sat */ -/* - * REG_CTRL - */ -#define CTRL_ENABLE (1 << 0) /* Set to 1 */ - -/* - * REG_BIST_CONFIG - */ -#define TONE_PRBS (1 << 1) /* Tone/ PRBS */ -#define BIST_ENABLE (1 << 0) /* BIST Enable */ -#define TONE_FREQ(x) (((x) & 0x3) << 6) /* Tone Frequency<1:0> */ -#define TONE_LEVEL(x) (((x) & 0x3) << 4) /* Tone Level<1:0> */ -#define BIST_CTRL_POINT(x) (((x) & 0x3) << 2) /* BIST Control Point <1:0> */ - -/* - * REG_OBSERVE_CONFIG - */ -#define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7) /* Data Port SP, HD Loop Test OE */ -#define RX_MASK (1 << 6) /* Rx Mask */ -#define CHANNEL (1 << 5) /* Channel */ -#define DATA_PORT_LOOP_TEST_ENABLE (1 << 0) /* Data Port Loop Test Enable */ -#define OBSERVATION_POINT(x) (((x) & 0xF) << 1) /* Observation Point<2:0> */ - -/* - * REG_BIST_AND_DATA_PORT_TEST_CONFIG - */ -#define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5) /* BIST Mask Channel 2 Q data */ -#define BIST_MASK_CHANNEL_2_I_DATA (1 << 4) /* BIST Mask Channel 2 I data */ -#define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3) /* BIST Mask Channel 1 Q data */ -#define BIST_MASK_CHANNEL_1_I_DATA (1 << 2) /* BIST Mask Channel 1 I data */ -#define DATA_PORT_HILOW (1 << 1) /* Data Port Hi/Low */ -#define USE_DATA_PORT (1 << 0) /* Use Data Port */ -#define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */ - -/* - * REG_DAC_TEST_2 - */ -#define DAC_TEST_ENABLE (1 << 7) /* DAC Test Enable */ -#define DAC_TEST_WORD(x) (((x) & 0x7F) << 0) /* DAC test Word <22:16> */ - -/* - * SPI Comm Helpers - */ -#define AD_READ (0 << 15) -#define AD_WRITE (1 << 15) -#define AD_CNT(x) ((((x) - 1) & 0x7) << 12) -#define AD_ADDR(x) ((x) & 0x3FF) - - -/* - * AD9361 Limits - */ - -#define RSSI_MULTIPLIER 100 -#define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER)) -#define RSSI_MAX_WEIGHT 255 - -#define MAX_LMT_INDEX 40 -#define MAX_LPF_GAIN 24 -#define MAX_DIG_GAIN 31 - -#define MAX_BBPLL_FREF 70007000UL /* 70 MHz + 100ppm */ -#define MIN_BBPLL_FREQ 714928500UL /* 715 MHz - 100ppm */ -#define MAX_BBPLL_FREQ 1430143000UL /* 1430 MHz + 100ppm */ -#define MAX_BBPLL_DIV 64 -#define MIN_BBPLL_DIV 2 - -/* - * The ADC minimum and maximum operating output data rates - * are 25MHz and 640MHz respectively. - * For more information see here: https://ez.analog.com/docs/DOC-12763 - */ - -#define MIN_ADC_CLK 25000000UL /* 25 MHz */ -#define MAX_ADC_CLK 640000000UL /* 640 MHz */ -#define MAX_DAC_CLK (MAX_ADC_CLK / 2) - -/* Associated with outputs of stage */ -#define MAX_RX_HB1 122880000UL -#define MAX_RX_HB2 245760000UL -#define MAX_RX_HB3 320000000UL -/* Associated with inputs of stage */ -#define MAX_TX_HB1 122880000UL -#define MAX_TX_HB2 245760000UL -#define MAX_TX_HB3 320000000UL - -#define MAX_BASEBAND_RATE 61440000UL - -#define MAX_MBYTE_SPI 8 - -#define RFPLL_MODULUS 8388593UL -#define BBPLL_MODULUS 2088960UL - -#define MAX_SYNTH_FREF 80008000UL /* 80 MHz + 100ppm */ -#define MIN_SYNTH_FREF 9999000UL /* 10 MHz - 100ppm */ -#define MIN_VCO_FREQ_HZ 6000000000ULL - -#define MAX_CARRIER_FREQ_HZ 6000000000ULL -#define MIN_RX_CARRIER_FREQ_HZ 70000000ULL -#define MIN_TX_CARRIER_FREQ_HZ 46875001ULL - -#define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL -#define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL - -#define MAX_GAIN_TABLE_SIZE 90 -#define MAX_NUM_GAIN_TABLES 16 /* randomly picked */ - -#define MAX_TX_ATTENUATION_DB 89750 - -#endif diff --git a/driver/ad9361/cf_axi_adc.h b/driver/ad9361/cf_axi_adc.h deleted file mode 100644 index d3553fd..0000000 --- a/driver/ad9361/cf_axi_adc.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * ADI-AIM ADI ADC Interface Module - * - * Copyright 2012-2017 Analog Devices Inc. - * - * Licensed under the GPL-2. - * - * http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467 - */ - -#ifndef ADI_AXI_ADC_H_ -#define ADI_AXI_ADC_H_ - -#include - -/* ADC COMMON */ - -#define ADI_REG_CONFIG 0x000C -#define ADI_IQCORRECTION_DISABLE (1 << 0) -#define ADI_DCFILTER_DISABLE (1 << 1) -#define ADI_DATAFORMAT_DISABLE (1 << 2) -#define ADI_USERPORTS_DISABLE (1 << 3) -#define ADI_MODE_1R1T (1 << 4) -#define ADI_SCALECORRECTION_ONLY (1 << 5) -#define ADI_CMOS_OR_LVDS_N (1 << 7) -#define ADI_PPS_RECEIVER_ENABLE (1 << 8) - -#define ADI_REG_RSTN 0x0040 -#define ADI_RSTN (1 << 0) -#define ADI_MMCM_RSTN (1 << 1) - -#define ADI_REG_CNTRL 0x0044 -#define ADI_R1_MODE (1 << 2) -#define ADI_DDR_EDGESEL (1 << 1) -#define ADI_PIN_MODE (1 << 0) - -#define ADI_REG_CLK_FREQ 0x0054 -#define ADI_CLK_FREQ(x) (((x) & 0xFFFFFFFF) << 0) -#define ADI_TO_CLK_FREQ(x) (((x) >> 0) & 0xFFFFFFFF) - -#define ADI_REG_CLK_RATIO 0x0058 -#define ADI_CLK_RATIO(x) (((x) & 0xFFFFFFFF) << 0) -#define ADI_TO_CLK_RATIO(x) (((x) >> 0) & 0xFFFFFFFF) - -#define ADI_REG_STATUS 0x005C -#define ADI_MUX_PN_ERR (1 << 3) -#define ADI_MUX_PN_OOS (1 << 2) -#define ADI_MUX_OVER_RANGE (1 << 1) -#define ADI_STATUS (1 << 0) - -#define ADI_REG_DELAY_CNTRL 0x0060 /* <= v8.0 */ -#define ADI_DELAY_SEL (1 << 17) -#define ADI_DELAY_RWN (1 << 16) -#define ADI_DELAY_ADDRESS(x) (((x) & 0xFF) << 8) -#define ADI_TO_DELAY_ADDRESS(x) (((x) >> 8) & 0xFF) -#define ADI_DELAY_WDATA(x) (((x) & 0x1F) << 0) -#define ADI_TO_DELAY_WDATA(x) (((x) >> 0) & 0x1F) - -#define ADI_REG_DELAY_STATUS 0x0064 /* <= v8.0 */ -#define ADI_DELAY_LOCKED (1 << 9) -#define ADI_DELAY_STATUS (1 << 8) -#define ADI_DELAY_RDATA(x) (((x) & 0x1F) << 0) -#define ADI_TO_DELAY_RDATA(x) (((x) >> 0) & 0x1F) - -#define ADI_REG_DRP_CNTRL 0x0070 -#define ADI_DRP_SEL (1 << 29) -#define ADI_DRP_RWN (1 << 28) -#define ADI_DRP_ADDRESS(x) (((x) & 0xFFF) << 16) -#define ADI_TO_DRP_ADDRESS(x) (((x) >> 16) & 0xFFF) -#define ADI_DRP_WDATA(x) (((x) & 0xFFFF) << 0) -#define ADI_TO_DRP_WDATA(x) (((x) >> 0) & 0xFFFF) - -#define ADI_REG_DRP_STATUS 0x0074 -#define ADI_DRP_STATUS (1 << 16) -#define ADI_DRP_RDATA(x) (((x) & 0xFFFF) << 0) -#define ADI_TO_DRP_RDATA(x) (((x) >> 0) & 0xFFFF) - -#define ADI_REG_DMA_STATUS 0x0088 -#define ADI_DMA_OVF (1 << 2) -#define ADI_DMA_UNF (1 << 1) -#define ADI_DMA_STATUS (1 << 0) - -#define ADI_REG_DMA_BUSWIDTH 0x008C -#define ADI_DMA_BUSWIDTH(x) (((x) & 0xFFFFFFFF) << 0) -#define ADI_TO_DMA_BUSWIDTH(x) (((x) >> 0) & 0xFFFFFFFF) - -#define ADI_REG_USR_CNTRL_1 0x00A0 -#define ADI_USR_CHANMAX(x) (((x) & 0xFF) << 0) -#define ADI_TO_USR_CHANMAX(x) (((x) >> 0) & 0xFF) - -#define ADI_REG_GP_CONTROL 0x00BC - -#define ADI_REG_CLOCKS_PER_PPS 0x00C0 -#define ADI_REG_CLOCKS_PER_PPS_STATUS 0x00C4 -#define ADI_CLOCKS_PER_PPS_STAT_INVAL (1 << 0) - -/* ADC CHANNEL */ - -#define ADI_REG_CHAN_CNTRL(c) (0x0400 + (c) * 0x40) -#define ADI_PN_SEL (1 << 10) /* !v8.0 */ -#define ADI_IQCOR_ENB (1 << 9) -#define ADI_DCFILT_ENB (1 << 8) -#define ADI_FORMAT_SIGNEXT (1 << 6) -#define ADI_FORMAT_TYPE (1 << 5) -#define ADI_FORMAT_ENABLE (1 << 4) -#define ADI_PN23_TYPE (1 << 1) /* !v8.0 */ -#define ADI_ENABLE (1 << 0) - -#define ADI_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40) -#define ADI_PN_ERR (1 << 2) -#define ADI_PN_OOS (1 << 1) -#define ADI_OVER_RANGE (1 << 0) - -#define ADI_REG_CHAN_CNTRL_1(c) (0x0410 + (c) * 0x40) -#define ADI_DCFILT_OFFSET(x) (((x) & 0xFFFF) << 16) -#define ADI_TO_DCFILT_OFFSET(x) (((x) >> 16) & 0xFFFF) -#define ADI_DCFILT_COEFF(x) (((x) & 0xFFFF) << 0) -#define ADI_TO_DCFILT_COEFF(x) (((x) >> 0) & 0xFFFF) - -#define ADI_REG_CHAN_CNTRL_2(c) (0x0414 + (c) * 0x40) -#define ADI_IQCOR_COEFF_1(x) (((x) & 0xFFFF) << 16) -#define ADI_TO_IQCOR_COEFF_1(x) (((x) >> 16) & 0xFFFF) -#define ADI_IQCOR_COEFF_2(x) (((x) & 0xFFFF) << 0) -#define ADI_TO_IQCOR_COEFF_2(x) (((x) >> 0) & 0xFFFF) - -#define ADI_REG_CHAN_CNTRL_3(c) (0x0418 + (c) * 0x40) /* v8.0 */ -#define ADI_ADC_PN_SEL(x) (((x) & 0xF) << 16) -#define ADI_TO_ADC_PN_SEL(x) (((x) >> 16) & 0xF) -#define ADI_ADC_DATA_SEL(x) (((x) & 0xF) << 0) -#define ADI_TO_ADC_DATA_SEL(x) (((x) >> 0) & 0xF) - -enum adc_pn_sel { - ADC_PN9 = 0, - ADC_PN23A = 1, - ADC_PN7 = 4, - ADC_PN15 = 5, - ADC_PN23 = 6, - ADC_PN31 = 7, - ADC_PN_CUSTOM = 9, - ADC_PN_OFF = 10, -}; - -enum adc_data_sel { - ADC_DATA_SEL_NORM, - ADC_DATA_SEL_LB, /* DAC loopback */ - ADC_DATA_SEL_RAMP, /* TBD */ -}; - -#define ADI_REG_CHAN_USR_CNTRL_1(c) (0x0420 + (c) * 0x40) -#define ADI_USR_DATATYPE_BE (1 << 25) -#define ADI_USR_DATATYPE_SIGNED (1 << 24) -#define ADI_USR_DATATYPE_SHIFT(x) (((x) & 0xFF) << 16) -#define ADI_TO_USR_DATATYPE_SHIFT(x) (((x) >> 16) & 0xFF) -#define ADI_USR_DATATYPE_TOTAL_BITS(x) (((x) & 0xFF) << 8) -#define ADI_TO_USR_DATATYPE_TOTAL_BITS(x) (((x) >> 8) & 0xFF) -#define ADI_USR_DATATYPE_BITS(x) (((x) & 0xFF) << 0) -#define ADI_TO_USR_DATATYPE_BITS(x) (((x) >> 0) & 0xFF) - -#define ADI_REG_CHAN_USR_CNTRL_2(c) (0x0424 + (c) * 0x40) -#define ADI_USR_DECIMATION_M(x) (((x) & 0xFFFF) << 16) -#define ADI_TO_USR_DECIMATION_M(x) (((x) >> 16) & 0xFFFF) -#define ADI_USR_DECIMATION_N(x) (((x) & 0xFFFF) << 0) -#define ADI_TO_USR_DECIMATION_N(x) (((x) >> 0) & 0xFFFF) - -#define ADI_REG_ADC_DP_DISABLE 0x00C0 - -/* PCORE Version > 8.00 */ -#define ADI_REG_DELAY(l) (0x0800 + (l) * 0x4) - -/* debugfs direct register access */ -#define DEBUGFS_DRA_PCORE_REG_MAGIC 0x80000000 - -#define AXIADC_MAX_CHANNEL 16 - -#include -#include - -struct axiadc_chip_info { - char *name; - unsigned num_channels; - unsigned num_shadow_slave_channels; - const unsigned long *scan_masks; - const int (*scale_table)[2]; - int num_scales; - int max_testmode; - unsigned long max_rate; - struct iio_chan_spec channel[AXIADC_MAX_CHANNEL]; -}; - -struct axiadc_state { - struct device *dev_spi; - struct iio_info iio_info; - struct clk *clk; - struct gpio_desc *gpio_decimation; - size_t regs_size; - void __iomem *regs; - void __iomem *slave_regs; - unsigned max_usr_channel; - unsigned adc_def_output_mode; - unsigned max_count; - unsigned id; - unsigned pcore_version; - unsigned decimation_factor; - unsigned int oversampling_ratio; - bool dp_disable; - unsigned long long adc_clk; - unsigned have_slave_channels; - bool additional_channel; - - struct iio_hw_consumer *frontend; - - struct iio_chan_spec channels[AXIADC_MAX_CHANNEL]; -}; - -struct axiadc_converter { - struct spi_device *spi; - struct clk *clk; - struct clock_scale adc_clkscale; - struct clk *lane_clk; - struct clk *sysref_clk; - void *phy; - struct gpio_desc *pwrdown_gpio; - struct gpio_desc *reset_gpio; - unsigned id; - unsigned adc_output_mode; - unsigned testmode[AXIADC_MAX_CHANNEL]; - unsigned scratch_reg[AXIADC_MAX_CHANNEL]; - unsigned long adc_clk; - const struct axiadc_chip_info *chip_info; - - struct delayed_work watchdog_work; - bool sample_rate_read_only; - - int (*reg_access)(struct iio_dev *indio_dev, unsigned int reg, - unsigned int writeval, unsigned int *readval); - int (*setup)(struct spi_device *spi, unsigned mode); - - struct iio_chan_spec const *channels; - int num_channels; - const struct attribute_group *attrs; - struct iio_dev *indio_dev; - int (*read_raw)(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long mask); - - int (*write_raw)(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask); - - int (*read_event_value)(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - enum iio_event_type type, - enum iio_event_direction dir, - enum iio_event_info info, - int *val, - int *val2); - - int (*write_event_value)(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - enum iio_event_type type, - enum iio_event_direction dir, - enum iio_event_info info, - int val, - int val2); - - int (*read_event_config)(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan, - enum iio_event_type type, - enum iio_event_direction dir); - - int (*write_event_config)(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan, - enum iio_event_type type, - enum iio_event_direction dir, - int state); - - int (*post_setup)(struct iio_dev *indio_dev); - int (*post_iio_register)(struct iio_dev *indio_dev); - int (*set_pnsel)(struct iio_dev *indio_dev, unsigned chan, - enum adc_pn_sel sel); -}; - - - -static inline struct axiadc_converter *to_converter(struct device *dev) -{ - struct axiadc_converter *conv = spi_get_drvdata(to_spi_device(dev)); - - if (conv) - return conv; - - return ERR_PTR(-ENODEV); -}; - -struct axiadc_spidev { - struct device_node *of_nspi; - struct device *dev_spi; -}; - -/* - * IO accessors - */ - -static inline void axiadc_write(struct axiadc_state *st, unsigned reg, unsigned val) -{ - iowrite32(val, st->regs + reg); -} - -static inline unsigned int axiadc_read(struct axiadc_state *st, unsigned reg) -{ - return ioread32(st->regs + reg); -} - -static inline void axiadc_slave_write(struct axiadc_state *st, unsigned reg, unsigned val) -{ - iowrite32(val, st->slave_regs + reg); -} - -static inline unsigned int axiadc_slave_read(struct axiadc_state *st, unsigned reg) -{ - return ioread32(st->slave_regs + reg); -} - - -static inline void axiadc_idelay_set(struct axiadc_state *st, - unsigned lane, unsigned val) -{ - if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8) { - axiadc_write(st, ADI_REG_DELAY(lane), val); - } else { - axiadc_write(st, ADI_REG_DELAY_CNTRL, 0); - axiadc_write(st, ADI_REG_DELAY_CNTRL, - ADI_DELAY_ADDRESS(lane) - | ADI_DELAY_WDATA(val) - | ADI_DELAY_SEL); - } -} - -int axiadc_set_pnsel(struct axiadc_state *st, int channel, enum adc_pn_sel sel); -enum adc_pn_sel axiadc_get_pnsel(struct axiadc_state *st, - int channel, const char **name); - -int axiadc_configure_ring_stream(struct iio_dev *indio_dev, - const char *dma_name); -void axiadc_unconfigure_ring_stream(struct iio_dev *indio_dev); - -#endif /* ADI_AXI_ADC_H_ */ diff --git a/driver/hw_def.h b/driver/hw_def.h index b31c99c..01d9cee 100644 --- a/driver/hw_def.h +++ b/driver/hw_def.h @@ -1,7 +1,14 @@ -// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be +// Author: Xianjun jiao, Michael Mehari, Wei Liu +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later const char *sdr_compatible_str = "sdr,sdr"; +enum openwifi_fpga_type { + SMALL_FPGA = 0, + LARGE_FPGA = 1, +}; + enum openwifi_band { BAND_900M = 0, BAND_2_4GHZ, @@ -20,7 +27,7 @@ const char *tx_intf_compatible_str = "sdr,tx_intf"; #define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) #define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) -#define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) +#define TX_INTF_REG_CSI_FUZZER_ADDR (5*4) #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) #define TX_INTF_REG_MISC_SEL_ADDR (7*4) #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) @@ -54,7 +61,7 @@ const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10}; const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v struct tx_intf_driver_api { - u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); + u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type); u32 (*reg_read)(u32 reg); void (*reg_write)(u32 reg, u32 value); @@ -64,7 +71,7 @@ struct tx_intf_driver_api { u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void); u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); - u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); + u32 (*TX_INTF_REG_CSI_FUZZER_read)(void); u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); u32 (*TX_INTF_REG_MISC_SEL_read)(void); u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); @@ -84,7 +91,7 @@ struct tx_intf_driver_api { void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value); void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); - void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); + void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value); void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); void (*TX_INTF_REG_MISC_SEL_write)(u32 value); void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); @@ -182,6 +189,7 @@ const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; #define OPENOFDM_RX_REG_ENABLE_ADDR (1*4) #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) +#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4) #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) enum openofdm_rx_mode { @@ -204,6 +212,7 @@ struct openofdm_rx_driver_api { void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value); void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); + void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value); }; // ---------------------------------------openofdm tx------------------------------- @@ -240,21 +249,22 @@ struct openofdm_tx_driver_api { const char *xpu_compatible_str = "sdr,xpu"; -#define XPU_REG_MULTI_RST_ADDR (0*4) -#define XPU_REG_SRC_SEL_ADDR (1*4) -#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) -#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) -#define XPU_REG_BAND_CHANNEL_ADDR (4*4) -#define XPU_REG_DIFS_ADVANCE_ADDR (5*4) -#define XPU_REG_RSSI_DB_CFG_ADDR (7*4) -#define XPU_REG_LBT_TH_ADDR (8*4) -#define XPU_REG_CSMA_DEBUG_ADDR (9*4) -#define XPU_REG_BB_RF_DELAY_ADDR (10*4) -#define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4) -#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) -#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) -#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) -#define XPU_REG_CSMA_CFG_ADDR (19*4) +#define XPU_REG_MULTI_RST_ADDR (0*4) +#define XPU_REG_SRC_SEL_ADDR (1*4) +#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) +#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) +#define XPU_REG_BAND_CHANNEL_ADDR (4*4) +#define XPU_REG_DIFS_ADVANCE_ADDR (5*4) +#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4) +#define XPU_REG_RSSI_DB_CFG_ADDR (7*4) +#define XPU_REG_LBT_TH_ADDR (8*4) +#define XPU_REG_CSMA_DEBUG_ADDR (9*4) +#define XPU_REG_BB_RF_DELAY_ADDR (10*4) +#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4) +#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) +#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) +#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) +#define XPU_REG_CSMA_CFG_ADDR (19*4) #define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) #define XPU_REG_SLICE_COUNT_START_ADDR (21*4) @@ -341,6 +351,9 @@ struct xpu_driver_api { void (*XPU_REG_DIFS_ADVANCE_write)(u32 value); u32 (*XPU_REG_DIFS_ADVANCE_read)(void); + void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value); + u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void); + u32 (*XPU_REG_TRX_STATUS_read)(void); u32 (*XPU_REG_TX_RESULT_read)(void); @@ -384,7 +397,9 @@ struct xpu_driver_api { u32 (*XPU_REG_SLICE_COUNT_END1_read)(void); void (*XPU_REG_BB_RF_DELAY_write)(u32 value); - void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value); + + void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value); + u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void); void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr); }; diff --git a/driver/make_all.sh b/driver/make_all.sh index 39163a0..949daff 100755 --- a/driver/make_all.sh +++ b/driver/make_all.sh @@ -1,12 +1,17 @@ #!/bin/bash -if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)" + +# Author: Xianjun jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -ne 2 ]; then + echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)" exit 1 fi -OPENWIFI_DIR=$1 -XILINX_DIR=$2 -ARCH_OPTION=$3 +OPENWIFI_DIR=$(pwd)/../ +XILINX_DIR=$1 +ARCH_OPTION=$2 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" @@ -34,10 +39,12 @@ if [ "$ARCH_OPTION" == "64" ]; then LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/ ARCH="arm64" CROSS_COMPILE="aarch64-linux-gnu-" + echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h else LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/ ARCH="arm" CROSS_COMPILE="arm-linux-gnueabihf-" + echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h fi # check if user entered the right path to analog device linux @@ -65,9 +72,7 @@ cd $OPENWIFI_DIR/driver/rx_intf make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE cd $OPENWIFI_DIR/driver/xpu make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE -cd $OPENWIFI_DIR/driver/ad9361 -make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE -cd $OPENWIFI_DIR/driver/xilinx_dma -./make_xilinx_dma.sh $OPENWIFI_DIR $XILINX_DIR $ARCH_OPTION +# cd $OPENWIFI_DIR/driver/ad9361 +# make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE cd $home_dir diff --git a/driver/openofdm_rx/openofdm_rx.c b/driver/openofdm_rx/openofdm_rx.c index beb101c..f78ae84 100644 --- a/driver/openofdm_rx/openofdm_rx.c +++ b/driver/openofdm_rx/openofdm_rx.c @@ -1,7 +1,8 @@ /* - * axi lite register access driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun jiao, Michael Mehari, Wei Liu + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include @@ -51,7 +52,9 @@ static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) { static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data); } - +static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) { + reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data); +} static const struct of_device_id dev_of_ids[] = { { .compatible = "sdr,openofdm_rx", }, {} @@ -94,6 +97,7 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){ // 1) power threshold configuration and reset openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0); openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100); + openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write(1); //rst for (i=0;i<8;i++) @@ -139,6 +143,7 @@ static int dev_probe(struct platform_device *pdev) openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write; openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; + openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write; /* Request and map I/O memory */ io = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/driver/openofdm_tx/openofdm_tx.c b/driver/openofdm_tx/openofdm_tx.c index d9b5f1f..d94351c 100644 --- a/driver/openofdm_tx/openofdm_tx.c +++ b/driver/openofdm_tx/openofdm_tx.c @@ -1,7 +1,9 @@ /* * axi lite register access driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun jiao, Michael Mehari, Wei Liu + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include diff --git a/driver/rx_intf/rx_intf.c b/driver/rx_intf/rx_intf.c index 7e6cb25..8662905 100644 --- a/driver/rx_intf/rx_intf.c +++ b/driver/rx_intf/rx_intf.c @@ -1,7 +1,9 @@ /* * axi lite register access driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun Jiao, Michael Mehari, Wei Liu + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include @@ -287,7 +289,7 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 //rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); - //0x000-normal; 0x100-sig and fcs valid are controled by bit4 and bit0; + //0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0; //0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0); diff --git a/driver/sdr.c b/driver/sdr.c index 33adb3d..6972401 100644 --- a/driver/sdr.c +++ b/driver/sdr.c @@ -1,4 +1,6 @@ -//Author: Xianjun Jiao. putaoshu@msn.com; xianjun.jiao@imec.be +// Author: Xianjun Jiao, Michael Mehari, Wei Liu +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later #include #include @@ -43,11 +45,16 @@ #include #define IIO_AD9361_USE_PRIVATE_H_ -#include "ad9361/ad9361_regs.h" -#include "ad9361/ad9361.h" -#include "ad9361/ad9361_private.h" +#include <../../drivers/iio/adc/ad9361_regs.h> +#include <../../drivers/iio/adc/ad9361.h> +#include <../../drivers/iio/adc/ad9361_private.h> #include <../../drivers/iio/frequency/cf_axi_dds.h> +extern int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num); +extern int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, + bool tx1, bool tx2, bool immed); +extern int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, + struct ctrl_outs_control *ctrl); #include "../user_space/sdrctl_src/nl80211_testmode_def.h" #include "hw_def.h" @@ -126,14 +133,15 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev, u32 actual_rx_lo = conf->chandef.chan->center_freq - priv->rx_freq_offset_to_lo_MHz + priv->drv_rx_reg_val[DRV_RX_REG_IDX_EXTRA_FO]; u32 actual_tx_lo; bool change_flag = (actual_rx_lo != priv->actual_rx_lo); + int static_lbt_th, auto_lbt_th, fpga_lbt_th; if (change_flag) { priv->actual_rx_lo = actual_rx_lo; actual_tx_lo = conf->chandef.chan->center_freq - priv->tx_freq_offset_to_lo_MHz; - ad9361_clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo )>>1) ); - ad9361_clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo )>>1) ); + clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo )>>1) ); + clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo )>>1) ); if (actual_rx_lo<2412) { priv->rssi_correction = 153; @@ -150,8 +158,14 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev, } // xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62)<<1); // -62dBm - xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44 + // xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44 + auto_lbt_th = ((priv->rssi_correction-62-16)<<1); + static_lbt_th = priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]; + fpga_lbt_th = (static_lbt_th==0?auto_lbt_th:static_lbt_th); + xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th); + priv->last_auto_fpga_lbt_th = auto_lbt_th; + if (actual_rx_lo < 2500) { //priv->slot_time = 20; //20 is default slot time in ERP(OFDM)/11g 2.4G; short one is 9. //xpu_api->XPU_REG_BAND_CHANNEL_write(BAND_2_4GHZ<<16); @@ -183,8 +197,8 @@ static void ad9361_rf_set_channel(struct ieee80211_hw *dev, //printk("%s ad9361_rf_set_channel tune to %d read back %llu\n", sdr_compatible_str,conf->chandef.chan->center_freq,2*priv->ad9361_phy->state->current_rx_lo_freq); //ad9361_set_trx_clock_chain_default(priv->ad9361_phy); //printk("%s ad9361_rf_set_channel tune to %d read back %llu\n", sdr_compatible_str,conf->chandef.chan->center_freq,2*priv->ad9361_phy->state->current_rx_lo_freq); + printk("%s ad9361_rf_set_channel %dM rssi_correction %d (change flag %d) fpga_lbt_th %d (auto %d static %d)\n", sdr_compatible_str,conf->chandef.chan->center_freq,priv->rssi_correction,change_flag,fpga_lbt_th,auto_lbt_th,static_lbt_th); } - printk("%s ad9361_rf_set_channel %dM rssi_correction %d (change flag %d)\n", sdr_compatible_str,conf->chandef.chan->center_freq,priv->rssi_correction,change_flag); } const struct openwifi_rf_ops ad9361_rf_ops = { @@ -229,8 +243,8 @@ static int openwifi_init_tx_ring(struct openwifi_priv *priv, int ring_idx) for (i = 0; i < NUM_TX_BD; i++) { ring->bds[i].skb_linked=0; // for tx, skb is from upper layer - //at frist right after skb allocated, head, data, tail are the same. - ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from uppler layer in tx routine + //at first right after skb allocated, head, data, tail are the same. + ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from upper layer in tx routine } return 0; @@ -253,8 +267,8 @@ static void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx) // dev_kfree_skb(ring->bds[i].skb_linked); // only use dev_kfree_skb when there is exception if ( (ring->bds[i].dma_mapping_addr != 0 && ring->bds[i].skb_linked == 0) || (ring->bds[i].dma_mapping_addr == 0 && ring->bds[i].skb_linked != 0)) - printk("%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08llx\n", sdr_compatible_str, - ring_idx, i, (void*)(ring->bds[i].skb_linked), ring->bds[i].dma_mapping_addr); + printk("%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08x\n", sdr_compatible_str, + ring_idx, i, (void*)(ring->bds[i].skb_linked), (unsigned int)(ring->bds[i].dma_mapping_addr)); ring->bds[i].skb_linked=0; ring->bds[i].dma_mapping_addr = 0; @@ -266,12 +280,24 @@ static void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx) static int openwifi_init_rx_ring(struct openwifi_priv *priv) { + int i; + u8 *pdata_tmp; + priv->rx_cyclic_buf = dma_alloc_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,&priv->rx_cyclic_buf_dma_mapping_addr,GFP_KERNEL); if (!priv->rx_cyclic_buf) { printk("%s openwifi_init_rx_ring: WARNING dma_alloc_coherent failed!\n", sdr_compatible_str); dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr); return(-1); } + + // Set tsft_low and tsft_high to 0. If they are not zero, it means there is a packet in the buffer by DMA + for (i=0; irx_cyclic_buf + i*RX_BD_BUF_SIZE; // our header insertion is at the beginning + (*((u32*)(pdata_tmp+0 ))) = 0; + (*((u32*)(pdata_tmp+4 ))) = 0; + } + printk("%s openwifi_init_rx_ring: tsft_low and tsft_high are cleared!\n", sdr_compatible_str); + return 0; } @@ -317,20 +343,29 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id) struct ieee80211_hdr *hdr; u32 addr1_low32=0, addr2_low32=0, addr3_low32=0, len, rate_idx, tsft_low, tsft_high, loop_count=0, ht_flag, short_gi;//, fc_di; // u32 dma_driver_buf_idx_mod; - u8 *pdata_tmp, fcs_ok, target_buf_idx;//, phy_rx_sn_hw; + u8 *pdata_tmp, fcs_ok;//, target_buf_idx;//, phy_rx_sn_hw; s8 signal; - u16 rssi_val, addr1_high16=0, addr2_high16=0, addr3_high16=0, sc=0; + u16 agc_status_and_pkt_exist_flag, rssi_val, addr1_high16=0, addr2_high16=0, addr3_high16=0, sc=0; bool content_ok = false, len_overflow = false; - struct dma_tx_state state; - static u8 target_buf_idx_old = 0xFF; +#ifdef USE_NEW_RX_INTERRUPT + int i; spin_lock(&priv->lock); - priv->rx_chan->device->device_tx_status(priv->rx_chan,priv->rx_cookie,&state); - target_buf_idx = ((state.residue-1)&(NUM_RX_BD-1)); - - while( target_buf_idx_old!=target_buf_idx ) { // loop all rx buffers that have new rx packets - target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1)); + for (i=0; irx_cyclic_buf + i*RX_BD_BUF_SIZE; + agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10))); //check rx_intf_pl_to_m_axis.v. FPGA TODO: add pkt exist 1bit flag next to gpio_status_lock_by_sig_valid + if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer + continue; +#else + static u8 target_buf_idx_old = 0; + spin_lock(&priv->lock); + while(1) { // loop all rx buffers that have new rx packets pdata_tmp = priv->rx_cyclic_buf + target_buf_idx_old*RX_BD_BUF_SIZE; // our header insertion is at the beginning + agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10))); + if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer + break; +#endif + tsft_low = (*((u32*)(pdata_tmp+0 ))); tsft_high = (*((u32*)(pdata_tmp+4 ))); rssi_val = (*((u16*)(pdata_tmp+8 ))); @@ -388,11 +423,15 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id) if (len>=28) sc = hdr->seq_ctrl; - if ( addr1_low32!=0xffffffff || addr1_high16!=0xffff ) + if ( (addr1_low32!=0xffffffff || addr1_high16!=0xffff) || (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&4) ) printk("%s openwifi_rx_interrupt:%4dbytes ht%d %3dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x fcs%d buf_idx%d %ddBm\n", sdr_compatible_str, len, ht_flag, wifi_rate_table[rate_idx], hdr->frame_control, hdr->duration_id, reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32), +#ifdef USE_NEW_RX_INTERRUPT + sc, fcs_ok, i, signal); +#else sc, fcs_ok, target_buf_idx_old, signal); +#endif } // priv->phy_rx_sn_hw_old = phy_rx_sn_hw; @@ -424,7 +463,11 @@ static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id) } else printk("%s openwifi_rx_interrupt: WARNING dev_alloc_skb failed!\n", sdr_compatible_str); } + (*((u16*)(pdata_tmp+10))) = 0; // clear the field (set by rx_intf_pl_to_m_axis.v) to indicate the packet has been processed loop_count++; +#ifndef USE_NEW_RX_INTERRUPT + target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1)); +#endif } if ( loop_count!=1 && (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&1) ) @@ -442,7 +485,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id) struct openwifi_ring *ring; struct sk_buff *skb; struct ieee80211_tx_info *info; - u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, loop_count=0;//, i; + u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, num_slot_random, cw, loop_count=0;//, i; u8 tx_result_report; // u16 prio_rd_idx_store[64]={0}; @@ -450,8 +493,15 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id) while(1) { // loop all packets that have been sent by FPGA reg_val = tx_intf_api->TX_INTF_REG_PKT_INFO_read(); - if (reg_val!=0x7FFFF) { - prio = (reg_val>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE)); + if (reg_val!=0xFFFFFFFF) { + prio = ((0x7FFFF & reg_val)>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE)); + cw = ((0xF0000000 & reg_val) >> 28); + num_slot_random = ((0xFF80000 ®_val)>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE)); + if(cw > 10) { + cw = 10 ; + num_slot_random += 512 ; + } + ring = &(priv->tx_ring[prio]); ring->bd_rd_idx = ((reg_val>>5)&MAX_PHY_TX_SN); skb = ring->bds[ring->bd_rd_idx].skb_linked; @@ -506,6 +556,8 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id) if ( (tx_result_report&0x10) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&1) ) printk("%s openwifi_tx_interrupt: WARNING tx_result %02x prio%d wr%d rd%d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx); + if ( ( (!(info->flags & IEEE80211_TX_CTL_NO_ACK))||(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&4) ) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&2) ) + printk("%s openwifi_tx_interrupt: tx_result %02x prio%d wr%d rd%d num_rand_slot %d cw %d \n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx, num_slot_random,cw); ieee80211_tx_status_irqsafe(dev, skb); @@ -685,7 +737,7 @@ static void openwifi_tx(struct ieee80211_hw *dev, } } //} - queue_idx = (i>=MAX_NUM_HW_QUEUE?2:i); // if no address is hit, use FPGA queue 2. becuase the queue 2 is the longest. + queue_idx = (i>=MAX_NUM_HW_QUEUE?2:i); // if no address is hit, use FPGA queue 2. because the queue 2 is the longest. } // -------------------- end of Map Linux/SW "prio" to hardware "queue_idx" ------------------ @@ -769,7 +821,7 @@ static void openwifi_tx(struct ieee80211_hw *dev, sc = hdr->seq_ctrl; } - if ( (!addr_flag) && (priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&2) ) + if ( ( (!addr_flag)||(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&4) ) && (priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&2) ) printk("%s openwifi_tx: %4dbytes ht%d %3dM FC%04x DI%04x addr1/2/3:%04x%08x/%04x%08x/%04x%08x SC%04x flag%08x retr%d ack%d prio%d q%d wr%d rd%d\n", sdr_compatible_str, len_mac_pdu, (use_ht_rate == false ? 0 : 1), (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]),frame_control,duration_id, reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32), @@ -818,7 +870,6 @@ static void openwifi_tx(struct ieee80211_hw *dev, skb_push( skb, LEN_PHY_HEADER ); rate_signal_value = calc_phy_header(rate_hw_value, use_ht_rate, use_short_gi, len_mac_pdu+LEN_PHY_CRC, skb->data); //fill the phy header - //make sure dma length is integer times of DDC_NUM_BYTE_PER_DMA_SYMBOL if (skb_tailroom(skb)bd_wr_idx); @@ -827,7 +878,7 @@ static void openwifi_tx(struct ieee80211_hw *dev, } skb_put( skb, num_byte_pad ); - retry_limit_hw_value = (retry_limit_raw - 1)&0xF; + retry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) ); dma_buf = skb->data; cts_rate_signal_value = wifi_mcs_table_11b_force_up[cts_rate_hw_value]; @@ -839,8 +890,8 @@ static void openwifi_tx(struct ieee80211_hw *dev, */ //wmb(); // entry->flags = cpu_to_le32(tx_flags); - /* We must be sure this has been written before followings HW - * register write, because this write will made the HW attempts + /* We must be sure this has been written before following HW + * register write, because this write will make the HW attempts * to DMA the just-written data */ //wmb(); @@ -899,7 +950,7 @@ static void openwifi_tx(struct ieee80211_hw *dev, goto openwifi_tx_after_dma_mapping; } - // seems everything ok. let's mark this pkt in bd descriptor ring + // seems everything is ok. let's mark this pkt in bd descriptor ring ring->bds[ring->bd_wr_idx].skb_linked = skb; ring->bds[ring->bd_wr_idx].dma_mapping_addr = dma_mapping_addr; @@ -975,28 +1026,27 @@ static int openwifi_start(struct ieee80211_hw *dev) priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg]; rx_intf_api->hw_init(priv->rx_intf_cfg,8,8); - tx_intf_api->hw_init(priv->tx_intf_cfg,8,8); + tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type); openofdm_tx_api->hw_init(priv->openofdm_tx_cfg); openofdm_rx_api->hw_init(priv->openofdm_rx_cfg); xpu_api->hw_init(priv->xpu_cfg); agc_gain_delay = 50; //samples - rssi_half_db_offset = 150; + rssi_half_db_offset = 150; // to be consistent xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) ); xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) ); openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0); - // rssi_half_db_th = 87<<1; // -62dBm // will settup in runtime in _rf_set_channel + // rssi_half_db_th = 87<<1; // -62dBm // will setup in runtime in _rf_set_channel // xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it - - // xpu_api->XPU_REG_CSMA_CFG_write(3); // cw_min -- already set in xpu.c + xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals //xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!) //xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51+23)<<16)|(0+23) );//we have more time when we use FIR in AD9361 - xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) - xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) + xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) + xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed @@ -1048,19 +1098,19 @@ static int openwifi_start(struct ieee80211_hw *dev) } priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm"); - if (IS_ERR(priv->rx_chan)) { + if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) { ret = PTR_ERR(priv->rx_chan); - pr_err("%s openwifi_start: No Rx channel %d\n",sdr_compatible_str,ret); + pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan); goto err_dma; } priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s"); - if (IS_ERR(priv->tx_chan)) { + if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) { ret = PTR_ERR(priv->tx_chan); - pr_err("%s openwifi_start: No Tx channel %d\n",sdr_compatible_str,ret); + pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan); goto err_dma; } - printk("%s openwifi_start: DMA channel setup successfully.\n",sdr_compatible_str); + printk("%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\n",sdr_compatible_str, priv->rx_chan, priv->tx_chan); ret = openwifi_init_rx_ring(priv); if (ret) { @@ -1093,7 +1143,7 @@ static int openwifi_start(struct ieee80211_hw *dev) priv->irq_tx = irq_of_parse_and_map(priv->pdev->dev.of_node, 3); ret = request_irq(priv->irq_tx, openwifi_tx_interrupt, - IRQF_SHARED, "sdr,tx_itrpt1", dev); + IRQF_SHARED, "sdr,tx_itrpt", dev); if (ret) { wiphy_err(dev->wiphy, "openwifi_start: failed to register IRQ handler openwifi_tx_interrupt\n"); goto err_free_rings; @@ -1378,12 +1428,35 @@ static void openwifi_bss_info_changed(struct ieee80211_hw *dev, changed&BSS_CHANGED_BEACON_ENABLED,changed&BSS_CHANGED_BEACON); } } +// helper function +u32 log2val(u32 val){ + u32 ret_val = 0 ; + while(val>1){ + val = val >> 1 ; + ret_val ++ ; + } + return ret_val ; +} static int openwifi_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, const struct ieee80211_tx_queue_params *params) { - printk("%s openwifi_conf_tx: WARNING [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", + u32 reg_val, cw_min_exp, cw_max_exp; + + printk("%s openwifi_conf_tx: [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\n", sdr_compatible_str,queue,params->aifs,params->cw_min,params->cw_max,params->txop); + + reg_val=xpu_api->XPU_REG_CSMA_CFG_read(); + cw_min_exp = (log2val(params->cw_min + 1) & 0x0F); + cw_max_exp = (log2val(params->cw_max + 1) & 0x0F); + switch(queue){ + case 0: reg_val = ( (reg_val & 0xFFFFFF00) | ((cw_min_exp | (cw_max_exp << 4)) << 0) ); break; + case 1: reg_val = ( (reg_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8) ); break; + case 2: reg_val = ( (reg_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16) ); break; + case 3: reg_val = ( (reg_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24) ); break; + default: printk("%s openwifi_conf_tx: WARNING queue %d does not exist",sdr_compatible_str, queue); return(0); + } + xpu_api->XPU_REG_CSMA_CFG_write(reg_val); return(0); } @@ -1620,9 +1693,11 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * if (!tb[OPENWIFI_ATTR_RSSI_TH]) return -EINVAL; tmp = nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]); - printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp); - xpu_api->XPU_REG_LBT_TH_write(tmp); - return 0; + // printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp); + // xpu_api->XPU_REG_LBT_TH_write(tmp); + // return 0; + printk("%s WARNING Please use command: sdrctl dev sdr0 set reg drv_xpu 0 reg_value! (1~2047, 0 means AUTO)!\n", sdr_compatible_str); + return -EOPNOTSUPP; case OPENWIFI_CMD_GET_RSSI_TH: skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32))); if (!skb) @@ -1653,7 +1728,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * reg_addr_idx = (reg_addr>>2); printk("%s recv set cmd reg cat %d addr %08x val %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_val, reg_addr_idx); if (reg_cat==1) - printk("%s reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str); + printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str); else if (reg_cat==2) rx_intf_api->reg_write(reg_addr,reg_val); else if (reg_cat==3) @@ -1677,7 +1752,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * //priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg]; } } else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else if (reg_cat==8) { if (reg_addr_idx>=0 && reg_addr_idxtx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg]; } } else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else if (reg_cat==9) { - if (reg_addr_idx>=0 && reg_addr_idx=0 && reg_addr_idxdrv_xpu_reg_val[reg_addr_idx]=reg_val; - else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) { + if (reg_val) { + xpu_api->XPU_REG_LBT_TH_write(reg_val); + printk("%s override FPGA LBT threshold to %d. The last_auto_fpga_lbt_th %d\n", sdr_compatible_str, reg_val, priv->last_auto_fpga_lbt_th); + } else { + xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th); + printk("%s Restore last_auto_fpga_lbt_th %d to FPGA. ad9361_rf_set_channel will take control\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th); + } + } + } else + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else - printk("%s reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat); + printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat); return 0; case REG_CMD_GET: @@ -1717,7 +1801,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * reg_addr_idx = (reg_addr>>2); printk("%s recv get cmd reg cat %d addr %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_addr_idx); if (reg_cat==1) { - printk("%s reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str); + printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str); tmp = 0xFFFFFFFF; } else if (reg_cat==2) @@ -1743,7 +1827,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * } tmp = priv->drv_rx_reg_val[reg_addr_idx]; } else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else if (reg_cat==8) { if (reg_addr_idx>=0 && reg_addr_idxdrv_tx_reg_val[reg_addr_idx]; } else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else if (reg_cat==9) { if (reg_addr_idx>=0 && reg_addr_idxdrv_xpu_reg_val[reg_addr_idx]; else - printk("%s reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); + printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx); } else - printk("%s reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat); + printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat); if (nla_put_u32(skb, REG_ATTR_VAL, tmp)) goto nla_put_failure; @@ -1833,7 +1917,7 @@ static int openwifi_dev_probe(struct platform_device *pdev) struct ieee80211_hw *dev; struct openwifi_priv *priv; int err=1, rand_val; - const char *chip_name; + const char *chip_name, *fpga_model; u32 reg;//, reg1; struct device_node *np = pdev->dev.of_node; @@ -1868,6 +1952,19 @@ static int openwifi_dev_probe(struct platform_device *pdev) priv = dev->priv; priv->pdev = pdev; + err = of_property_read_string(of_find_node_by_path("/"), "model", &fpga_model); + if(err < 0) { + printk("%s openwifi_dev_probe: WARNING unknown openwifi FPGA model %d\n",sdr_compatible_str, err); + priv->fpga_type = SMALL_FPGA; + } else { + // LARGE FPGAs (i.e. ZCU102, Z7035, ZC706) + if(strstr(fpga_model, "ZCU102") != NULL || strstr(fpga_model, "Z7035") != NULL || strstr(fpga_model, "ZC706") != NULL) + priv->fpga_type = LARGE_FPGA; + // SMALL FPGA: (i.e. ZED, ZC702, Z7020) + else if(strstr(fpga_model, "ZED") != NULL || strstr(fpga_model, "ZC702") != NULL || strstr(fpga_model, "Z7020") != NULL) + priv->fpga_type = SMALL_FPGA; + } + // //-------------find ad9361-phy driver for lo/channel control--------------- priv->actual_rx_lo = 0; tmp_dev = bus_find_device( &spi_bus_type, NULL, "ad9361-phy", custom_match_spi_dev ); @@ -1949,6 +2046,7 @@ static int openwifi_dev_probe(struct platform_device *pdev) // else // printk("%s openwifi_dev_probe: WARNING rfkill radio off failed. tx att read %d %d require %d\n",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT); + priv->last_auto_fpga_lbt_th = 134;//just to avoid uninitialized priv->rssi_correction = 43;//this will be set in real-time by _rf_set_channel() //priv->rf_bw = 20000000; // Signal quality issue! NOT use for now. 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode @@ -2005,10 +2103,9 @@ static int openwifi_dev_probe(struct platform_device *pdev) if (reg == AD9361_RADIO_ON_TX_ATT) { priv->rfkill_off = 1;// 0 off, 1 on printk("%s openwifi_dev_probe: rfkill radio on\n",sdr_compatible_str); - } - else + } else printk("%s openwifi_dev_probe: WARNING rfkill radio on failed. tx att read %d require %d\n",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT); - + memset(priv->drv_rx_reg_val,0,sizeof(priv->drv_rx_reg_val)); memset(priv->drv_tx_reg_val,0,sizeof(priv->drv_tx_reg_val)); memset(priv->drv_xpu_reg_val,0,sizeof(priv->drv_xpu_reg_val)); @@ -2021,7 +2118,7 @@ static int openwifi_dev_probe(struct platform_device *pdev) printk("%s openwifi_dev_probe: ad9361_update_rf_bandwidth %dHz err %d\n",sdr_compatible_str, priv->rf_bw,err); rx_intf_api->hw_init(priv->rx_intf_cfg,8,8); - tx_intf_api->hw_init(priv->tx_intf_cfg,8,8); + tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type); openofdm_tx_api->hw_init(priv->openofdm_tx_cfg); openofdm_rx_api->hw_init(priv->openofdm_rx_cfg); printk("%s openwifi_dev_probe: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\n",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg); @@ -2142,7 +2239,7 @@ static int openwifi_dev_probe(struct platform_device *pdev) } // // //--------------------hook leds (not complete yet)-------------------------------- - // tmp_dev = bus_find_device( &platform_bus_type, NULL, "leds", custom_match_platform_dev ); //leds is the name in devicetree, not "compatiable" field + // tmp_dev = bus_find_device( &platform_bus_type, NULL, "leds", custom_match_platform_dev ); //leds is the name in devicetree, not "compatible" field // if (!tmp_dev) { // printk(KERN_ERR "%s bus_find_device platform_bus_type leds-gpio failed\n",sdr_compatible_str); // err = -ENOMEM; diff --git a/driver/sdr.h b/driver/sdr.h index 925958f..04c0f17 100644 --- a/driver/sdr.h +++ b/driver/sdr.h @@ -1,10 +1,14 @@ -// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be +// Author: Xianjun Jiao, Michael Mehari, Wei Liu +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later #ifndef OPENWIFI_SDR #define OPENWIFI_SDR +#include "pre_def.h" + // -------------------for leds-------------------------------- -struct gpio_led_data { //pleas always align with the leds-gpio.c in linux kernel +struct gpio_led_data { //please always align with the leds-gpio.c in linux kernel struct led_classdev cdev; struct gpio_desc *gpiod; u8 can_sleep; @@ -12,7 +16,7 @@ struct gpio_led_data { //pleas always align with the leds-gpio.c in linux kernel gpio_blink_set_t platform_gpio_blink_set; }; -struct gpio_leds_priv { //pleas always align with the leds-gpio.c in linux kernel +struct gpio_leds_priv { //please always align with the leds-gpio.c in linux kernel int num_leds; struct gpio_led_data leds[]; }; @@ -77,6 +81,7 @@ union u16_byte2 { #define DRV_RX_REG_IDX_EXTRA_FO 2 #define DRV_RX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1) +#define DRV_XPU_REG_IDX_LBT_TH 0 #define DRV_XPU_REG_IDX_GIT_REV (MAX_NUM_DRV_REG-1) // ------end of software reg definition ------------ @@ -88,7 +93,13 @@ union u16_byte2 { #define RING_ROOM_THRESHOLD 4 #define NUM_TX_BD 64 // !!! should align to the fifo size in tx_bit_intf.v + +#ifdef USE_NEW_RX_INTERRUPT +#define NUM_RX_BD 8 +#else #define NUM_RX_BD 16 +#endif + #define TX_BD_BUF_SIZE (8192) #define RX_BD_BUF_SIZE (8192) @@ -304,6 +315,7 @@ struct openwifi_priv { struct ieee80211_vif *vif[MAX_NUM_VIF]; const struct openwifi_rf_ops *rf; + enum openwifi_fpga_type fpga_type; struct cf_axi_dds_state *dds_st; //axi_ad9361 hdl ref design module, dac channel struct axiadc_state *adc_st; //axi_ad9361 hdl ref design module, adc channel @@ -362,6 +374,7 @@ struct openwifi_priv { u32 drv_rx_reg_val[MAX_NUM_DRV_REG]; u32 drv_tx_reg_val[MAX_NUM_DRV_REG]; u32 drv_xpu_reg_val[MAX_NUM_DRV_REG]; + int last_auto_fpga_lbt_th; // u8 num_led; // struct led_classdev *led[MAX_NUM_LED];//zc706 has 4 user leds. please find openwifi_dev_probe to see how we get them. // char led_name[MAX_NUM_LED][OPENWIFI_LED_MAX_NAME_LEN]; diff --git a/driver/side_ch/make_driver.sh b/driver/side_ch/make_driver.sh index fe5a143..77a1d7a 100755 --- a/driver/side_ch/make_driver.sh +++ b/driver/side_ch/make_driver.sh @@ -1,12 +1,17 @@ #!/bin/bash -if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)" + +# Author: Xianjun Jiao, Wei Liu +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -ne 2 ]; then + echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)" exit 1 fi -OPENWIFI_DIR=$1 -XILINX_DIR=$2 -ARCH_OPTION=$3 +OPENWIFI_DIR=$(pwd)/../../ +XILINX_DIR=$1 +ARCH_OPTION=$2 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" @@ -55,4 +60,4 @@ home_dir=$(pwd) cd $OPENWIFI_DIR/driver/side_ch make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE -cd $home_dir \ No newline at end of file +cd $home_dir diff --git a/driver/side_ch/side_ch.c b/driver/side_ch/side_ch.c index 0fb0d2a..98d6160 100644 --- a/driver/side_ch/side_ch.c +++ b/driver/side_ch/side_ch.c @@ -1,7 +1,9 @@ /* * openwifi side channel driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun Jiao + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include diff --git a/driver/side_ch/side_ch.h b/driver/side_ch/side_ch.h index 7d19960..a5fb54b 100644 --- a/driver/side_ch/side_ch.h +++ b/driver/side_ch/side_ch.h @@ -1,4 +1,6 @@ -// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be +// Author: Xianjun Jiao +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later // ---------------------------------------side channel------------------------------- const char *side_ch_compatible_str = "sdr,side_ch"; diff --git a/driver/tx_intf/tx_intf.c b/driver/tx_intf/tx_intf.c index 75bf261..c856d15 100644 --- a/driver/tx_intf/tx_intf.c +++ b/driver/tx_intf/tx_intf.c @@ -1,7 +1,9 @@ /* * axi lite register access driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun Jiao, Michael Mehari, Wei Liu + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include @@ -54,8 +56,8 @@ static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){ return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR); } -static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){ - return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR); +static inline u32 TX_INTF_REG_CSI_FUZZER_read(void){ + return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR); } static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){ @@ -132,8 +134,8 @@ static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){ reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value); } -static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){ - reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value); +static inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){ + reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value); } static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){ @@ -194,7 +196,7 @@ static struct tx_intf_driver_api tx_intf_driver_api_inst; static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst; EXPORT_SYMBOL(tx_intf_api); -static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){ +static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){ int err=0, i; u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0; @@ -208,7 +210,12 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 for (i=0;i<8;i++) tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); - tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue + + if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192 + tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-200); // when only 200 DMA symbol room left in fifo, stop Linux queue + else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096 + tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue + switch(mode) { case TX_INTF_AXIS_LOOP_BACK: @@ -276,7 +283,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg); tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel); - tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2); + tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0); tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl); @@ -331,7 +338,7 @@ static int dev_probe(struct platform_device *pdev) tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read; tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read; tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read; - tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read; + tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read; tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read; tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read; tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read; @@ -351,7 +358,7 @@ static int dev_probe(struct platform_device *pdev) tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write; tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write; tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write; - tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write; + tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write; tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write; tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write; tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write; @@ -371,16 +378,16 @@ static int dev_probe(struct platform_device *pdev) if (IS_ERR(base_addr)) return PTR_ERR(base_addr); - printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); + printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc); printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr); printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) ); printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api); printk("%s dev_probe succeed!\n", tx_intf_compatible_str); - //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8); - //err = hw_init(TX_INTF_BYPASS, 8, 8); - err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma + //err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA); + //err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA); + err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma return err; } diff --git a/driver/xilinx_dma/README.md b/driver/xilinx_dma/README.md index f1c25af..94022bb 100644 --- a/driver/xilinx_dma/README.md +++ b/driver/xilinx_dma/README.md @@ -1,3 +1,9 @@ + +We don't maintain our own (modified) xilinx dma driver anymore! The original xilinx dma driver in the Linux kernel tree can be used. ===============Following are obsolete content================= diff --git a/driver/xilinx_dma/make_xilinx_dma.sh b/driver/xilinx_dma/make_xilinx_dma.sh index 65d097b..22f19ed 100755 --- a/driver/xilinx_dma/make_xilinx_dma.sh +++ b/driver/xilinx_dma/make_xilinx_dma.sh @@ -1,13 +1,18 @@ #!/bin/bash -if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$ARCH(32 or 64)" + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -ne 2 ]; then + echo "You must enter exactly 2 arguments: \$XILINX_DIR \$ARCH(32 or 64)" exit 1 fi WORKDIR=$PWD -OPENWIFI_DIR=$1 -XILINX_DIR=$2 -ARCH_OPTION=$3 +OPENWIFI_DIR=$(pwd)/../../ +XILINX_DIR=$1 +ARCH_OPTION=$2 set -x diff --git a/driver/xilinx_dma/xilinx_dma.c b/driver/xilinx_dma/xilinx_dma.c index 7c88955..a643d7a 100644 --- a/driver/xilinx_dma/xilinx_dma.c +++ b/driver/xilinx_dma/xilinx_dma.c @@ -1,11 +1,9 @@ /* * DMA driver for Xilinx Video DMA Engine - * - * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. - * - * Based on the Freescale DMA driver. - * - * Modified by Xianjun Jiao. putaoshu@msn.com; xianjun.jiao@imec.be + * SPDX-FileCopyrightText: Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved + * Based on the Freescale DMA driver + * Modified by Xianjun Jiao + * SPDX-License-Identifier: GPL-2.0-or-later * * Description: * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP @@ -421,7 +419,7 @@ struct xilinx_dma_config { * @ext_addr: Indicates 64 bit addressing is supported by dma device * @pdev: Platform device structure pointer * @dma_config: DMA config structure - * @axi_clk: DMA Axi4-lite interace clock + * @axi_clk: DMA Axi4-lite interface clock * @tx_clk: DMA mm2s clock * @txs_clk: DMA mm2s stream clock * @rx_clk: DMA s2mm clock diff --git a/driver/xpu/xpu.c b/driver/xpu/xpu.c index d6ce10b..13f9ee8 100644 --- a/driver/xpu/xpu.c +++ b/driver/xpu/xpu.c @@ -1,7 +1,9 @@ /* * axi lite register access driver - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be - */ + * Author: Xianjun Jiao, Michael Mehari, Wei Liu + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ #include #include @@ -140,6 +142,14 @@ static inline u32 XPU_REG_DIFS_ADVANCE_read(void){ return reg_read(XPU_REG_DIFS_ADVANCE_ADDR); } +static inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) { + reg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data); +} + +static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){ + return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR); +} + static inline u32 XPU_REG_TRX_STATUS_read(void){ return reg_read(XPU_REG_TRX_STATUS_ADDR); } @@ -251,13 +261,15 @@ static inline u32 XPU_REG_SLICE_COUNT_END_read(void){ return reg_read(XPU_REG_SLICE_COUNT_END_ADDR); } - static inline void XPU_REG_BB_RF_DELAY_write(u32 value){ reg_write(XPU_REG_BB_RF_DELAY_ADDR, value); } -static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){ - reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value); +static inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){ + reg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value); +} +static inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){ + return reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR); } static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){ @@ -337,7 +349,7 @@ static inline u32 hw_init(enum xpu_mode mode){ // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"! // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz - //xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit + //xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit // xpu_api->XPU_REG_BB_RF_DELAY_write((1<<8)|47); xpu_api->XPU_REG_BB_RF_DELAY_write((10<<8)|40); // extended rf is ongoing for perfect muting. (10<<8)|40 is verified good for zcu102/zed @@ -397,11 +409,13 @@ static inline u32 hw_init(enum xpu_mode mode){ rssi_half_db_th = 87<<1; // -62dBm xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it + xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals + //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); xpu_api->XPU_REG_CSMA_DEBUG_write(0); - xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA - // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority + // xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx + // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately @@ -472,6 +486,9 @@ static int dev_probe(struct platform_device *pdev) xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write; xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read; + xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write; + xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read; + xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; @@ -508,7 +525,9 @@ static int dev_probe(struct platform_device *pdev) xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read; xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write; - xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write; + + xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write; + xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read; xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write; diff --git a/kernel_boot/72113-files.zip b/kernel_boot/72113-files.zip new file mode 100644 index 0000000..d039420 Binary files /dev/null and b/kernel_boot/72113-files.zip differ diff --git a/kernel_boot/boards/antsdr/devicetree.dtb b/kernel_boot/boards/antsdr/devicetree.dtb new file mode 100644 index 0000000..de44f31 Binary files /dev/null and b/kernel_boot/boards/antsdr/devicetree.dtb differ diff --git a/kernel_boot/boards/antsdr/devicetree.dts b/kernel_boot/boards/antsdr/devicetree.dts new file mode 100644 index 0000000..9e9d88a --- /dev/null +++ b/kernel_boot/boards/antsdr/devicetree.dts @@ -0,0 +1,883 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "xlnx,zynq-7000"; + interrupt-parent = <0x1>; + model = "MicroPhase ANTSDR-E310 (Z7020/AD9361 Z7020/AD9363)"; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x0>; + clocks = <0x2 0x3>; + clock-latency = <0x3e8>; + cpu0-supply = <0x3>; + operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x1>; + clocks = <0x2 0x3>; + }; + }; + + fpga-full { + compatible = "fpga-region"; + fpga-mgr = <0x4>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + + pmu@f8891000 { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; + interrupt-parent = <0x1>; + reg = <0xf8891000 0x1000 0xf8893000 0x1000>; + }; + + fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <0xf4240>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <0x3>; + phandle = <0x3>; + }; + + amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + interrupt-parent = <0x1>; + ranges; + + adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0x0 0x7 0x4>; + interrupt-parent = <0x1>; + clocks = <0x2 0xc>; + }; + + can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x2 0x13 0x2 0x24>; + clock-names = "can_clk", "pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0x0 0x1c 0x4>; + interrupt-parent = <0x1>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x2 0x14 0x2 0x25>; + clock-names = "can_clk", "pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0x0 0x33 0x4>; + interrupt-parent = <0x1>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <0x2>; + clocks = <0x2 0x2a>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x14 0x4>; + reg = <0xe000a000 0x1000>; + linux,phandle = <0x6>; + phandle = <0x6>; + }; + + i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x2 0x26>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x19 0x4>; + reg = <0xe0004000 0x1000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x2 0x27>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x30 0x4>; + reg = <0xe0005000 0x1000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x3>; + interrupt-controller; + reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; + linux,phandle = <0x1>; + phandle = <0x1>; + }; + + cache-controller@f8f02000 { + compatible = "arm,pl310-cache"; + reg = <0xf8f02000 0x1000>; + interrupts = <0x0 0x2 0x4>; + arm,data-latency = <0x3 0x2 0x2>; + arm,tag-latency = <0x2 0x2 0x2>; + cache-unified; + cache-level = <0x2>; + }; + + memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; + + ocmc@f800c000 { + compatible = "xlnx,zynq-ocmc-1.0"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x3 0x4>; + reg = <0xf800c000 0x1000>; + }; + + serial@e0000000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + status = "disabled"; + clocks = <0x2 0x17 0x2 0x28>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0x0 0x1b 0x4>; + }; + + serial@e0001000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + status = "okay"; + clocks = <0x2 0x18 0x2 0x29>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0001000 0x1000>; + interrupts = <0x0 0x32 0x4>; + }; + + spi@e0006000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0006000 0x1000>; + status = "okay"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x1a 0x4>; + clocks = <0x2 0x19 0x2 0x22>; + clock-names = "ref_clk", "pclk"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ad9361-phy@0 { + #address-cells = <0x1>; + #size-cells = <0x0>; + #clock-cells = <0x1>; + compatible = "adi,ad9361"; + reg = <0x0>; + spi-cpha; + spi-max-frequency = <0x989680>; + clocks = <0x5 0x0>; + clock-names = "ad9364_ext_refclk"; + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + adi,digital-interface-tune-skip-mode = <0x0>; + adi,pp-tx-swap-enable; + adi,pp-rx-swap-enable; + adi,rx-frame-pulse-mode-enable; + adi,lvds-mode-enable; + adi,lvds-bias-mV = <0x96>; + adi,lvds-rx-onchip-termination-enable; + adi,rx-data-delay = <0x4>; + adi,tx-fb-clock-delay = <0x7>; + adi,xo-disable-use-ext-refclk-enable; + adi,2rx-2tx-mode-enable; + adi,frequency-division-duplex-mode-enable; + adi,rx-rf-port-input-select = <0x0>; + adi,tx-rf-port-input-select = <0x0>; + adi,tx-attenuation-mdB = <0x2710>; + adi,tx-lo-powerdown-managed-enable; + adi,rf-rx-bandwidth-hz = <0x112a880>; + adi,rf-tx-bandwidth-hz = <0x112a880>; + adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; + adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; + adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,gc-rx1-mode = <0x2>; + adi,gc-rx2-mode = <0x2>; + adi,gc-adc-ovr-sample-size = <0x4>; + adi,gc-adc-small-overload-thresh = <0x2f>; + adi,gc-adc-large-overload-thresh = <0x3a>; + adi,gc-lmt-overload-high-thresh = <0x320>; + adi,gc-lmt-overload-low-thresh = <0x2c0>; + adi,gc-dec-pow-measurement-duration = <0x2000>; + adi,gc-low-power-thresh = <0x18>; + adi,mgc-inc-gain-step = <0x2>; + adi,mgc-dec-gain-step = <0x2>; + adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; + adi,agc-attack-delay-extra-margin-us = <0x1>; + adi,agc-outer-thresh-high = <0x5>; + adi,agc-outer-thresh-high-dec-steps = <0x2>; + adi,agc-inner-thresh-high = <0xa>; + adi,agc-inner-thresh-high-dec-steps = <0x1>; + adi,agc-inner-thresh-low = <0xc>; + adi,agc-inner-thresh-low-inc-steps = <0x1>; + adi,agc-outer-thresh-low = <0x12>; + adi,agc-outer-thresh-low-inc-steps = <0x2>; + adi,agc-adc-small-overload-exceed-counter = <0xa>; + adi,agc-adc-large-overload-exceed-counter = <0xa>; + adi,agc-adc-large-overload-inc-steps = <0x2>; + adi,agc-lmt-overload-large-exceed-counter = <0xa>; + adi,agc-lmt-overload-small-exceed-counter = <0xa>; + adi,agc-lmt-overload-large-inc-steps = <0x2>; + adi,agc-gain-update-interval-us = <0x3e8>; + adi,fagc-dec-pow-measurement-duration = <0x40>; + adi,fagc-lp-thresh-increment-steps = <0x1>; + adi,fagc-lp-thresh-increment-time = <0x5>; + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; + adi,fagc-final-overrange-count = <0x3>; + adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; + adi,fagc-lmt-final-settling-steps = <0x1>; + adi,fagc-lock-level = <0xa>; + adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; + adi,fagc-lock-level-lmt-gain-increase-enable; + adi,fagc-lpf-final-settling-steps = <0x1>; + adi,fagc-optimized-gain-offset = <0x5>; + adi,fagc-power-measurement-duration-in-state5 = <0x40>; + adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; + adi,fagc-rst-gla-large-adc-overload-enable; + adi,fagc-rst-gla-large-lmt-overload-enable; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; + adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; + adi,fagc-state-wait-time-ns = <0x104>; + adi,fagc-use-last-lock-level-for-set-gain-enable; + adi,rssi-restart-mode = <0x3>; + adi,rssi-delay = <0x1>; + adi,rssi-wait = <0x1>; + adi,rssi-duration = <0x3e8>; + adi,ctrl-outs-index = <0x0>; + adi,ctrl-outs-enable-mask = <0xff>; + adi,temp-sense-measurement-interval-ms = <0x3e8>; + adi,temp-sense-offset-signed = <0xce>; + adi,temp-sense-periodic-measurement-enable; + adi,aux-dac-manual-mode-enable; + adi,aux-dac1-default-value-mV = <0x0>; + adi,aux-dac1-rx-delay-us = <0x0>; + adi,aux-dac1-tx-delay-us = <0x0>; + adi,aux-dac2-default-value-mV = <0x0>; + adi,aux-dac2-rx-delay-us = <0x0>; + adi,aux-dac2-tx-delay-us = <0x0>; + en_agc-gpios = <0x6 0x62 0x0>; + sync-gpios = <0x6 0x63 0x0>; + reset-gpios = <0x6 0x64 0x0>; + enable-gpios = <0x6 0x65 0x0>; + txnrx-gpios = <0x6 0x66 0x0>; + linux,phandle = <0xb>; + phandle = <0xb>; + }; + }; + + spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0007000 0x1000>; + status = "disabled"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x31 0x4>; + clocks = <0x2 0x1a 0x2 0x23>; + clock-names = "ref_clk", "pclk"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + spi@e000d000 { + clock-names = "ref_clk", "pclk"; + clocks = <0x2 0xa 0x2 0x2b>; + compatible = "xlnx,zynq-qspi-1.0"; + status = "okay"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x13 0x4>; + reg = <0xe000d000 0x1000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + is-dual = <0x0>; + num-cs = <0x1>; + + ps7-qspi@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + spi-tx-bus-width = <0x1>; + spi-rx-bus-width = <0x4>; + compatible = "n25q256a", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <0x2faf080>; + + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0xe0000>; + }; + + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0xe0000 0x20000>; + }; + + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0xce0000>; + }; + + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0x1300000 0xd00000>; + }; + }; + }; + + memory-controller@e000e000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + status = "disabled"; + clock-names = "memclk", "aclk"; + clocks = <0x2 0xb 0x2 0x2c>; + compatible = "arm,pl353-smc-r2p1"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x12 0x4>; + ranges; + reg = <0xe000e000 0x1000>; + + flash@e1000000 { + status = "disabled"; + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + flash@e2000000 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <0xe2000000 0x2000000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + }; + + ethernet@e000b000 { + compatible = "cdns,zynq-gem", "cdns,gem"; + reg = <0xe000b000 0x1000>; + status = "okay"; + interrupts = <0x0 0x16 0x4>; + clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <0x1>; + #size-cells = <0x0>; + phy-handle = <0x7>; + phy-mode = "rgmii-id"; + + phy@0 { + device_type = "ethernet-phy"; + reg = <0x0>; + marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; + linux,phandle = <0x7>; + phandle = <0x7>; + }; + }; + + ethernet@e000c000 { + compatible = "cdns,zynq-gem", "cdns,gem"; + reg = <0xe000c000 0x1000>; + status = "disabled"; + interrupts = <0x0 0x2d 0x4>; + clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + mmc@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "okay"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <0x2 0x15 0x2 0x20>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x18 0x4>; + reg = <0xe0100000 0x1000>; + disable-wp; + }; + + mmc@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <0x2 0x16 0x2 0x21>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x2f 0x4>; + reg = <0xe0101000 0x1000>; + }; + + slcr@f8000000 { + u-boot,dm-pre-reloc; + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; + reg = <0xf8000000 0x1000>; + ranges; + linux,phandle = <0x8>; + phandle = <0x8>; + + clkc@100 { + u-boot,dm-pre-reloc; + #clock-cells = <0x1>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0xf>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + ps-clk-frequency = <0x1fca055>; + linux,phandle = <0x2>; + phandle = <0x2>; + }; + + rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <0x1>; + syscon = <0x8>; + }; + + pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <0x8>; + }; + }; + + dmac@f8003000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <0x1>; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; + interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; + #dma-cells = <0x1>; + #dma-channels = <0x8>; + #dma-requests = <0x4>; + clocks = <0x2 0x1b>; + clock-names = "apb_pclk"; + }; + + devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x8 0x4>; + reg = <0xf8007000 0x100>; + clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + syscon = <0x8>; + linux,phandle = <0x4>; + phandle = <0x4>; + }; + + efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; + }; + + timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <0x1 0xb 0x301>; + interrupt-parent = <0x1>; + clocks = <0x2 0x4>; + }; + + timer@f8001000 { + interrupt-parent = <0x1>; + interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; + compatible = "cdns,ttc"; + clocks = <0x2 0x6>; + reg = <0xf8001000 0x1000>; + }; + + timer@f8002000 { + interrupt-parent = <0x1>; + interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; + compatible = "cdns,ttc"; + clocks = <0x2 0x6>; + reg = <0xf8002000 0x1000>; + }; + + timer@f8f00600 { + interrupt-parent = <0x1>; + interrupts = <0x1 0xd 0x301>; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clocks = <0x2 0x4>; + }; + + usb@e0002000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "okay"; + clocks = <0x2 0x1c>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x15 0x4>; + reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; + dr_mode = "host"; + xlnx,phy-reset-gpio = <0x6 0x7 0x0>; + }; + + usb@e0003000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "disabled"; + clocks = <0x2 0x1d>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x2c 0x4>; + reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + }; + + watchdog@f8005000 { + clocks = <0x2 0x2d>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x9 0x1>; + reg = <0xf8005000 0x1000>; + timeout-sec = <0xa>; + }; + }; + + aliases { + ethernet0 = "/amba/ethernet@e000b000"; + serial0 = "/amba/serial@e0001000"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + linux,stdout-path = "/amba@0/uart@E0001000"; + }; + + clocks { + + clock@0 { + #clock-cells = <0x0>; + compatible = "adjustable-clock"; + clock-frequency = <0x2625a00>; + clock-accuracy = <0x30d40>; + clock-output-names = "ad9364_ext_refclk"; + linux,phandle = <0x5>; + phandle = <0x5>; + }; + + clock@1 { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "24MHz"; + linux,phandle = <0x9>; + phandle = <0x9>; + }; + }; + + usb-ulpi-gpio-gate@0 { + compatible = "gpio-gate-clock"; + clocks = <0x9>; + #clock-cells = <0x0>; + enable-gpios = <0x6 0x9 0x1>; + }; + + fpga-axi@0 { + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + i2c@41600000 { + compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; + reg = <0x41600000 0x10000>; + interrupt-parent = <0x1>; + interrupts = <0x0 0x3a 0x4>; + clocks = <0x2 0xf>; + clock-names = "pclk"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ad7291@20 { + compatible = "adi,ad7291"; + reg = <0x20>; + }; + + ad7291-bob@2C { + compatible = "adi,ad7291"; + reg = <0x2c>; + }; + + eeprom@50 { + compatible = "at24,24c32"; + reg = <0x50>; + }; + }; + + dma@7c400000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c400000 0x10000>; + #dma-cells = <0x1>; + interrupts = <0x0 0x39 0x0>; + clocks = <0x2 0x10>; + linux,phandle = <0xa>; + phandle = <0xa>; + + adi,channels { + #size-cells = <0x0>; + #address-cells = <0x1>; + + dma-channel@0 { + reg = <0x0>; + adi,source-bus-width = <0x40>; + adi,source-bus-type = <0x2>; + adi,destination-bus-width = <0x40>; + adi,destination-bus-type = <0x0>; + }; + }; + }; + + dma@7c420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c420000 0x10000>; + #dma-cells = <0x1>; + interrupts = <0x0 0x38 0x0>; + clocks = <0x2 0x10>; + linux,phandle = <0xc>; + phandle = <0xc>; + + adi,channels { + #size-cells = <0x0>; + #address-cells = <0x1>; + + dma-channel@0 { + reg = <0x0>; + adi,source-bus-width = <0x40>; + adi,source-bus-type = <0x0>; + adi,destination-bus-width = <0x40>; + adi,destination-bus-type = <0x2>; + }; + }; + }; + + sdr: sdr { + compatible ="sdr,sdr"; + dmas = <&rx_dma 1 + &tx_dma 0>; + dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; + interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; + interrupt-parent = <1>; + interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; + } ; + + axidmatest_1: axidmatest@1 { + compatible ="xlnx,axi-dma-test-1.00.a"; + dmas = <&rx_dma 0 + &rx_dma 1>; + dma-names = "axidma0", "axidma1"; + } ; + + tx_dma: dma@80400000 { + #dma-cells = <1>; + clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + interrupt-names = "mm2s_introut", "s2mm_introut"; + interrupt-parent = <1>; + interrupts = <0 35 4 0 36 4>; + reg = <0x80400000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg ; + xlnx,sg-length-width = <0xe>; + dma-channel@80400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x1>; + interrupts = <0 35 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x0>; + }; + dma-channel@80400030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x1>; + interrupts = <0 36 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x0>; + }; + }; + + rx_dma: dma@80410000 { + #dma-cells = <1>; + clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + //dma-coherent ; + interrupt-names = "mm2s_introut", "s2mm_introut"; + interrupt-parent = <1>; + interrupts = <0 31 4 0 32 4>; + reg = <0x80410000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg ; + xlnx,sg-length-width = <0xe>; + dma-channel@80410000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x1>; + interrupts = <0 31 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x1>; + }; + dma-channel@80410030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x1>; + interrupts = <0 32 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x1>; + }; + }; + + tx_intf_0: tx_intf@83c00000 { + clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; + compatible = "sdr,tx_intf"; + interrupt-names = "tx_itrpt"; + interrupt-parent = <1>; + interrupts = <0 34 1>; + reg = <0x83c00000 0x10000>; + xlnx,s00-axi-addr-width = <0x7>; + xlnx,s00-axi-data-width = <0x20>; + }; + + rx_intf_0: rx_intf@83c20000 { + clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; + compatible = "sdr,rx_intf"; + interrupt-names = "not_valid_anymore", "rx_pkt_intr"; + interrupt-parent = <1>; + interrupts = <0 29 1 0 30 1>; + reg = <0x83c20000 0x10000>; + xlnx,s00-axi-addr-width = <0x7>; + xlnx,s00-axi-data-width = <0x20>; + }; + + openofdm_tx_0: openofdm_tx@83c10000 { + clock-names = "clk"; + clocks = <0x2 0x11>; + compatible = "sdr,openofdm_tx"; + reg = <0x83c10000 0x10000>; + }; + + openofdm_rx_0: openofdm_rx@83c30000 { + clock-names = "clk"; + clocks = <0x2 0x11>; + compatible = "sdr,openofdm_rx"; + reg = <0x83c30000 0x10000>; + }; + + xpu_0: xpu@83c40000 { + clock-names = "s00_axi_aclk"; + clocks = <0x2 0x11>; + compatible = "sdr,xpu"; + reg = <0x83c40000 0x10000>; + }; + + side_ch_0: side_ch@83c50000 { + clock-names = "s00_axi_aclk"; + clocks = <0x2 0x11>; + compatible = "sdr,side_ch"; + reg = <0x83c50000 0x10000>; + dmas = <&rx_dma 0 + &tx_dma 1>; + dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; + }; + + cf-ad9361-lpc@79020000 { + compatible = "adi,axi-ad9361-6.00.a"; + reg = <0x79020000 0x6000>; + dmas = <0xa 0x0>; + dma-names = "rx"; + spibus-connected = <0xb>; + }; + + cf-ad9361-dds-core-lpc@79024000 { + compatible = "adi,axi-ad9361-dds-6.00.a"; + reg = <0x79024000 0x1000>; + clocks = <0xb 0xd>; + clock-names = "sampl_clk"; + dmas = <0xc 0x0>; + dma-names = "tx"; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-axi4lite-v1.00"; + reg = <0x43c00000 0xffff>; + }; + + /*axi-sysid-0@45000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x45000000 0x10000>; + };*/ + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "led0:green"; + gpios = <0x6 0xF 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <0x1>; + #size-cells = <0x0>; + autorepeat; + + sw1 { + label = "SW1"; + linux,input-type = <0x5>; + linux,code = <0x3>; + gpios = <0x6 0xE 0x0>; + }; + }; +}; diff --git a/kernel_boot/boards/antsdr/notes.md b/kernel_boot/boards/antsdr/notes.md new file mode 100644 index 0000000..3443c59 --- /dev/null +++ b/kernel_boot/boards/antsdr/notes.md @@ -0,0 +1,15 @@ +# antsdr for openwifi-hw + +## Introduction +[ANTSDR](https://github.com/MicroPhase/antsdr-fw) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi. + + + + +## Work to be done +The antsdr has RF switch in the front-end, for now, the RF switch is fixed at a higer range, which will isolation the frequency below 3GHz and pass the frequency at 3GHz~6GHz. +For future work, it can add the rf swicth control in the devicetree, and this will change the rf switch with the frequency change. diff --git a/kernel_boot/boards/antsdr/u-boot.elf b/kernel_boot/boards/antsdr/u-boot.elf new file mode 100755 index 0000000..760aed1 Binary files /dev/null and b/kernel_boot/boards/antsdr/u-boot.elf differ diff --git a/kernel_boot/build_boot_bin.sh b/kernel_boot/build_boot_bin.sh index 668d61c..b25826a 100755 --- a/kernel_boot/build_boot_bin.sh +++ b/kernel_boot/build_boot_bin.sh @@ -1,24 +1,29 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later # https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_2014r2 -if [ "$#" -ne 1 ]; then - echo "You must enter the \$BOARD_NAME as argument" - echo "Like: adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" +if [ "$#" -ne 2 ]; then + echo "You must enter the \$OPENWIFI_HW_DIR \$BOARD_NAME as argument" + echo "BOARD_NAME Like: antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" exit 1 fi -BOARD_NAME=$1 -if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then +OPENWIFI_HW_DIR=$1 +BOARD_NAME=$2 + +if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else echo "\$BOARD_NAME is found!" fi - set -ex -HDF_FILE=../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf +HDF_FILE=$OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf UBOOT_FILE=./boards/$BOARD_NAME/u-boot.elf BUILD_DIR=./boards/$BOARD_NAME/build_boot_bin OUTPUT_DIR=./boards/$BOARD_NAME/output_boot_bin diff --git a/kernel_boot/build_zynqmp_boot_bin.sh b/kernel_boot/build_zynqmp_boot_bin.sh index 72af9c6..abe3448 100755 --- a/kernel_boot/build_zynqmp_boot_bin.sh +++ b/kernel_boot/build_zynqmp_boot_bin.sh @@ -1,4 +1,8 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later # https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp set -ex @@ -97,7 +101,8 @@ tool_version=${tool_version%\ (64-bit)*} # (https://www.xilinx.com/support/answers/71961.html) if [ $tool_version == "v2018.3" ];then ( - wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR +# wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR + cp -P 72113-files.zip $BUILD_DIR unzip $BUILD_DIR/72113-files.zip -d $BUILD_DIR ) fi diff --git a/openwifi-arch.jpg.license b/openwifi-arch.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/openwifi-arch.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/openwifi-hw b/openwifi-hw deleted file mode 160000 index b3bd6e2..0000000 --- a/openwifi-hw +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b3bd6e298feaa75f7be688f5fe2ded842351fca1 diff --git a/user_space/boot_bin_gen.sh b/user_space/boot_bin_gen.sh index d15dead..a566329 100755 --- a/user_space/boot_bin_gen.sh +++ b/user_space/boot_bin_gen.sh @@ -1,13 +1,23 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME" + echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME" exit 1 fi -OPENWIFI_DIR=$1 +OPENWIFI_HW_DIR=$1 XILINX_DIR=$2 BOARD_NAME=$3 +OPENWIFI_DIR=$(pwd)/../ + +echo OPENWIFI_DIR $OPENWIFI_DIR +echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR + if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" else @@ -22,13 +32,20 @@ else exit 1 fi -if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then +if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else echo "\$BOARD_NAME is found!" fi +if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then + echo "\$OPENWIFI_HW_DIR is found!" +else + echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + exit 1 +fi + home_dir=$(pwd) set -ex @@ -38,6 +55,6 @@ source $XILINX_DIR/SDK/2018.3/settings64.sh cd $OPENWIFI_DIR/kernel_boot -./build_boot_bin.sh $BOARD_NAME +./build_boot_bin.sh $OPENWIFI_HW_DIR $BOARD_NAME cd $home_dir diff --git a/user_space/boot_bin_gen_zynqmp.sh b/user_space/boot_bin_gen_zynqmp.sh index 0c33ef8..673bdc5 100755 --- a/user_space/boot_bin_gen_zynqmp.sh +++ b/user_space/boot_bin_gen_zynqmp.sh @@ -1,13 +1,23 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME" + echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME" exit 1 fi -OPENWIFI_DIR=$1 +OPENWIFI_HW_DIR=$1 XILINX_DIR=$2 BOARD_NAME=$3 +OPENWIFI_DIR=$(pwd)/../ + +echo OPENWIFI_DIR $OPENWIFI_DIR +echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR + if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" else @@ -29,6 +39,13 @@ else echo "\$BOARD_NAME is found!" fi +if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then + echo "\$OPENWIFI_HW_DIR is found!" +else + echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + exit 1 +fi + home_dir=$(pwd) set -ex @@ -38,8 +55,8 @@ source $XILINX_DIR/SDK/2018.3/settings64.sh cd $OPENWIFI_DIR/kernel_boot -./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf -# ./build_zynqmp_boot_bin.sh ../openwifi-hw/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf download +./build_zynqmp_boot_bin.sh $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf + rm -rf build_boot_bin rm -rf boards/$BOARD_NAME/output_boot_bin mv output_boot_bin boards/$BOARD_NAME/ diff --git a/user_space/build_wpa_supplicant_wo11b.sh b/user_space/build_wpa_supplicant_wo11b.sh index d2829cd..da6acea 100755 --- a/user_space/build_wpa_supplicant_wo11b.sh +++ b/user_space/build_wpa_supplicant_wo11b.sh @@ -1,10 +1,15 @@ #!/bin/bash -if [ "$#" -ne 1 ]; then - echo "You must enter exactly 1 arguments: \$OPENWIFI_DIR" - exit 1 -fi -OPENWIFI_DIR=$1 +# Author: Michael Mehari +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +# if [ "$#" -ne 1 ]; then +# echo "You must enter exactly 1 arguments: \$OPENWIFI_DIR" +# exit 1 +# fi + +OPENWIFI_DIR=$(pwd)/../ set -x diff --git a/user_space/csi_fuzzer.sh b/user_space/csi_fuzzer.sh new file mode 100755 index 0000000..90d8aa1 --- /dev/null +++ b/user_space/csi_fuzzer.sh @@ -0,0 +1,61 @@ + +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2021 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -lt 4 ]; then + echo "You must enter 4 arguments: c1_rot90_en c1_raw(-64 to 63) c2_rot90_en c2_raw(-64 to 63)" + exit 1 +fi + +c1_rot90_en=$1 +c1_raw=$2 +c2_rot90_en=$3 +c2_raw=$4 + +if (($c1_rot90_en != 0)) && (($c1_rot90_en != 1)); then + echo "c1_rot90_en must be 0 or 1!" + exit 1 +fi + +if (($c1_raw < -64)) || (($c1_raw > 63)); then + echo "c1_raw must be -64 to 63!" + exit 1 +fi + +if (($c2_rot90_en != 0)) && (($c2_rot90_en != 1)); then + echo "c2_rot90_en must be 0 or 1!" + exit 1 +fi + +if (($c2_raw < -64)) || (($c2_raw > 63)); then + echo "c2_raw must be -64 to 63!" + exit 1 +fi + +if (($c1_raw < 0)); then + unsigned_c1=$(expr 128 + $c1_raw) +# echo $unsigned_c1 +else + unsigned_c1=$c1_raw +fi + +if (($c2_raw < 0)); then + unsigned_c2=$(expr 128 + $c2_raw) +# echo $unsigned_c2 +else + unsigned_c2=$c2_raw +fi + +# echo $c1_rot90_en +# echo $unsigned_c1 +# echo $c2_rot90_en +# echo $unsigned_c2 + +unsigned_dec_combined=$(($unsigned_c1 + 512 * $c1_rot90_en + 1024 * $unsigned_c2 + 524288 * $c2_rot90_en)) +# echo $unsigned_dec_combined + +echo "./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined" +./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined diff --git a/user_space/csi_fuzzer_scan.sh b/user_space/csi_fuzzer_scan.sh new file mode 100755 index 0000000..28b0260 --- /dev/null +++ b/user_space/csi_fuzzer_scan.sh @@ -0,0 +1,110 @@ +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2021 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -lt 1 ]; then + echo "You must enter 1 arguments: 1, 2, 3 or 4. For scan c1, c2, c2&c1 or c1&c2," + exit 1 +fi + +SCAN_OPTION=$1 + +if (($SCAN_OPTION == 1)); then + echo "Scan tap1:" + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 $i 0 0 + sleep 0.01 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 1 $i 0 0 + sleep 0.01 + done + done + exit 1 +fi + +if (($SCAN_OPTION == 2)); then + echo "Scan tap2:" + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 0 0 $i + sleep 0.01 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 0 1 $i + sleep 0.01 + done + done + exit 1 +fi + +if (($SCAN_OPTION == 3)); then + echo "Scan tap1 after tap2:" + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 $j 0 $i + # sleep 0.1 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 $j 1 $i + # sleep 0.1 + done + done + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 1 $j 0 $i + # sleep 0.1 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 1 $j 1 $i + # sleep 0.1 + done + done + exit 1 +fi + +if (($SCAN_OPTION == 4)); then + echo "Scan tap2 after tap1:" + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 $i 0 $j + # sleep 0.1 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 1 $i 0 $j + # sleep 0.1 + done + done + for j in {-64..63}; + do + for i in {-64..63}; + do + ./csi_fuzzer.sh 0 $i 1 $j + # sleep 0.1 + done + for i in {-64..63}; + do + ./csi_fuzzer.sh 1 $i 1 $j + # sleep 0.1 + done + done + exit 1 +fi diff --git a/user_space/fosdem-11ag.sh b/user_space/fosdem-11ag.sh index 010cb0e..a001fd9 100755 --- a/user_space/fosdem-11ag.sh +++ b/user_space/fosdem-11ag.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + killall hostapd killall webfsd diff --git a/user_space/fosdem.sh b/user_space/fosdem.sh index e7656ab..8d86291 100755 --- a/user_space/fosdem.sh +++ b/user_space/fosdem.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + killall hostapd killall webfsd diff --git a/user_space/get_fpga.sh b/user_space/get_fpga.sh deleted file mode 100755 index 9a698ed..0000000 --- a/user_space/get_fpga.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/bash - -if [ "$#" -ne 1 ]; then - echo "You must enter the \$OPENWIFI_DIR (the openwifi root directory) as argument" - exit 1 -fi -OPENWIFI_DIR=$1 - - -if [ -f "$OPENWIFI_DIR/LICENSE" ]; then - echo "\$OPENWIFI_DIR is found!" -else - echo "\$OPENWIFI_DIR is not correct. Please check!" - exit 1 -fi - -home_dir=$(pwd) - -set -ex - -cd $OPENWIFI_DIR/ -git submodule init openwifi-hw -git submodule update openwifi-hw -cd openwifi-hw -git checkout master -git pull - -cd $home_dir diff --git a/user_space/inject_80211/analyze_80211.c b/user_space/inject_80211/analyze_80211.c index d11f065..a6d1dbd 100644 --- a/user_space/inject_80211/analyze_80211.c +++ b/user_space/inject_80211/analyze_80211.c @@ -1,5 +1,7 @@ -// (c)2020 Michael Tetemke Mehari +// Author: Michael Mehari +// SPDX-FileCopyrightText: 2020 UGent +// SPDX-License-Identifier: GPL-2.0-or-later /* * This program is free software; you can redistribute it and/or modify diff --git a/user_space/inject_80211/inject_80211.c b/user_space/inject_80211/inject_80211.c index d022f77..7609e36 100644 --- a/user_space/inject_80211/inject_80211.c +++ b/user_space/inject_80211/inject_80211.c @@ -1,5 +1,7 @@ -// (c)2007 Andy Green -// (r)2020 Michael Tetemke Mehari +// Modified by: Michael Mehari +// SPDX-FileCopyrightText: 2020 UGent +// SPDX-FileCopyrightText: 2007 Andy Green +// SPDX-License-Identifier: GPL-2.0-or-later /* * This program is free software; you can redistribute it and/or modify @@ -58,11 +60,11 @@ static const u8 u8aRadiotapHeader[] = /* IEEE80211 header */ static const u8 ieee_hdr[] = { - 0x08, 0x01, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, - 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, - 0x10, 0x86, + 0x08, 0x01, 0x00, 0x00, // FC 0x0801. 0--subtype; 8--type&version; 01--toDS1 fromDS0 (data packet to DS) + 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP + 0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Source address (STA) + 0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Destination address (another STA under the same AP) + 0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number }; // Generate random string @@ -117,7 +119,7 @@ void usage(void) int main(int argc, char *argv[]) { u8 buffer[1536]; - char szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1536], hw_mode = 'n'; + char szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1484], hw_mode = 'n'; int i, nLinkEncap = 0, r, rate_index = 0, sgi_flag = 0, num_packets = 10, payload_size = 64, packet_size, nDelay = 100000; pcap_t *ppcap = NULL; diff --git a/user_space/inject_80211/inject_80211.h b/user_space/inject_80211/inject_80211.h index 175e7d5..8eb711b 100644 --- a/user_space/inject_80211/inject_80211.h +++ b/user_space/inject_80211/inject_80211.h @@ -1,3 +1,9 @@ +/* + * Author: Michael Mehari + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ + #include #include #include diff --git a/user_space/inject_80211/inject_80211.sh b/user_space/inject_80211/inject_80211.sh index 8edb789..6d16c59 100755 --- a/user_space/inject_80211/inject_80211.sh +++ b/user_space/inject_80211/inject_80211.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Michael Mehari +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + HW_MODE='n' COUNT=100 DELAY=1000 diff --git a/user_space/inject_80211/radiotap.c b/user_space/inject_80211/radiotap.c index 2d9d320..179dc15 100644 --- a/user_space/inject_80211/radiotap.c +++ b/user_space/inject_80211/radiotap.c @@ -107,7 +107,7 @@ int ieee80211_radiotap_iterator_init( * present fields. @this_arg can be changed by the caller (eg, * incremented to move inside a compound argument like * IEEE80211_RADIOTAP_CHANNEL). The args pointed to are in - * little-endian format whatever the endianess of your CPU. + * little-endian format whatever the endianness of your CPU. */ int ieee80211_radiotap_iterator_next( diff --git a/user_space/link_perf_test.sh b/user_space/link_perf_test.sh index a950ef1..d6a9644 100755 --- a/user_space/link_perf_test.sh +++ b/user_space/link_perf_test.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Michael Mehari +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + PL_MIN=100 PL_INC=100 PL_MAX=1500 diff --git a/user_space/monitor_ch.sh b/user_space/monitor_ch.sh index 7c86663..d485898 100755 --- a/user_space/monitor_ch.sh +++ b/user_space/monitor_ch.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ $# -ne 2 ] then echo "Please input NIC_name ch_number as input parameter!" diff --git a/user_space/nic_back_to_normal.sh b/user_space/nic_back_to_normal.sh index 13b9caf..38c7dd5 100755 --- a/user_space/nic_back_to_normal.sh +++ b/user_space/nic_back_to_normal.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ $# -ne 1 ] then echo "Please input NIC name as input parameter!" diff --git a/user_space/post_config.sh b/user_space/post_config.sh index 0a9423f..0212827 100755 --- a/user_space/post_config.sh +++ b/user_space/post_config.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + set -ex MACHINE_TYPE=`uname -m` @@ -47,6 +51,16 @@ sudo apt-get -y install nano sudo apt-get -y install tcpdump sudo apt-get -y install webfs sudo apt-get -y install iperf +sudo apt-get -y install libpcap-dev -# change the password to openwifi +# change the root password to openwifi +cat /etc/passwd +sed -i 's/root:x:0:0:root:\/root:\/bin\/bash/root::0:0:root:\/root:\/bin\/bash/' /etc/passwd +sync +sleep 1 +cat /etc/passwd echo -e "openwifi\nopenwifi" | passwd +sync +sleep 1 +cat /etc/passwd + diff --git a/user_space/prepare_kernel.sh b/user_space/prepare_kernel.sh index defe2da..da460d7 100755 --- a/user_space/prepare_kernel.sh +++ b/user_space/prepare_kernel.sh @@ -1,13 +1,18 @@ #!/bin/bash -if [ "$#" -lt 3 ]; then - echo "You must enter at least 3 arguments: \$OPENWIFI_DIR \$XILINX_DIR ARCH_BIT(32 or 64)" + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +if [ "$#" -lt 2 ]; then + echo "You must enter at least 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)" exit 1 fi -OPENWIFI_DIR=$1 -XILINX_DIR=$2 -ARCH_OPTION=$3 +OPENWIFI_DIR=$(pwd)/../ +XILINX_DIR=$1 +ARCH_OPTION=$2 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" @@ -54,22 +59,24 @@ git submodule update $LINUX_KERNEL_SRC_DIR_NAME cd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME git checkout 2019_R1 git pull origin 2019_R1 -# git reset --hard 4fea7c5 -cp $OPENWIFI_DIR/driver/xilinx_dma/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/dma/xilinx/xilinx_dma.c +git reset --hard +# git reset --hard 4e81f0927cfb2fada92fc762dbd65d002848405a cp $LINUX_KERNEL_CONFIG_FILE ./.config +cp $OPENWIFI_DIR/driver/ad9361/ad9361.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361.c -rf + source $XILINX_DIR/SDK/2018.3/settings64.sh export ARCH=$ARCH_NAME export CROSS_COMPILE=$CROSS_COMPILE_NAME make oldconfig && make prepare && make modules_prepare -if [ "$#" -gt 3 ]; then - if [ -f "$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/arch/$ARCH_NAME/boot/$IMAGE_TYPE" ]; then - echo "Kernel found! Skip the time costly Linux kernel compiling." - else +if [ "$#" -gt 2 ]; then + # if [ -f "$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/arch/$ARCH_NAME/boot/$IMAGE_TYPE" ]; then + # echo "Kernel found! Skip the time costly Linux kernel compiling." + # else make -j12 $IMAGE_TYPE UIMAGE_LOADADDR=0x8000 make modules - fi + # fi fi cd $home_dir diff --git a/user_space/rf_init.sh b/user_space/rf_init.sh index 5efb7c1..397e847 100755 --- a/user_space/rf_init.sh +++ b/user_space/rf_init.sh @@ -1,5 +1,9 @@ #!/bin/sh +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + home_dir=$(pwd) if test -f "openwifi_ad9361_fir.ftr"; then @@ -81,7 +85,7 @@ echo "rssi" cat in_voltage0_rssi cat in_voltage1_rssi -# # --------not neede maybe-------- # # +# # --------not needed maybe-------- # # echo "rx0 gain to 70" # this set gain is gpio gain - 5dB (test with agc and read back gpio in driver) cat in_voltage0_hardwaregain echo 70 > in_voltage0_hardwaregain @@ -105,7 +109,7 @@ cat out_voltage1_hardwaregain echo 0 > out_voltage1_hardwaregain cat out_voltage1_hardwaregain sync -# # --------not neede maybe-------- # # +# # --------not needed maybe-------- # # cd $home_dir diff --git a/user_space/sdcard_boot_update.sh b/user_space/sdcard_boot_update.sh index d732291..bcd19f0 100755 --- a/user_space/sdcard_boot_update.sh +++ b/user_space/sdcard_boot_update.sh @@ -1,12 +1,17 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ "$#" -ne 1 ]; then echo "You must enter the \$BOARD_NAME as argument" - echo "Like: adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" + echo "Like: antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" exit 1 fi BOARD_NAME=$1 -if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then +if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else @@ -30,19 +35,44 @@ echo $image_filename set -x -rm BOOT.BIN +mv BOOT.BIN BOOT.BIN.bak sync wget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN +if [ -f "./BOOT.BIN" ]; then + echo "BOOT.BIN downloaded!" +else + echo "WARNING! BOOT.BIN not downloaded! Old file used!" + mv BOOT.BIN.bak BOOT.BIN +# exit 1 +fi sync -rm $image_filename + +mv $image_filename $image_filename.bak sync wget ftp://192.168.10.1/$LINUX_KERNEL_SRC_DIR_NAME/$image_filepath/$image_filename +if [ -f "./$image_filename" ]; then + echo "$image_filename downloaded!" +else + echo "WARNING! $image_filename not downloaded! Old file used!" + mv $image_filename.bak $image_filename +# exit 1 +fi sync -rm $dtb_filename + +mv $dtb_filename $dtb_filename.bak sync wget ftp://192.168.10.1/kernel_boot/boards/$BOARD_NAME/$dtb_filename +if [ -f "./$dtb_filename" ]; then + echo "$dtb_filename downloaded!" +else + echo "WARNING! $dtb_filename not downloaded! Old file used!" + mv $dtb_filename.bak $dtb_filename +# exit 1 +fi sync + #slepp 0.5 + mount /dev/mmcblk0p1 /mnt sync #sleep 0.5 diff --git a/user_space/sdr-ad-hoc-join.sh b/user_space/sdr-ad-hoc-join.sh index 33a9192..2c3d088 100755 --- a/user_space/sdr-ad-hoc-join.sh +++ b/user_space/sdr-ad-hoc-join.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ $# -ne 4 ] then echo "Please input NIC_name ch_number ip_addr cell as input parameter!" diff --git a/user_space/sdr-ad-hoc-up.sh b/user_space/sdr-ad-hoc-up.sh index 293e9c4..81c476d 100755 --- a/user_space/sdr-ad-hoc-up.sh +++ b/user_space/sdr-ad-hoc-up.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ $# -ne 3 ] then echo "Please input NIC_name ch_number ip_addr as input parameter!" diff --git a/user_space/sdrctl_src/cmd.c b/user_space/sdrctl_src/cmd.c index 7398e95..29f1951 100644 --- a/user_space/sdrctl_src/cmd.c +++ b/user_space/sdrctl_src/cmd.c @@ -1,4 +1,6 @@ -// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; +// Author: Xianjun Jiao +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later #include #include diff --git a/user_space/sdrctl_src/nl80211.h b/user_space/sdrctl_src/nl80211.h index 51626b4..95e3364 100644 --- a/user_space/sdrctl_src/nl80211.h +++ b/user_space/sdrctl_src/nl80211.h @@ -3,14 +3,15 @@ /* * 802.11 netlink interface public header * - * Copyright 2006-2010 Johannes Berg - * Copyright 2008 Michael Wu - * Copyright 2008 Luis Carlos Cobo - * Copyright 2008 Michael Buesch - * Copyright 2008, 2009 Luis R. Rodriguez - * Copyright 2008 Jouni Malinen - * Copyright 2008 Colin McCabe - * Copyright 2015-2017 Intel Deutschland GmbH + * SPDX-FileCopyrightText: 2006-2010 Johannes Berg + * SPDX-FileCopyrightText: 2008 Michael Wu + * SPDX-FileCopyrightText: 2008 Luis Carlos Cobo + * SPDX-FileCopyrightText: 2008 Michael Buesch + * SPDX-FileCopyrightText: 2008, 2009 Luis R. Rodriguez + * SPDX-FileCopyrightText: 2008 Jouni Malinen + * SPDX-FileCopyrightText: 2008 Colin McCabe + * SPDX-FileCopyrightText: 2015-2017 Intel Deutschland GmbH + * SPDX-License-Identifier: ISC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -395,7 +396,7 @@ * %NL80211_ATTR_SCHED_SCAN_PLANS. If %NL80211_ATTR_SCHED_SCAN_PLANS is * not specified and only %NL80211_ATTR_SCHED_SCAN_INTERVAL is specified, * scheduled scan will run in an infinite loop with the specified interval. - * These attributes are mutually exculsive, + * These attributes are mutually exclusive, * i.e. NL80211_ATTR_SCHED_SCAN_INTERVAL must not be passed if * NL80211_ATTR_SCHED_SCAN_PLANS is defined. * If for some reason scheduled scan is aborted by the driver, all scan @@ -569,7 +570,7 @@ * authentication/association or not receiving a response from the AP. * Non-zero %NL80211_ATTR_STATUS_CODE value is indicated in that case as * well to remain backwards compatible. - * @NL80211_CMD_ROAM: notifcation indicating the card/driver roamed by itself. + * @NL80211_CMD_ROAM: notification indicating the card/driver roamed by itself. * When the driver roamed in a network that requires 802.1X authentication, * %NL80211_ATTR_PORT_AUTHORIZED should be set if the 802.1X authentication * was done by the driver or if roaming was done using Fast Transition @@ -735,7 +736,7 @@ * inform userspace of the new replay counter. * * @NL80211_CMD_PMKSA_CANDIDATE: This is used as an event to inform userspace - * of PMKSA caching dandidates. + * of PMKSA caching candidates. * * @NL80211_CMD_TDLS_OPER: Perform a high-level TDLS command (e.g. link setup). * In addition, this can be used as an event to request userspace to take @@ -771,7 +772,7 @@ * * @NL80211_CMD_PROBE_CLIENT: Probe an associated station on an AP interface * by sending a null data frame to it and reporting when the frame is - * acknowleged. This is used to allow timing out inactive clients. Uses + * acknowledged. This is used to allow timing out inactive clients. Uses * %NL80211_ATTR_IFINDEX and %NL80211_ATTR_MAC. The command returns a * direct reply with an %NL80211_ATTR_COOKIE that is later used to match * up the event with the request. The event includes the same data and @@ -1557,10 +1558,10 @@ enum nl80211_commands { * bit. Depending on which antennas are selected in the bitmap, 802.11n * drivers can derive which chainmasks to use (if all antennas belonging to * a particular chain are disabled this chain should be disabled) and if - * a chain has diversity antennas wether diversity should be used or not. + * a chain has diversity antennas whether diversity should be used or not. * HT capabilities (STBC, TX Beamforming, Antenna selection) can be * derived from the available chains after applying the antenna mask. - * Non-802.11n drivers can derive wether to use diversity or not. + * Non-802.11n drivers can derive whether to use diversity or not. * Drivers may reject configurations or RX/TX mask combinations they cannot * support by returning -EINVAL. * @@ -1628,7 +1629,7 @@ enum nl80211_commands { * the values passed in @NL80211_ATTR_SCAN_SSIDS (eg. if an SSID * is included in the probe request, but the match attributes * will never let it go through), -EINVAL may be returned. - * If ommited, no filtering is done. + * If omitted, no filtering is done. * * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported * interface combinations. In each nested item, it contains attributes @@ -1733,7 +1734,7 @@ enum nl80211_commands { * * @NL80211_ATTR_INACTIVITY_TIMEOUT: timeout value in seconds, this can be * used by the drivers which has MLME in firmware and does not have support - * to report per station tx/rx activity to free up the staion entry from + * to report per station tx/rx activity to free up the station entry from * the list. This needs to be used when the driver advertises the * capability to timeout the stations. * @@ -2088,7 +2089,7 @@ enum nl80211_commands { * * @NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST: When present the RSSI level for BSSs in * the specified band is to be adjusted before doing - * %NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI based comparision to figure out + * %NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI based comparison to figure out * better BSSs. The attribute value is a packed structure * value as specified by &struct nl80211_bss_select_rssi_adjust. * @@ -2989,7 +2990,7 @@ enum nl80211_mpath_flags { * @NL80211_MPATH_INFO_DISCOVERY_TIMEOUT: total path discovery timeout, in msec * @NL80211_MPATH_INFO_DISCOVERY_RETRIES: mesh path discovery retries * @NL80211_MPATH_INFO_MAX: highest mesh path information attribute number - * currently defind + * currently defined * @__NL80211_MPATH_INFO_AFTER_LAST: internal use */ enum nl80211_mpath_info { @@ -3060,7 +3061,7 @@ enum nl80211_band_attr { * (100 * dBm). * @NL80211_FREQUENCY_ATTR_DFS_STATE: current state for DFS * (enum nl80211_dfs_state) - * @NL80211_FREQUENCY_ATTR_DFS_TIME: time in miliseconds for how long + * @NL80211_FREQUENCY_ATTR_DFS_TIME: time in milliseconds for how long * this channel is in this DFS state. * @NL80211_FREQUENCY_ATTR_NO_HT40_MINUS: HT40- isn't possible with this * channel as the control channel @@ -4485,7 +4486,7 @@ enum nl80211_attr_coalesce_rule { /** * enum nl80211_coalesce_condition - coalesce rule conditions - * @NL80211_COALESCE_CONDITION_MATCH: coalaesce Rx packets when patterns + * @NL80211_COALESCE_CONDITION_MATCH: coalesce Rx packets when patterns * in a rule are matched. * @NL80211_COALESCE_CONDITION_NO_MATCH: coalesce Rx packets when patterns * in a rule are not matched. @@ -4554,7 +4555,7 @@ enum nl80211_iface_limit_attrs { * numbers = [ #{STA} <= 1, #{P2P-client,P2P-GO} <= 3 ], max = 4 * => allows a STA plus three P2P interfaces * - * The list of these four possiblities could completely be contained + * The list of these four possibilities could completely be contained * within the %NL80211_ATTR_INTERFACE_COMBINATIONS attribute to indicate * that any of these groups must match. * @@ -4584,7 +4585,7 @@ enum nl80211_if_combination_attrs { * enum nl80211_plink_state - state of a mesh peer link finite state machine * * @NL80211_PLINK_LISTEN: initial state, considered the implicit - * state of non existant mesh peer links + * state of non existent mesh peer links * @NL80211_PLINK_OPN_SNT: mesh plink open frame has been sent to * this mesh peer * @NL80211_PLINK_OPN_RCVD: mesh plink open frame has been received @@ -4744,7 +4745,7 @@ enum nl80211_ap_sme_features { * @NL80211_FEATURE_INACTIVITY_TIMER: This driver takes care of freeing up * the connected inactive stations in AP mode. * @NL80211_FEATURE_CELL_BASE_REG_HINTS: This driver has been tested - * to work properly to suppport receiving regulatory hints from + * to work properly to support receiving regulatory hints from * cellular base stations. * @NL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL: (no longer available, only * here to reserve the value for API/ABI compatibility) diff --git a/user_space/sdrctl_src/nl80211_testmode_def.h b/user_space/sdrctl_src/nl80211_testmode_def.h index f824f22..f7d6578 100644 --- a/user_space/sdrctl_src/nl80211_testmode_def.h +++ b/user_space/sdrctl_src/nl80211_testmode_def.h @@ -1,3 +1,7 @@ +// Author: Xianjun Jiao +// SPDX-FileCopyrightText: 2019 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later + //---nl80211 cmd testmode definitions //---should be used in driver sdr.c and user space app diff --git a/user_space/sdrctl_src/sdrctl.c b/user_space/sdrctl_src/sdrctl.c index 0870270..0dd84dd 100644 --- a/user_space/sdrctl_src/sdrctl.c +++ b/user_space/sdrctl_src/sdrctl.c @@ -1,8 +1,9 @@ /* * nl80211 userspace tool * - * Copyright 2007, 2008 Johannes Berg - * Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; + * SPDX-FileCopyrightText: Copyright 2007, 2008 Johannes Berg + * Modified by Xianjun jiao + * SPDX-License-Identifier: AGPL-3.0-or-later */ #include diff --git a/user_space/sdrctl_src/sdrctl.h b/user_space/sdrctl_src/sdrctl.h index 2be0627..a3b194e 100644 --- a/user_space/sdrctl_src/sdrctl.h +++ b/user_space/sdrctl_src/sdrctl.h @@ -1,3 +1,9 @@ +/* + * Author: Xianjun Jiao + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ + #ifndef __IW_H #define __IW_H diff --git a/user_space/sdrctl_src/sections.c b/user_space/sdrctl_src/sections.c index 3bc2ac4..accabb9 100644 --- a/user_space/sdrctl_src/sections.c +++ b/user_space/sdrctl_src/sections.c @@ -1,3 +1,9 @@ +/* + * Author: Xianjun Jiao + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later +*/ + #include "sdrctl.h" SECTION(get); diff --git a/user_space/sdrctl_src/version.sh b/user_space/sdrctl_src/version.sh index 1adcecf..0d2798d 100755 --- a/user_space/sdrctl_src/version.sh +++ b/user_space/sdrctl_src/version.sh @@ -1,5 +1,9 @@ #!/bin/sh +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + VERSION="3.17" OUT="$1" diff --git a/user_space/set_ant.sh b/user_space/set_ant.sh index baf9b84..e46286c 100755 --- a/user_space/set_ant.sh +++ b/user_space/set_ant.sh @@ -1,5 +1,9 @@ #!/bin/sh +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ "$#" -ne 2 ]; then echo "Need 2 arguments. The 1st select rx antenna. The 2nd for tx antenna." echo "Eg, " diff --git a/user_space/set_csma_high.sh b/user_space/set_csma_high.sh index 53e5a06..caecc9f 100755 --- a/user_space/set_csma_high.sh +++ b/user_space/set_csma_high.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + ./sdrctl dev sdr0 get reg xpu 19 ./sdrctl dev sdr0 set reg xpu 19 3758096384 diff --git a/user_space/set_csma_normal.sh b/user_space/set_csma_normal.sh index 25aeb85..87f2207 100755 --- a/user_space/set_csma_normal.sh +++ b/user_space/set_csma_normal.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + ./sdrctl dev sdr0 get reg xpu 19 ./sdrctl dev sdr0 set reg xpu 19 3 diff --git a/user_space/side_ch_ctl_src/save_iq_to_txt_for_verilog_sim.m b/user_space/side_ch_ctl_src/save_iq_to_txt_for_verilog_sim.m new file mode 100644 index 0000000..2d85e24 --- /dev/null +++ b/user_space/side_ch_ctl_src/save_iq_to_txt_for_verilog_sim.m @@ -0,0 +1,39 @@ +% Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com + +function save_iq_to_txt_for_verilog_sim(mat_filename, varargin) +a = load(mat_filename); +var_names = fieldnames(a); +var_cells = struct2cell(a); +[len_iq, num_frame] = size(var_cells{1}); + +if nargin>=2 + idx_set = varargin{1}; +else + idx_set = 1:num_frame; +end + +if nargin >= 3 + sp = varargin{2}(1); + ep = varargin{2}(2); +else + sp = 1; + ep = len_iq; +end + +for name_idx = 1 : length(var_names) + filename_txt = [var_names{name_idx} '.txt']; + fid = fopen(filename_txt,'w'); + if fid == -1 + disp('fopen failed'); + return; + end + var_tmp = var_cells{name_idx}; + for j=1:length(idx_set) + idx = idx_set(j); + iq = var_tmp(:,idx); + for i=sp:ep + fprintf(fid, '%d %d\n', round(real(iq(i))), round(imag(iq(i)))); + end + end + fclose(fid); +end diff --git a/user_space/side_ch_ctl_src/side_ch_ctl.c b/user_space/side_ch_ctl_src/side_ch_ctl.c index af1e0ce..3d87038 100644 --- a/user_space/side_ch_ctl_src/side_ch_ctl.c +++ b/user_space/side_ch_ctl_src/side_ch_ctl.c @@ -1,6 +1,8 @@ /* * openwifi side channel user space program - * Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be + * Author: Xianjun Jiao + * SPDX-FileCopyrightText: 2019 UGent + * SPDX-License-Identifier: AGPL-3.0-or-later */ #include @@ -149,7 +151,7 @@ int parse_para_string(char *para, int *action_flag, int *reg_type, int *reg_idx, if ( para[0] == 'g'){// || para[0] == 'G' ) { (*action_flag) = ACTION_SIDE_INFO_GET; - if (para_string_len == 1) { // no explict input + if (para_string_len == 1) { // no explicit input (*interval_ms) = 100; printf("The default 100ms side info getting period is taken!\n"); return(0); @@ -400,4 +402,4 @@ int main(const int argc, char * const argv[]) close(s); close(sock_fd); return(ret); -} \ No newline at end of file +} diff --git a/user_space/side_ch_ctl_src/test_iq_2ant_file_display.m b/user_space/side_ch_ctl_src/test_iq_2ant_file_display.m index d36670c..0181387 100644 --- a/user_space/side_ch_ctl_src/test_iq_2ant_file_display.m +++ b/user_space/side_ch_ctl_src/test_iq_2ant_file_display.m @@ -1,10 +1,15 @@ % Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com -clear all; -close all; +% clear all; +% close all; +function test_iq_2ant_file_display(varargin) -% iq_len = 8187; % default for big fpga -iq_len = 4095; % for small fpga +if nargin == 0 + iq_len = 8187; % default for big fpga + % iq_len = 4095; % for small fpga +else + iq_len = varargin{1}; +end a = load('iq_2ant.txt'); len_a = floor(length(a)/4)*4; @@ -16,14 +21,17 @@ num_iq_capture = floor(size(b,1)/num_data_in_each_iq_capture); iq0_capture = zeros(iq_len, num_iq_capture); iq1_capture = zeros(iq_len, num_iq_capture); +timestamp = zeros(1, num_iq_capture); for i=1:num_iq_capture sp = (i-1)*num_data_in_each_iq_capture + 1; ep = i*num_data_in_each_iq_capture; timestamp(i) = b(sp,1) + (2^16)*b(sp,2) + (2^32)*b(sp,3) + (2^48)*b(sp,4); - iq0_capture(:,i) = b((sp+1):ep,1) + 1i.*b((sp+1):ep,2); - iq1_capture(:,i) = b((sp+1):ep,3) + 1i.*b((sp+1):ep,4); + iq0_capture(:,i) = 1i.*b((sp+1):ep,1) + b((sp+1):ep,2); + iq1_capture(:,i) = 1i.*b((sp+1):ep,3) + b((sp+1):ep,4); end +save(['iq_2ant_' num2str(iq_len) '.mat'], 'iq0_capture', 'iq1_capture'); + iq0_capture = iq0_capture(:); iq1_capture = iq1_capture(:); @@ -38,7 +46,7 @@ plot(real(iq1_capture)); hold on; plot(imag(iq1_capture),'r'); title('rx1 I (blu figure; a = abs(iq0_capture); b = abs(iq1_capture); -a(a==0) = max(b); +% a(a==0) = max(b); plot(a); hold on; plot(b,'r'); title('rx0 and rx1 abs'); xlabel('sample'); ylabel('abs'); grid on; legend('rx0','rx1'); diff --git a/user_space/side_ch_ctl_src/test_iq_file_display.m b/user_space/side_ch_ctl_src/test_iq_file_display.m index a3668df..5705306 100644 --- a/user_space/side_ch_ctl_src/test_iq_file_display.m +++ b/user_space/side_ch_ctl_src/test_iq_file_display.m @@ -1,9 +1,15 @@ % Xianjun Jiao. xianjun.jiao@imec.be; putaoshu@msn.com -clear all; -close all; +% clear all; +% close all; -iq_len = 8187; +function test_iq_file_display(varargin) + +if nargin == 0 + iq_len = 8187; +else + iq_len = varargin{1}; +end a = load('iq.txt'); len_a = floor(length(a)/4)*4; @@ -22,10 +28,12 @@ for i=1:num_iq_capture sp = (i-1)*num_data_in_each_iq_capture + 1; ep = i*num_data_in_each_iq_capture; timestamp(i) = b(sp,1) + (2^16)*b(sp,2) + (2^32)*b(sp,3) + (2^48)*b(sp,4); - iq_capture(:,i) = b((sp+1):ep,1) + 1i.*b((sp+1):ep,2); + iq_capture(:,i) = 1i.*b((sp+1):ep,1) + b((sp+1):ep,2); agc_gain(:,i) = b((sp+1):ep,3); rssi_half_db(:,i) = b((sp+1):ep,4); end +save(['iq_' num2str(iq_len) '.mat'], 'iq_capture'); + iq_capture = iq_capture(:); agc_gain = agc_gain(:); rssi_half_db = rssi_half_db(:); diff --git a/user_space/slice_cfg.sh b/user_space/slice_cfg.sh index ef6ed2f..894ece8 100755 --- a/user_space/slice_cfg.sh +++ b/user_space/slice_cfg.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ $# -ne 5 ] then echo "Please input slice_idx mac_addr cycle_period(us) start_time(us) end_time(us) as input parameter!" diff --git a/user_space/update_sdcard.sh b/user_space/update_sdcard.sh index a79c853..c2649bd 100755 --- a/user_space/update_sdcard.sh +++ b/user_space/update_sdcard.sh @@ -1,16 +1,26 @@ #!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + if [ "$#" -ne 4 ]; then echo "You have input $# arguments." - echo "You must enter exactly 4 arguments: \$OPENWIFI_DIR \$XILINX_DIR \$BOARD_NAME \$SDCARD_DIR" + echo "You must enter exactly 4 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME \$SDCARD_DIR" exit 1 fi -OPENWIFI_DIR=$1 +OPENWIFI_HW_DIR=$1 XILINX_DIR=$2 BOARD_NAME=$3 SDCARD_DIR=$4 +OPENWIFI_DIR=$(pwd)/../ + +echo OPENWIFI_DIR $OPENWIFI_DIR +echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR + if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" else @@ -25,13 +35,20 @@ else exit 1 fi -if [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then +if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else echo "\$BOARD_NAME is found!" fi +if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then + echo "\$OPENWIFI_HW_DIR is found!" +else + echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + exit 1 +fi + # detect SD card mounting status if [ -d "$SDCARD_DIR/BOOT/" ]; then echo "$SDCARD_DIR/BOOT/" @@ -69,19 +86,12 @@ LINUX_KERNEL_SRC_DIR_NAME32=adi-linux LINUX_KERNEL_SRC_DIR_NAME64=adi-linux-64 cd $OPENWIFI_DIR/user_space/ -# special case, we need our xilinx_dma.c is there when building kernel to avoid version issue -cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/drivers/dma/xilinx/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/drivers/dma/xilinx/xilinx_dma.c.bak -cp $OPENWIFI_DIR/driver/xilinx_dma/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/drivers/dma/xilinx -rf -./prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR 32 build +./prepare_kernel.sh $XILINX_DIR 32 build sudo true -cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/drivers/dma/xilinx/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/drivers/dma/xilinx/xilinx_dma.c.bak -cp $OPENWIFI_DIR/driver/xilinx_dma/xilinx_dma.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/drivers/dma/xilinx -rf -./prepare_kernel.sh $OPENWIFI_DIR $XILINX_DIR 64 build +./prepare_kernel.sh $XILINX_DIR 64 build sudo true -$OPENWIFI_DIR/user_space/get_fpga.sh $OPENWIFI_DIR - -BOARD_NAME_ALL="zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 zcu102_9371" +BOARD_NAME_ALL="antsdr zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 zcu102_9371" # BOARD_NAME_ALL="zcu102_fmcs2" # BOARD_NAME_ALL="adrv9361z7035" for BOARD_NAME_TMP in $BOARD_NAME_ALL @@ -89,11 +99,11 @@ do if [ "$BOARD_NAME_TMP" == "zcu102_fmcs2" ] || [ "$BOARD_NAME_TMP" == "zcu102_9371" ]; then dtb_filename_tmp="system.dtb" dts_filename_tmp="system.dts" - $OPENWIFI_DIR/user_space/boot_bin_gen_zynqmp.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME_TMP + ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME_TMP else dtb_filename_tmp="devicetree.dtb" dts_filename_tmp="devicetree.dts" - $OPENWIFI_DIR/user_space/boot_bin_gen.sh $OPENWIFI_DIR $XILINX_DIR $BOARD_NAME_TMP + ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME_TMP fi echo $dtb_filename_tmp echo $dts_filename_tmp @@ -110,29 +120,44 @@ sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD sudo mkdir $SDCARD_DIR/BOOT/openwifi/zynqmp-common sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/openwifi/zynqmp-common/ -# Copy uImage BOOT.BIN and devicetree to SD card BOOT partition +sudo mkdir $SDCARD_DIR/rootfs/root/openwifi + +# Copy uImage BOOT.BIN and devicetree to SD card BOOT partition and backup at rootfs/root/openwifi sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/$dtb_filename $SDCARD_DIR/BOOT/ +sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/$dtb_filename $SDCARD_DIR/rootfs/root/openwifi/ -rf sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/ +sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN $SDCARD_DIR/rootfs/root/openwifi/ -rf if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/rootfs/root/openwifi/ -rf else sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/BOOT/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/rootfs/root/openwifi/ -rf fi -sudo mkdir $SDCARD_DIR/rootfs/root/openwifi sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/ -rf sudo wget -P $SDCARD_DIR/rootfs/root/openwifi/webserver/ https://users.ugent.be/~xjiao/openwifi-low-aac.mp4 # build openwifi driver -$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR 32 -$OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR 32 +saved_dir=$(pwd) +cd $OPENWIFI_DIR/driver +./make_all.sh $XILINX_DIR 32 +cd $OPENWIFI_DIR/driver/side_ch +./make_driver.sh $XILINX_DIR 32 +cd $saved_dir + # Copy files to SD card rootfs partition sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv32 sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv32 \; # build openwifi driver -$OPENWIFI_DIR/driver/make_all.sh $OPENWIFI_DIR $XILINX_DIR 64 -$OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR 64 +saved_dir=$(pwd) +cd $OPENWIFI_DIR/driver +./make_all.sh $XILINX_DIR 64 +cd $OPENWIFI_DIR/driver/side_ch +./make_driver.sh $XILINX_DIR 64 +cd $saved_dir + # Copy files to SD card rootfs partition sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv64 sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv64 \; @@ -141,11 +166,11 @@ sudo mkdir $SDCARD_DIR/rootfs/lib/modules sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32 sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/ \; -sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f +sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/{axidmatest.ko,adi_axi_hdmi.ko} -f sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64 sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/ \; -sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f +sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/{axidmatest.ko,adi_axi_hdmi.ko} -f sudo rm $SDCARD_DIR/rootfs/etc/udev/rules.d/70-persistent-net.rules sudo cp $OPENWIFI_DIR/kernel_boot/70-persistent-net.rules $SDCARD_DIR/rootfs/etc/udev/rules.d/ diff --git a/user_space/webserver/openwifi-detail.jpg b/user_space/webserver/openwifi-detail.jpg index 2527749..312277a 100644 Binary files a/user_space/webserver/openwifi-detail.jpg and b/user_space/webserver/openwifi-detail.jpg differ diff --git a/user_space/webserver/openwifi-detail.jpg.license b/user_space/webserver/openwifi-detail.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/user_space/webserver/openwifi-detail.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/user_space/webserver/openwifi-logo-small.jpg.license b/user_space/webserver/openwifi-logo-small.jpg.license new file mode 100644 index 0000000..b5c5f6b --- /dev/null +++ b/user_space/webserver/openwifi-logo-small.jpg.license @@ -0,0 +1,5 @@ + +# Author: Xianjun jiao + +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later diff --git a/user_space/wgd.sh b/user_space/wgd.sh index 1d3fd12..99f7829 100755 --- a/user_space/wgd.sh +++ b/user_space/wgd.sh @@ -1,5 +1,9 @@ #!/bin/bash +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + checkModule () { MODULE="$1" if lsmod | grep "$MODULE" &> /dev/null ; then @@ -42,26 +46,6 @@ modprobe mac80211 PROG=sdr rmmod $PROG -SUBMODULE=xilinx_dma -if [ $last_input == "remote" ] - then - rm $SUBMODULE.ko - sync - wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko - sync -fi -rmmod $SUBMODULE -insmod $SUBMODULE.ko - -#sleep 1 - -echo check $SUBMODULE module is loaded or not -checkModule $SUBMODULE -if [ $? -eq 1 ] -then - return -fi - # before drive ad9361, let's bring up duc and make sure dac is connected to ad9361 dma SUBMODULE=tx_intf if [ $last_input == "remote" ] @@ -82,24 +66,24 @@ then fi sleep 0.5 -SUBMODULE=ad9361_drv -if [ $last_input == "remote" ] - then - rm $SUBMODULE.ko - sync - wget ftp://192.168.10.1/driver/ad9361/$SUBMODULE.ko - sync -fi -rmmod $SUBMODULE -insmod $SUBMODULE.ko +# SUBMODULE=ad9361_drv +# if [ $last_input == "remote" ] +# then +# rm $SUBMODULE.ko +# sync +# wget ftp://192.168.10.1/driver/ad9361/$SUBMODULE.ko +# sync +# fi +# rmmod $SUBMODULE +# insmod $SUBMODULE.ko -echo check $SUBMODULE module is loaded or not -checkModule $SUBMODULE -if [ $? -eq 1 ] -then - return -fi -sleep 1 +# echo check $SUBMODULE module is loaded or not +# checkModule $SUBMODULE +# if [ $? -eq 1 ] +# then +# return +# fi +# sleep 1 echo "set RF frontend" # if [ $last_input == "remote" ] diff --git a/user_space/wpa-openwifi.conf b/user_space/wpa-openwifi.conf new file mode 100644 index 0000000..7c240a6 --- /dev/null +++ b/user_space/wpa-openwifi.conf @@ -0,0 +1,4 @@ +network={ + ssid="openwifi" + key_mgmt=NONE +}