34 Commits

Author	SHA1	Message	Date
Xianjun Jiao	b2e08ff46e	Add precise sample_in_strobe phase control into dot11_tb.v for debugging the back luck FPGA loopback issue	2023-01-09 15:56:17 +01:00
thavinga	95e93cadfd	LVPE correction before estimation ... - Add state in equalizer and rename others - Add new dumper files in testbench to check with MATLAB	2023-01-09 15:45:05 +01:00
thavinga	b0df85040f	Add FFT window shift register	2023-01-09 15:40:42 +01:00
Xianjun Jiao	4359e4f96d	Add phy len log into dot11_tb	2023-01-09 15:25:29 +01:00
Xianjun Jiao	27392f217f	Adapt the test bench to align with ...	2023-01-09 14:51:55 +01:00
Xianjun Jiao	a1e1e0090b	Add threshold_scale and enable it by default: ... sync short works at low SNR and the receiver sensitivity is better	2023-01-09 14:43:34 +01:00
Wei Liu	2747d431f9	fix viterbi decoder logging issue	2023-01-05 16:47:07 +01:00
Wei Liu	fe93170efc	log all header bits, also when error occors	2023-01-05 16:45:43 +01:00
Wei Liu	c9f3d280a3	clean up log file, prolong simulation at the end by 300 sp	2023-01-05 16:38:51 +01:00
Xianjun Jiao	707cb99a90	Remove the huge logging thing in dot11_tb.v	2022-07-15 12:10:03 +02:00
Xianjun Jiao	064bbe4250	Auto stop the simulation at the end of iq sample file	2022-05-16 09:53:07 +02:00
Xianjun Jiao	f6fd0a2a85	Minor cleaning	2022-05-16 09:52:24 +02:00
Xianjun Jiao	7622d7aaa0	Disable signal watch dog for normal simulation in the tb	2022-05-16 09:51:30 +02:00
Xianjun Jiao	55f77bb16b	Connect pkt_len from dot11 to signal watch dog in the tb	2022-05-16 09:51:01 +02:00
thavinga	cb6b566d5f	Move all signal logging to dot11_tb.v	2022-05-16 09:33:19 +02:00
Xianjun Jiao	1659c01ac7	Add conditional compiling framework	2022-05-13 13:24:41 +02:00
Xianjun Jiao	44c8846072	Add more test vectors into testing_inputs/simulated	2022-03-16 15:07:48 +01:00
Xianjun Jiao	f08c76ca3d	Add signal_watchdog module to prevent fake demod in early phase: ... 1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset 2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver	2022-03-15 16:03:40 +01:00
Xianjun Jiao	954bae4e77	Add a test vector fake-demod-0.txt that could cause fake demodulation	2022-03-15 15:53:36 +01:00
Xianjun Jiao	566e82f43e	Add more clock cases into dot11_tb.v	2022-01-28 12:17:16 +01:00
mmehari	e257d3373b	storage update: A-MPDU decoding	2022-01-04 22:20:44 +01:00
mmehari	48aade0190	provide demod_soft_bits and demod_soft_bits_pos signals out	2022-01-04 22:18:23 +01:00
Xianjun Jiao	8714c30857	output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux	2020-10-08 10:06:03 +02:00
Xianjun Jiao	539133f453	make the code more testbench friendly	2020-09-02 21:59:37 +02:00
Xianjun Jiao	2b3a043e8c	turn on soft_decoding in dot11_tb.v	2020-09-02 17:15:11 +02:00
Xianjun Jiao	abbe9ecde9	extend support to zcu102/Zynq MPSoC ultra_scale	2020-04-27 15:46:16 +02:00
mmehari	1f8bb83587	soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM	2019-12-10 13:45:43 +01:00
Xianjun Jiao	2643844f2f	necessary bug fixes and improvements for openwifi	2019-12-10 13:31:16 +01:00
weiliu	10ff8da3d7	port dot11 to zynq	2019-12-10 14:09:31 +01:00
Jinghao Shi	079744bec1	fix dot11 port pinout	2017-04-21 13:42:09 -04:00
Jinghao Shi	e5d4dc7cfc	enlarge num_sample	2017-04-14 11:01:18 -04:00
Jinghao Shi	297162af13	working	2017-04-07 16:51:06 -04:00
Jinghao Shi	cf42e1b7ae	working	2017-04-03 15:48:25 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00