Commit Graph

790 Commits

Author SHA1 Message Date
Norman Feske
a4c59c03e3 core: rework page-fault resolution
The change "core: allow offset-attached managed dataspaces" addressed a
corner case of the use of nested region maps. Apparently, this change
negatively affects other scenarios (tool_chain_auto).

In order to confidently cover all the differnt situations, this patch
reworks the page-fault resolution code for improved clarity and safety,
by introducing dedicated result types, reducing the use of basic types,
choosing expressive names, and fostering constness.

It also introduces a number of 'print' hooks that greatly ease manual
instrumentation and streamlines the error messages printed by core.
Those messages no longer appear when a user-level page-fault handler
is reistered for the faulted-at region map. So the monitor component
produces less noise on the attempt to dump non-existing memory.

Issue #4917
Fixes #4920
2023-06-16 11:24:26 +02:00
Alexander Boettcher
b349dd9c0a sel4: convert io memory on demand
instead all during boot. On x86 and qemu this takes quite a while until
the system is booted.

Fixes #4913
2023-06-16 11:24:25 +02:00
Benjamin Lamowski
e882ca748d base-hw: virt: implement support for SVM
Ref #4826
2023-05-30 12:13:34 +02:00
Benjamin Lamowski
1e3836f8b5 base-hw: pass generic Vm_data structure to the kernel object
This enables passing additional data structures to the kernel on x86.

Ref #4826
2023-05-30 12:13:34 +02:00
Benjamin Lamowski
312b638220 base-hw: export Intel TSC platform information
Export TSC invariant and the frequency reported on Intel processors.
Currently lacks TSC calibration and reports a fixed frequency on AMD.

Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
c75b07e0fd base-hw: SVM: allow execute on NPT mappings
Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
cb69c59fa3 base-hw: implement VMCB data structure for AMD SVM
Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
0a819d5e19 base-hw: add MSR and CPUID registers for AMD SVM
Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
e11ed069bf base-hw: fix x86 CPUID register width
Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
7477f99d05 base-hw: x86: detect CPU Vendor and SVM support
Ref #4826
2023-05-30 12:13:33 +02:00
Benjamin Lamowski
6ca7119267 base-hw: copy virtualization structure for x86_64
Ref #4826
2023-05-30 12:13:33 +02:00
Stefan Kalkowski
0aef0959d5 hw: catch all cache lines for mis-aligned addresses
Fix genodelabs/genode#4905
2023-05-30 12:03:33 +02:00
Stefan Kalkowski
90690d96d4 hw: fix build errors with -std=gnu++20
Fix genodelabs/genode#4894
2023-05-30 12:03:31 +02:00
Christian Prochaska
b29db99f1c hw: fix build error with gcc 12
Fixes #4831
2023-05-08 15:55:35 +02:00
Norman Feske
61926ebc07 base: introduce platform_init function
The new 'init_platform' function performs the platform-specific
component-local low-level initialization. It allows for the
differentiation between core and regular components as well as
kernel-dependent peculiarities.

This patch introduces a consistent notion of a 'Platform'. Within core,
the 'Platform' contains the kernel-specific initialization. Outside
core, the platform sets up the interplay with the parent component. In
all cases, the platform is constructed while running on the initial
stack.

Issue #4784
2023-03-15 17:05:01 +01:00
Norman Feske
c99fb2b69b core: replace use of Avl_string by Dictionary
Issue #4780
2023-03-13 14:32:53 +01:00
Norman Feske
9debad4e91 Remove format strings from connection types
Issue #2064
2023-03-13 14:32:37 +01:00
Norman Feske
2e6dd010ae core: introduce 'Core' namespace
The namespace draws a clear line between the base library and the core
component.

It is declared at the new core-local header <types.h>, which is expected
to be included by all code of the core component. It is thereby a
natural place for kernel-agnostic general types like commonly used C++
utilities.

Fixes #4777
2023-03-13 14:32:37 +01:00
Alexander Boettcher
df27cc87b5 hw/x86: add suspend kernel syscall
using the ACPI mechanism. The syscall can be triggered solely via core's
RPC managing_system call.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
30c6feb86e hw/x86: re-init devices on resume
Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
1ea6708d84 hw/x86: prepare ACPI resume entry
Set wakeup pointer in FADT/FACS tables and prepare/place ACPI resume code
at application processors (AP) 16-bit entry. Exclude memory used for AP resume
from RAM range to avoid usage by Genode core in allocators.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
faf54244c4 hw/x86: keep cpu id after resume
The CPUs are woken all at once and up to now the IDs are assigned depending
on the arrival order, which is unfortunate for the resume case. Keep track
of once assigned IDs for CPUs, so that on resume the very same CPU id is given.
The APIC id is guaranteed to be fixed per CPU on suspend, but unfortunately
not dense packed.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
32b1aa605a hw/x86: add ACPI tables for resume
The ACPI table FACS and FADT are required to support ACPI suspend/resume. The
commits add the lookup of the ACPI table in bootstrap and the general usage
of the ACPI registers via the MMIO framework.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
dc1996d289 hw/x86: add interrupt controller re-init support
Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
1da71afbf3 hw: add Serial re-init/resume support
Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
5587476b4e hw: add Timer re-init/resume support
Add explicit init() to Timer infrastructure to re-initialize the hardware
based on the parameters given during constructing time of the timer object.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
1b5bfec8f9 hw: add CPU re-init/resume support
On resume the CPU state must be re-initialized, since all CPUs have been
potentially off (depending on sleep form) and lost state. Handle the halt
and suspend state explicitly by an extra Job implementation which can be
executed without holding the global kernel lock.

Issue #4669
2023-02-27 08:22:50 +01:00
Alexander Boettcher
a20a26b41b hw: add IPI type to flush and stop CPUs
as preparation before powering off the CPU

Issue #4669
2023-02-27 08:22:50 +01:00
Stefan Kalkowski
80453236c4 hw: don't depend on ARMv8 HCR, CPTR EL2 reg values
Instead of re-using the register values found in HCR_EL2 and CPTR_EL2
and setting single bits within them, define the complete content to
prevent inconsistent hardware/hypervisor state.

Ref genodelabs/genode#4759
2023-02-27 08:22:49 +01:00
Norman Feske
6d25ffc70b Remove base/lock_guard.h
For Genode API users, the 'Mutex::Guard' is the way to go.
Special lock implementations can bring their own 'Guard' utilities.

Fixes #4769
2023-02-27 08:22:49 +01:00
Norman Feske
356506a67a base: remove base/blocking.h
This patch removes the obsolete exception type 'Blocking_canceled'.

Issue #4768
2023-02-27 08:22:49 +01:00
Stefan Kalkowski
13453e3c68 hw: activate strict conversion checking in kernel
Fix genodelabs/genode#4753
2023-02-27 08:22:48 +01:00
Stefan Kalkowski
0212f94809 hw: eliminate -DNR_OF_CPUS, use constant instead
Fix genodelabs/genode#4752
2023-02-27 08:22:48 +01:00
Martin Stein
5bdc88bf57 base-hw scheduler: sanitize access to invalid head
Issue #4755
2023-02-27 08:22:47 +01:00
Johannes Schlatow
4d0cb175da base-hw: use global timer on Cortex A9
genodelabs/genode#4360
2023-02-27 08:20:45 +01:00
Benjamin Lamowski
641fadb3e9 base-hw: remove memory hole in bootstrap page table
Tests on qemu would fail when started with RAM sizes from 1025MiB to
2048MiB, because the the mapping hole in the page table from 1GiB to
2GiB would interfere with qemu's mapping addresses for ACPI.

Identity-map the complete first 4GiB of memory to catch all early
memory accesses during bootstrap.

Fixes #4724.
2023-01-24 12:07:31 +01:00
Norman Feske
0e311845bf base-hw: don't show ROM modules at boot time
On complex scenarios like Sculpt on the phone, this change noticeably
reduces the boot time.

Issue #4705
2023-01-24 12:07:31 +01:00
Martin Stein
68afbbc0f0 base-hw scheduler test: print method
Adds befriended test-local wrappers for the classes Cpu_share and Cpu_scheduler
and adds a print method to the scheduler wrapper that prints the internal state
of the scheduler to the given output. Cpu_shares are referenced in the output
via a the IDs that the test uses to organize them. I.e., this corresponds to
how the CPU shares are named when calling the atomic steps the test is made of.

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
f60a004cff base-hw scheduler test: rename test.cc main.cc
Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
20fea7fdd2 base-hw scheduler test: adapt to new behavior
This adapts the test to the changes that were applied to the scheduling scheme
by the following commits:

* base-hw scheduler: optimize quota depletion events
* base-hw scheduler: fix bug on removing head
* base-hw scheduler: fix ready method
* base-hw: optimize & cleanup scheduler

Part of that is that the test used to check whether the act of setting a share
ready outdates the head or not. However, with the current version of the
scheduler, this check is not possible anymore. We can merely check whether the
head is outdated after setting the share ready. So, among other adaptions, this
commit adapts the expectations of the test to the new semantics of the check.

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
615dd377dd base-hw scheduler test: clean up
* Get rid of preprocessor macros.
* Introduce Main as class.
* Exit with -1 instead of endless loops on errors.
* Don't try to deal with error conditions, just print a message and exit
  with -1.
* Only one operation per line.

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
0467b4aaf3 base-hw scheduler: optimize quota depletion events
This is an optimization for the case that a prioritized scheduling context
needs slightly more time during a round than granted via quota. If this is the
case, we move the scheduling context to the front of the unprioritized schedule
once its quota gets depleted and thereby at least ensure that it does not have
to wait for all unprioritized scheduling contexts as well before being
scheduled again.

Note that this introduces the possibility of undeserved starvation of
unprioritized scheduling contexts to the scheduling scheme. If there are
enough prioritized contexts that deplete their quota during a round,
they may cover up also the rest of the round with their unprioritized time
slices. If this happens every round, contexts without a priority/quota may
never get a turn. In the previous scheduling scheme, this could not occur as
the unprioritized schedule was completely independent from prioritized
schedules and rounds.

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
f74962bdad base-hw scheduler: fix bug on removing head
The scheduler did not consider the consumed quota during a call to "update"
if the head that consumed the quota was removed from the scheduler. When this
occured, the internal round time did not advance as expected but remained at
its previous value untile the next call to "update" (without a removed head)
This commit introduces a new flag that is set only when the head gets removed
in order to detect and handle the situation correctly on the next call to
"update".

Ref #4151
Ref #4710
2023-01-24 12:07:31 +01:00
Martin Stein
ab298b6337 base-hw scheduler: fix ready method
Setting the _need_to_schedule member in the 'ready' method of the scheduler
was not done correctly. At least, the _need_to_schedule was set true in
situations were the head was not outdated by the 'ready' operation.

Ref #4151
2023-01-24 12:07:31 +01:00
Stefan Kalkowski
1151706243 hw: rename functions of Ipc_node class signature
* Remove *request* in context of: wait, reply, send to shorten it.
* Use ready_to_* instead of can_*, which is regularily used in Genode's APIs
* Replace helping_sink with helping_destination, as destination is more common

Ref genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
fd3c70ec5b hw: mark threads as dead in case of ipc violations
The IPC protcol violations are:

* Sending to an unknown thread (cap)
* Waiting for messages if a reply hasn't happened yet

This silents threads that otherwise repeatedly cause kernel messages
about the violation.

Ref genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
fc690f1c47 hw: re-work the ipc node's internal state machine
* Split the internal state into incoming and outgoing message relations
* Avoid fragmenting of one state like formerly '_state' and '_help'
* Remove pointer to caller, use incoming FIFO instead

This commit fixes at least two bugs that were triggered by tests that
destroy threads in many different states, like run/bomb:

* The '_help' data member was not reset reliable in each situation where a
  helping relationship came to an end. However, when we fixed this bug alone
  in the old state model, the issues remained. The new state model fixes
  this bug as well.

* A thread sometimes referenced an already dead thread as receiver. This caused
  the kernel IPC code to access the vtable of an object that didn't exist any
  longer. Note that the two threads were not in direct IPC relationship while
  the receiver was destroyed, so, there must have been an intermediate node
  between them. Due to the complexity of this problem, we eventually gave up
  pin-pointing the exact reason in the kernel IPC code. The issue disappeared
  with the new state model.

Fix genodelabs/genode#4704
2023-01-24 12:07:30 +01:00
Stefan Kalkowski
08c56e61e1 hw: avoid overhead for cache maintainance
When running on x86, and riscv never enter the kernel for cache maintainance,
but use the dummy implementation of the generic base library instead.

On ARMv8 it is not necessary to enter privileged mode for cache cleaning, and
unification of instruction/data cache, but only for invalidating cache lines
at all levels, which is necessary for the use cases, where this function it
needed (coherency of DMA memory).

Fix genodelabs/genode#4339
2023-01-24 12:07:29 +01:00
Josef Söntgen
66fd027b96 base-hw: introduce 'cache_line_size' call
This call is used to query the cache line size of the underlying CPU.
For now it is only implemented and used by 'arm_v8' platforms.

It does not distinguish between D-/I-cache sizes and always uses the
smallest size. Furthermore it does not account for any discrepancy
in 'big.little' CPUs.

Issue #4339.
2023-01-24 12:07:29 +01:00
Josef Söntgen
e8f748cfed base-hw: unprivileged cache maintenance on ARMv8
Set 'Sctlr_el1::Uci' bit to allow for executing cache clean and
invalidate instruction from user space.

Issue #4339.
2023-01-24 12:07:29 +01:00