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base-hw: export Intel TSC platform information
Export TSC invariant and the frequency reported on Intel processors. Currently lacks TSC calibration and reports a fixed frequency on AMD. Ref #4826
This commit is contained in:
Benjamin Lamowski
Christian Helmuth
parent
c75b07e0fd
commit
312b638220
@ -52,11 +52,15 @@ void Platform::_init_additional_platform_info(Xml_generator &xml)
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xml.attribute("pitch", boot_fb.pitch);
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});
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});
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xml.node("hardware", [&] () {
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xml.node("hardware", [&]() {
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xml.node("features", [&] () {
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xml.attribute("svm", Hw::Virtualization_support::has_svm());
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xml.attribute("vmx", false);
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});
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xml.node("tsc", [&]() {
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xml.attribute("invariant", Hw::Lapic::invariant_tsc());
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xml.attribute("freq_khz", Hw::Lapic::tsc_freq());
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});
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});
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}
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@ -117,6 +117,17 @@ struct Hw::X86_64_cpu
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/* AMD host save physical address */
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X86_64_MSR_REGISTER(Amd_vm_hsavepa, 0xC0010117);
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X86_64_MSR_REGISTER(Platform_id, 0x17,
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struct Bus_ratio : Bitfield<8, 5> { }; /* Bus ratio on Core 2, see SDM 19.7.3 */
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);
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X86_64_MSR_REGISTER(Platform_info, 0xCE,
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struct Ratio : Bitfield< 8, 8> { }; /* Maximum Non-Turbo Ratio (R/O) */
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);
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X86_64_MSR_REGISTER(Fsb_freq, 0xCD,
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struct Speed : Bitfield< 0, 3> { }; /* Scaleable Bus Speed (R/O) */
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);
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X86_64_MSR_REGISTER(Ia32_efer, 0xC0000080,
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struct Svme : Bitfield< 12, 1> { }; /* Secure Virtual Machine Enable */
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@ -129,10 +140,17 @@ struct Hw::X86_64_cpu
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*/
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X86_64_MSR_REGISTER(Ia32_tsc_aux, 0xc0000103);
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X86_64_CPUID_REGISTER(Cpuid_0_eax, 0, eax);
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X86_64_CPUID_REGISTER(Cpuid_0_ebx, 0, ebx);
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X86_64_CPUID_REGISTER(Cpuid_0_ecx, 0, ecx);
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X86_64_CPUID_REGISTER(Cpuid_0_edx, 0, edx);
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X86_64_CPUID_REGISTER(Cpuid_1_eax, 1, eax);
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X86_64_CPUID_REGISTER(Cpuid_1_ecx, 1, ecx,
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struct Tsc_deadline : Bitfield<24, 1> { };
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);
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X86_64_CPUID_REGISTER(Cpuid_1_edx, 1, edx,
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struct Pat : Bitfield<16, 1> { };
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);
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@ -140,10 +158,18 @@ struct Hw::X86_64_cpu
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/* Number of address space identifiers (ASID) */
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X86_64_CPUID_REGISTER(Amd_nasid, 0x8000000A, ebx);
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X86_64_CPUID_REGISTER(Cpuid_15_eax, 15, eax);
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X86_64_CPUID_REGISTER(Cpuid_15_ebx, 15, ebx);
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X86_64_CPUID_REGISTER(Cpuid_15_ecx, 15, ecx);
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X86_64_CPUID_REGISTER(Cpuid_8000000A_edx, 0x8000000A, edx,
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struct Np : Bitfield<0, 1> { }; /* Nested paging */
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);
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X86_64_CPUID_REGISTER(Cpuid_80000007_eax, 0x80000007, eax,
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struct Invariant_tsc : Bitfield<2, 1> { }; /* Invariant TSC */
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);
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X86_64_CPUID_REGISTER(Cpuid_80000001_ecx, 0x80000001, ecx,
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struct Svm : Bitfield<2, 1> { };
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);
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@ -22,6 +22,7 @@ namespace Hw {
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struct Cpu_memory_map;
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struct Virtualization_support;
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class Vendor;
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class Lapic;
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}
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@ -40,7 +41,7 @@ struct Hw::Cpu_memory_map
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}
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};
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struct Hw::Vendor
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class Hw::Vendor
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{
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private:
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static constexpr char const *const vendor_string[] = {
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@ -85,6 +86,165 @@ public:
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return Vendor_id(v);
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}
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static unsigned get_family()
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{
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using Cpu = Hw::X86_64_cpu;
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Cpu::Cpuid_1_eax::access_t eax = Cpu::Cpuid_1_eax::read();
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return ((eax >> 8 & 0xf) + (eax >> 20 & 0xff)) & 0xff;
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}
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static unsigned get_model()
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{
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using Cpu = Hw::X86_64_cpu;
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Cpu::Cpuid_1_eax::access_t eax = Cpu::Cpuid_1_eax::read();
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return ((eax >> 4 & 0xf) + (eax >> 12 & 0xf0)) & 0xff;
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}
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};
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class Hw::Lapic
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{
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private:
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static bool _has_tsc_dl()
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{
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using Cpu = Hw::X86_64_cpu;
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Cpu::Cpuid_1_ecx::access_t ecx = Cpu::Cpuid_1_ecx::read();
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return (bool)Cpu::Cpuid_1_ecx::Tsc_deadline::get(ecx);
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}
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/*
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* Adapted from Christian Prochaska's and Alexander Boettcher's
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* implementation for Nova.
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*
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* For details, see Vol. 3A of the Intel SDM:
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* 19.7.3 Determining the Processor Base Frequency
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*/
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static unsigned _read_tsc_freq()
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{
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using Cpu = Hw::X86_64_cpu;
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unsigned freq_tsc = 0U;
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if (Vendor::get_vendor_id() != Vendor::INTEL)
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return 0;
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unsigned const model = Vendor::get_model();
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unsigned const family = Vendor::get_family();
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enum
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{
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Cpu_id_clock = 0x15
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};
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Cpu::Cpuid_0_eax::access_t eax = Cpu::Cpuid_0_eax::read();
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if (eax >= Cpu_id_clock) {
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Cpu::Cpuid_15_eax::access_t eax = Cpu::Cpuid_15_eax::read();
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Cpu::Cpuid_15_ebx::access_t ebx = Cpu::Cpuid_15_ebx::read();
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Cpu::Cpuid_15_ecx::access_t ecx = Cpu::Cpuid_15_ecx::read();
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if (eax && ebx) {
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if (ecx)
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return static_cast<unsigned>(
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((Genode::uint64_t)(ecx) * ebx) / eax / 1000
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);
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if (family == 6) {
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if (model == 0x5c) /* Goldmont */
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freq_tsc = static_cast<unsigned>((19200ull * ebx) / eax);
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if (model == 0x55) /* Xeon */
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freq_tsc = static_cast<unsigned>((25000ull * ebx) / eax);
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}
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if (!freq_tsc && family >= 6)
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freq_tsc = static_cast<unsigned>((24000ull * ebx) / eax);
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if (freq_tsc)
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return freq_tsc;
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}
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if (family != 6)
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return 0;
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if (model == 0x2a ||
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model == 0x2d || /* Sandy Bridge */
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model >= 0x3a) /* Ivy Bridge and later */
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{
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Cpu::Platform_info::access_t platform_info = Cpu::Platform_info::read();
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Genode::uint64_t ratio = Cpu::Platform_info::Ratio::get(platform_info);
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freq_tsc = static_cast<unsigned>(ratio * 100000);
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} else if (model == 0x1a ||
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model == 0x1e ||
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model == 0x1f ||
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model == 0x2e || /* Nehalem */
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model == 0x25 ||
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model == 0x2c ||
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model == 0x2f) /* Xeon Westmere */
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{
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Cpu::Platform_info::access_t platform_info = Cpu::Platform_info::read();
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Genode::uint64_t ratio = Cpu::Platform_info::Ratio::get(platform_info);
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freq_tsc = static_cast<unsigned>(ratio * 133330);
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} else if (model == 0x17 || model == 0xf) { /* Core 2 */
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Cpu::Fsb_freq::access_t fsb_freq = Cpu::Fsb_freq::read();
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Genode::uint64_t freq_bus = Cpu::Fsb_freq::Speed::get(fsb_freq);
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switch (freq_bus) {
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case 0b101: freq_bus = 100000; break;
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case 0b001: freq_bus = 133330; break;
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case 0b011: freq_bus = 166670; break;
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case 0b010: freq_bus = 200000; break;
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case 0b000: freq_bus = 266670; break;
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case 0b100: freq_bus = 333330; break;
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case 0b110: freq_bus = 400000; break;
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default: freq_bus = 0; break;
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}
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Cpu::Platform_id::access_t platform_id = Cpu::Platform_id::read();
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Genode::uint64_t ratio = Cpu::Platform_id::Bus_ratio::get(platform_id);
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freq_tsc = static_cast<unsigned>(freq_bus * ratio);
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}
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}
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return freq_tsc;
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}
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static unsigned _measure_tsc_freq()
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{
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Genode::warning("TSC calibration not yet implemented, using fixed value");
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/* TODO: implement TSC calibration on AMD */
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return 1000000U;
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}
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public:
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static Genode::uint64_t rdtsc()
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{
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Genode::uint32_t low, high;
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asm volatile("rdtsc" : "=a"(low), "=d"(high));
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return (Genode::uint64_t)(high) << 32 | low;
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}
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static bool invariant_tsc()
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{
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using Cpu = Hw::X86_64_cpu;
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Cpu::Cpuid_80000007_eax::access_t eax =
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Cpu::Cpuid_80000007_eax::read();
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return Cpu::Cpuid_80000007_eax::Invariant_tsc::get(eax);
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}
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static unsigned tsc_freq()
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{
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unsigned freq = _read_tsc_freq();
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if (freq)
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return freq;
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else
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return _measure_tsc_freq();
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}
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};
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struct Hw::Virtualization_support
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