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base-hw: add MSR and CPUID registers for AMD SVM

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Ref #4826
This commit is contained in:
Benjamin Lamowski 2022-10-21 16:34:36 +02:00 committed by Christian Helmuth
parent e11ed069bf
commit 0a819d5e19
1 changed files with 28 additions and 0 deletions
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28
repos/base-hw/src/include/hw/spec/x86_64/cpu.h
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@ -104,10 +104,31 @@ struct Hw::X86_64_cpu
};
);
X86_64_MSR_REGISTER(Amd_vm_syscvg, 0xC0010010,
struct Nested_paging : Bitfield< 0, 1> { }; /* Enable nested paging */
struct Sev : Bitfield< 1, 1> { }; /* Enable Secure Encrypted Virtualization */
struct Enc_state : Bitfield< 2, 1> { }; /* Enable Encrypted State for Secure Encrypted Virtualization */
);
X86_64_MSR_REGISTER(Amd_vm_cr, 0xC0010114,
struct Svmdis : Bitfield< 4, 1> { }; /* SVM disabled */
);
/* AMD host save physical address */
X86_64_MSR_REGISTER(Amd_vm_hsavepa, 0xC0010117);
X86_64_MSR_REGISTER(Ia32_efer, 0xC0000080,
struct Svme : Bitfield< 12, 1> { }; /* Secure Virtual Machine Enable */
);
/*
* Auxiliary TSC register
* For details, see Vol. 3B of the Intel SDM:
* 17.17.2 IA32_TSC_AUX Register and RDTSCP Support
*/
X86_64_MSR_REGISTER(Ia32_tsc_aux, 0xc0000103);
X86_64_CPUID_REGISTER(Cpuid_0_ebx, 0, ebx);
X86_64_CPUID_REGISTER(Cpuid_0_ecx, 0, ecx);
X86_64_CPUID_REGISTER(Cpuid_0_edx, 0, edx);
@ -116,6 +137,13 @@ struct Hw::X86_64_cpu
struct Pat : Bitfield<16, 1> { };
);
/* Number of address space identifiers (ASID) */
X86_64_CPUID_REGISTER(Amd_nasid, 0x8000000A, ebx);
X86_64_CPUID_REGISTER(Cpuid_8000000A_edx, 0x8000000A, edx,
struct Np : Bitfield<0, 1> { }; /* Nested paging */
);
X86_64_CPUID_REGISTER(Cpuid_80000001_ecx, 0x80000001, ecx,
struct Svm : Bitfield<2, 1> { };
);