Commit Graph

1029 Commits

Author SHA1 Message Date
Adrian-Ken Rueegsegger
ded302c61c hw_x86_64: Perform lazy FPU state initialization
Perform lazy-initialization of FPU state when it is enabled for the
first time. This assures that the FXSAVE area (including the stored
MXCSR) is always properly setup and initialized to the platform default
values.
2015-05-20 17:52:59 +02:00
Adrian-Ken Rueegsegger
a0ec317753 hw_x86_64: Explicitly set all FPU-related CR flags
Perform all FPU-related setup in the Cpu class' init_fpu function instead of
the general system bring-up assembly code.

Set all required control register 0 and 4 flags according to Intel SDM Vol. 3A,
sections 9.2 and 9.6 instead of only enabling FPU error reporting and OSFXSR.
2015-05-20 17:52:59 +02:00
Adrian-Ken Rueegsegger
5eb75e9e81 hw_x86_64: Add control register 4 to Cpu class 2015-05-20 17:52:59 +02:00
Adrian-Ken Rueegsegger
fdbb073414 hw_x86_64: Log ip on unknown exception 2015-05-20 17:52:59 +02:00
Adrian-Ken Rueegsegger
4d700fe2ae hw_x86_64: Emit debug message on #UD
Print information when handling an undefined instruction exception.
2015-05-20 17:52:59 +02:00
Adrian-Ken Rueegsegger
370271324e hw_x86_64: Simplify kernel physical init
Merge finish_init_phys_kernel into init_phys_kernel function.
2015-05-20 17:52:58 +02:00
Reto Buerki
bb06826c95 hw_x86_64: Factor out initial PT to separate file
This allows the specification of different initial pagetables for a
platform based on x86_64 (e.g. Muen).
2015-05-20 17:52:58 +02:00
Alexander Boettcher
d998df3b7f base: extend irq session to support MSIs
Works on base-nova and base-foc, the other kernels have no MSI support.

Issue #1216
2015-05-20 17:39:14 +02:00
Martin Stein
7c133add52 hw: acknowledge IRQs via Kernel::ack_irq
In the past, when the user blocked for an IRQ signal, the last signal was
acknowledged automatically thereby unmasking the IRQ. Now, the signal session
got a dedicated RPC for acknowledging IRQs and the HW back-end of that RPC
acknowledged the IRQ signal too. This led to the situation that IRQs were
unmasked twice. However, drivers expect an interrupt to be unmasked only on
the Irq_session::ack_irq and thus IRQ unmasking was moved from
Kernel::ack_signal to a dedicated kernel call.

Fixes #1493
2015-05-06 10:55:23 +02:00
Stefan Kalkowski
e61a3db30d hw: separate function declaration/implementation
Move kernel object functions from its headers to compilation units,
thereby reducing the kernel's text section, cache, and TLB footprint.

Fix #1492
2015-05-06 10:55:23 +02:00
Christian Helmuth
98def2488a thread: move Thread_base::myself() to separate file
The thread library (thread.cc) in base-foc shared 95% of the code with
the generic implementation except myself(). Therefore, its
implementation is now separated from the other generic sources into
myself.cc, which allows base-foc to use a foc-specific primitive to
enable our base libraries in L4Linux.

Issue #1491
2015-05-06 10:55:17 +02:00
Martin Stein
c9272937e7 CPU session: apply quota via relative weightings
Physical CPU quota was previously given to a thread on construction only
by directly specifying a percentage of the quota of the according CPU
session. Now, a new thread is given a weighting that can be any value.
The physical counter-value of such a weighting depends on the weightings
of the other threads at the CPU session. Thus, the physical quota of all
threads of a CPU session must be updated when a weighting is added or
removed. This is each time the session creates or destroys a thread.

This commit also adapts the "cpu_quota" test in base-hw accordingly.

Ref #1464
2015-05-06 10:55:16 +02:00
Martin Stein
955977b516 hw: syscall for changing a threads physical quota
This commit also extends the "cpu_scheduler" test to test the back-end of the
new syscall.

Ref #1464
2015-04-23 16:51:33 +02:00
Martin Stein
e4f560f39b hw: change round-robin scheduling slice to 10 ms
Previously, it was set to 100 ms which caused a remarkable disadvantage
in reactivity.

Ref #1464
2015-04-23 16:51:33 +02:00
Martin Stein
de9d69a6d7 hw: re-enable kernel tests with the new run env
The new run env doesn't pass the "core_type" parameter at one point
which is why we have to pass it through a global HW-specific variable.

Ref #1464
2015-04-23 16:51:33 +02:00
Alexander Boettcher
faa25e1df6 base: make irq_session asynchronous
second step

options: factor out common parts of irq_session_component.cc
options: use on foc arm no proxy threads

Fixes #1456
2015-04-23 16:47:58 +02:00
Alexander Boettcher
e2cbc7c5b3 base: unify some irq_session headers
remove repos/base-*/include/irq_session headers and use only a unification
from   repos/base/include/irq_session

first step

Issue #1456
2015-04-23 16:47:57 +02:00
Norman Feske
eaab23c012 base: const-correctness of Allocator interface
This patch adds const qualifiers to the functions Allocator::consumed,
Allocator::overhead, Allocator::avail, and Range_allocator::valid_addr.

Fixes #1481
2015-04-17 16:13:22 +02:00
Stefan Kalkowski
0188b08f6a hw: construct kernel irq objects on demand
Ref #1443
2015-04-17 16:13:21 +02:00
Stefan Kalkowski
b32af4e0a4 hw: directly reference kernel objects from core
Instead of handing over object ids to the kernel, which has to find them
in object pools then, core can simply use object pointers to reference
kernel objects.

Ref #1443
2015-04-17 16:13:20 +02:00
Stefan Kalkowski
c850462f43 hw: replace kernel's object id allocators
Instead of having an ID allocator per object class use one global allocator for
all. Thereby artificial limitations for the different object types are
superfluent. Moreover, replace the base-hw specific id allocator implementation
with the generic Bit_allocator, which is also memory saving.

Ref #1443
2015-04-17 16:13:20 +02:00
Stefan Kalkowski
2df86cd34b hw: rename bin_* syscalls with delete_*
The verb "bin" in the context of destroying kernel objects seems pretty
unusual in contrast to "delete". When reading "bin" in the context of
systems software an association to something like "binary" is more likely.

Ref #1443
2015-04-17 16:13:20 +02:00
Stefan Kalkowski
b949489641 base: remove local capability from generic base
* Instead of using local capabilities within core's context area implementation
  for stack allocation/attachment, simply do both operations while stack gets
  attached, thereby getting rid of the local capabilities in generic code
* In base-hw the UTCB of core's main thread gets mapped directly instead of
  constructing a dataspace component out of it and hand over its local
  capability
* Remove local capability implementation from all platforms except Linux

Ref #1443
2015-04-17 16:13:20 +02:00
Stefan Kalkowski
a168c9d6ce core: remove global capability id counter
The global capability ID counter is not used by NOVA and Fiasco.OC
and in the future not needed by base-hw too. Thereby, remove the static
counter variable from the generic code base and add it where appropriated.

Ref #1443
2015-04-17 16:13:19 +02:00
Stefan Kalkowski
358380046c base: assign allocator and quota to platform pd
Enable platform specific allocations and ram quota accounting for
protection domains. Needed to allocate object identity references
in the base-hw kernel when delegating capabilities via IPC.
Moreover, it can be used to account translation table entries in the
future.

Ref #1443
2015-04-17 16:13:19 +02:00
Christian Prochaska
0fd53c7fe4 Extract numeric string arguments with the correct signedness
There are lots of places where a numeric argument of an argument string
gets extraced as signed long value and then assigned to an unsigned long
variable. If the value in the string was negative, it would not be
detected as invalid (and replaced by the default value), but become a
positive bogus value.

With this patch, numeric values which are supposed to be unsigned get
extracted with the 'ulong_value()' function, which returns the default
value for negative numbers.

Fixes #1472
2015-04-13 14:18:15 +02:00
Martin Stein
70aa98d837 hw: fix bug in cancellation of 'await_signal'
There were two bugs. First, the caller of Kernel::await_signal wasn't
re-activated for scheduling. Second, the caller did not memorize that he
doesn't wait on a receiver anymore which had bad side effects on further
signal handling.

Fix #1459
2015-04-09 16:04:44 +02:00
Martin Stein
60e392f0c0 hw: support Wandboard Quad (i.MX6)
The port uses the Cortex-A9 private timer for the kernel and an EPIT as
user timer. It was successfully tested on the Wandboard Quad and the CuBox-i
with the signal test. It lacks L2-cache and Trustzone support by now.

Thanks to Praveen Srinivas (IIT Madras, India) and  Nikolay Golikov (Ksys Labs
LLC, Russia). This work is partially based on their contributions.

Fix #1467
2015-04-09 16:04:43 +02:00
Martin Stein
4f887448c3 hw & cortex_a9: clean-up board_support.h
Change class name according to our common naming scheme and remove unnecessary
'using' directive.

Ref #1467
2015-03-27 12:20:07 +01:00
Reto Buerki
c82f5e9269 hw_x86_64: Do not mask edge-triggered interrupts
Do not mask edge-triggered interrupts to avoid losing them while masked,
see Intel 82093AA I/O Advanced Programmable Interrupt Controller
(IOAPIC) specification, section 3.4.2, "Interrupt Mask":

"When this bit is 1, the interrupt signal is masked. Edge-sensitive
interrupts signaled on a masked interrupt pin are ignored (i.e., not
delivered or held pending)"

Or to quote Linus Torvalds on the subject:

"Now, edge-triggered interrupts are a _lot_ harder to mask, because the
Intel APIC is an unbelievable piece of sh*t, and has the edge-detect
logic _before_ the mask logic, so if a edge happens _while_ the device
is masked, you'll never ever see the edge ever again (unmasking will not
cause a new edge, so you simply lost the interrupt)."

So when you "mask" an edge-triggered IRQ, you can't really mask it at
all, because if you did that, you'd lose it forever if the IRQ comes in
while you masked it. Instead, we're supposed to leave it active, and set
a flag, and IF the IRQ comes in, we just remember it, and mask it at
that point instead, and then on unmasking, we have to replay it by
sending a self-IPI." [1]

[1] - http://yarchive.net/comp/linux/edge_triggered_interrupts.html

Ref #1448
2015-03-27 11:53:34 +01:00
Martin Stein
bfe1fac37c hw_x86_64: style fixes
Ref #1448
2015-03-27 11:53:34 +01:00
Adrian-Ken Rueegsegger
f4cb9101a4 hw: Fix format string for 64 bit platforms
Use the format specifier of the largest possible type and cast the value
to the chosen type. This avoids compiler warnings on x86_64.
2015-03-27 11:53:33 +01:00
Reto Buerki
92efc13a17 hw_x86_64: Add x86-specific IRQ session component
In order to match the I/O APIC configuration, a request for user timer
IRQ 0 is remapped to vector 50 (Board::TIMER_VECTOR_USER), all other
requests are transposed by adding the vector offset 48
(Board::VECTOR_REMAP_BASE).
2015-03-27 11:53:33 +01:00
Adrian-Ken Rueegsegger
f9f74d2930 hw_x86_64: Add VESA resources to x86 MMIO regions
The additional MMIO regions are necessary for emulated graphics devices
of QEMU and Bochs.
2015-03-27 11:53:33 +01:00
Adrian-Ken Rueegsegger
8b8e8c8270 hw_x86_64: Add various drivers to x86
Include PCI, PS2, VESA and Framebuffer drivers on x86_64 platform.
2015-03-27 11:53:33 +01:00
Adrian-Ken Rueegsegger
96a3eabe16 hw_x86_64: Log additional information on unknown exception
Provide more information in the log message when an unknown exception
occurs.
2015-03-27 11:53:32 +01:00
Adrian-Ken Rueegsegger
544148bc24 hw_x86_64: Add I/O port allocator to platform
Add the entire I/O port range to the I/O port allocator on x86. Do nothing
on ARM platforms since there are no I/O port resources.
2015-03-27 11:53:32 +01:00
Reto Buerki
5765398741 hw_x86_64: Add x86 platform services to core
Use the x86-specific platform_services.cc file and register the I/O port
session component.
2015-03-27 11:53:32 +01:00
Reto Buerki
28b5e67a8c Update or add hw_x86_64 copyright headers 2015-03-27 11:53:32 +01:00
Adrian-Ken Rueegsegger
ace61c54d6 hw_x86_64: Zero-fill BSS segment in x86_64 crt0.s
Make sure all content of the BSS segment is initialized to zero.
2015-03-27 11:53:32 +01:00
Reto Buerki
69a58c4bd5 hw_x86_64: Set EFLAGS IF, IOPL bits in Cpu::init_thread
Enable interrupts for all threads, set I/O privilege level (IOPL) to 3
for core threads to allow UART access.
2015-03-27 11:53:32 +01:00
Adrian-Ken Rueegsegger
7ce8464b3a hw_x86_64: Enable FPU support
* Enable the use of the FXSAVE and FXRSTOR instructions, see Intel SDM
  Vol. 3C, section 2.5.
* The state of the x87 floating point unit (FPU) is loaded and saved on
  demand.
* Make the cr0 control register accessible in the Cpu class. This is in
  preparation of the upcoming FPU management.
* Access to the FPU is disabled by setting the Task Switch flag in the cr0
  register.
* Access to the FPU is enabled by clearing the Task Switch flag in the cr0
  register.
* Implement FPU initialization
* Add is_fpu_enabled helper function
* Add pointer to CPU lazy state to CPU class
* Init FPU when finishing kernel initialization
* Add function to retry FPU instruction:
    Similar to the ARM mechanism to retry undefined instructions, implement a
    function for retrying an FPU instruction. If a floating-point instruction
    causes an #NM exception due to the FPU being disabled, it can be retried
    after the correct FPU state is restored, saving the current state and
    enabling the FPU in the process.
* Disable FPU when switching to different user context:
    This enables lazy save/restore of the FPU since trying to execute a
    floating point instruction when the FPU is disabled will cause a #NM
    exception.
* Declare constant for #NM exception
* Retry FPU instruction on #NM exception
* Assure alignment of FXSAVE area:
    The FXSAVE area is 512-byte memory region that must be 16-byte aligned. As
    it turns out the alignment attribute is not honored in all cases so add a
    workaround to assure the alignment constraint is met by manually rounding
    the start of the FXSAVE area to the next 16-byte boundary if necessary.
2015-03-27 11:53:31 +01:00
Reto Buerki
c14898703d hw_x86_64: Implement Cpu_idle::exception function
Forward external interrupts during the CPU idle thread to the
_interrupt function.
2015-03-27 11:53:31 +01:00
Reto Buerki
c9c84dd751 base: Move Cpu_exception enum to x86_64 cpu_state.h 2015-03-27 11:53:31 +01:00
Reto Buerki
4e259f7b1e hw_x86_64: Implement LAPIC-based kernel timer
The LAPIC timer is programmed in one-shot mode with vector 32
(Board::TIMER_VECTOR_KERNEL). The timer frequency is measured using PIT
channel 2 as reference (50ms delay).

Disable PIT timer channel 0 since BIOS programs it to fire periodically.
This avoids potential spurious timer interrupts.
2015-03-27 11:53:31 +01:00
Reto Buerki
a21959fc26 hw_x86_64: Implement APIC-based PIC driver
The implementation initializes the Local APIC (LAPIC) of CPU 0 in xapic
mode (mmio register access) and uses the I/O APIC to remap, mask and
unmask hardware IRQs. The remapping offset of IRQs is 48.

Also initialize the legacy PIC and mask all interrupts in order to
disable it.

For more information about LAPIC and I/O APIC see Intel SDM Vol. 3A,
chapter 10 and the Intel 82093AA I/O Advanced Programmable Interrupt
Controller (IOAPIC) specification

Set bit 9 in the RFLAGS register of user CPU context to enable
interrupts on kernel- to usermode switch.
2015-03-27 11:53:31 +01:00
Reto Buerki
557c96a9cb hw_x86_64: Add APIC MMIO to native regions 2015-03-27 11:53:30 +01:00
Reto Buerki
cf100f96af hw_x86_64: Add x86-specific board.h file
The file specifies constants for the LAPIC, I/O APIC MMIO regions plus
the interrupt remapping offset and timer vectors.
2015-03-27 11:53:30 +01:00
Adrian-Ken Rueegsegger
42987a7b2f hw_x86_64: Add mapping for I/O APIC MMIO to initial pt
Make the I/O APIC accessible via its MMIO region by adding a 2 MB large
page mapping at 0xfec00000 with memory type UC.
2015-03-27 11:53:30 +01:00
Adrian-Ken Rueegsegger
c06c21e472 hw_x86_64: Add mapping for APIC MMIO to initial pt
Make the local APIC accessible via its MMIO region by adding a 2 MB
large page mapping at 0xfee00000 with memory type UC.

Note: The mapping is added to the initial page tables to make the APIC
      usable prior to the activation of core's page tables, e.g. in the
      constructor of the timer class.
2015-03-27 11:53:30 +01:00
Reto Buerki
b75b1902f2 hw_x86_64: Provide inb and outb functions for port I/O
The port_io.h file provides the inb and outb functions to perform port
I/O operations.
2015-03-27 11:53:30 +01:00
Reto Buerki
1b3871a3f0 hw_x86_64: Move exception_entry to 0xffff0000
The location in memory is arbitrary but we use the same address as the
ARM architecture. Adjust references to virtual addresses in the mode
transition pages to cope with 64-bit values.
2015-03-27 11:53:30 +01:00
Reto Buerki
147b1ec2b1 hw_x86_64: Adjust parameter type of Message_tpl::prepare_send
Change the type of the local name parameter from unsigned to unsigned
long. Otherwise only 4 bytes are copied on x86_64, leaving 4 bytes of
garbage.
2015-03-27 11:53:29 +01:00
Reto Buerki
16a51b317a hw_x86_64: Implement Cpu_idle::Cpu_idle function
The function is a copy of the ARM version.
2015-03-27 11:53:29 +01:00
Reto Buerki
2ecdf4f729 hw_x86_64: Forward interrupts to _interrupt function
Extend the Thread::exception function to forward external interrupts to
the _interrupt function for processing.
2015-03-27 11:53:29 +01:00
Reto Buerki
d0024e1893 hw_x86_64: Fill _fault_addr from cr2 in _mmu_exception
Use the Cpu::Cr2 register to read the linear page fault address in the
Thread::_mmu_exception function.
2015-03-27 11:53:29 +01:00
Reto Buerki
d553d38ecf hw_x86_64: Model cr2 register in CPU state
Make the cr2 control register accessible in the Cpu class. The register
is needed to retrieve the linear address that caused a page fault.
2015-03-27 11:53:29 +01:00
Reto Buerki
466ad3aed4 hw_x86_64: Implement Thread::_mmu_exception() for x86_64
The function is a copy of the ARM version minus the in_fault
distinction.
2015-03-27 11:53:29 +01:00
Reto Buerki
0992c233bd hw_x86_64: Forward page faults to the _mmu_exception function 2015-03-27 11:53:28 +01:00
Reto Buerki
112ff2609a hw_x86_64: Add Thread::_event implementation
It is an exact copy of the ARM version.
2015-03-27 11:53:28 +01:00
Reto Buerki
83a1b826a3 hw_x86_64: Add supervisor call handling to Thread::exception
Forward supervisor calls to the Thread::_call function for dispatching.
2015-03-27 11:53:28 +01:00
Reto Buerki
0568dcc875 hw_x86_64: Implement Thread::_reg function 2015-03-27 11:53:28 +01:00
Reto Buerki
e5be376f57 hw_x86_64: Declare Thread_reg_id enum for x86_64
Only define IDs of registers which are actually accessed by threads.
2015-03-27 11:53:28 +01:00
Reto Buerki
472c3b6502 hw_x86_64: Use mtc relative addressing for master context 2015-03-27 11:53:28 +01:00
Reto Buerki
080d7d5f8b hw_x86_64: Use mtc relative addressing for _mt_buffer in crt0.s
Until the kernel page tables are active, labels can't be used directly
because the associated pages are not mapped for non-core threads.
2015-03-27 11:53:28 +01:00
Reto Buerki
09c90e5751 hw_x86_64: Set interrupt stack in Tss::Setup 2015-03-27 11:53:27 +01:00
Reto Buerki
9af9dcc02c hw_x86_64: Reserve space for interrupt stack in mtc region
The interrupt stack must reside in the mtc region in order to use it for
non-core threads. The size of the stack is set to 56 bytes in order to
hold the interrupt stack frame plus the additional vector number that is
pushed onto the stack by the ISR.
2015-03-27 11:53:27 +01:00
Reto Buerki
9c44d32dd9 hw_x86_64: Add virt_base paramater to Tss::setup function
The stack pointers (RSP) for privilege levels 0-2 must be setup using an
address in the mtc region to make stack switching work for non-core
threads.
2015-03-27 11:53:27 +01:00
Reto Buerki
15d131b723 hw_x86_64: Use _virt_mtc_addr to calculate ISR base
Call the _virt_mtc_addr function with the _mt_isrs label to calculate
the ISR base address in Idt::setup. Again, assume the address to be
below 0x10000.
2015-03-27 11:53:27 +01:00
Reto Buerki
a5efe04656 hw_x86_64: Add virt_base paramater to Idt::setup function
Use parameter instead of class member variable because it would get
stored into the mtc region otherwise. In a further iteration only the
actual IDT should be saved into the mtc, not the complete class
instance. Currently the class instance size is equal to the IDT table
size.
2015-03-27 11:53:27 +01:00
Reto Buerki
1102b2b562 hw_x86_64: Calculate limit using _mt_gdt_end in Gdt::load 2015-03-27 11:53:27 +01:00
Reto Buerki
6f5ea78a51 hw_x86_64: Prefix gdt labels with _mt
Streamline the naming by prepending the _mt prefix to the gdt labels.
2015-03-27 11:53:26 +01:00
Reto Buerki
69e820e4e3 hw_x86_64: Reload GDTR in Genode::Cpu::init_thread
The GDT reload must happen after the page tables mapping the mtc region
is active, that's why it cannot be done in the Genode::Cpu ctor.
2015-03-27 11:53:26 +01:00
Reto Buerki
968ab15bbb hw_x86_64: Add Genode::Gdt class
The class provides the load() function which reloads the GDTR with the
GDT address in the mtc region. This is needed to make the segments
accessible to non-core threads.

Make the _gdt_start label global to use it in the call to
_virt_mtc_addr().
2015-03-27 11:53:26 +01:00
Reto Buerki
251b270e4b hw_x86_64: Factor out _virt_mtc_addr to mtc_util.h header 2015-03-27 11:53:26 +01:00
Reto Buerki
cfe89996e8 hw_x86_64: Factor out pseudo descriptor class to own header 2015-03-27 11:53:26 +01:00
Reto Buerki
d0f14cb941 hw_x86_64: Use _mt_tss and _mt_begin labels to set TSS base
The TSS descriptor base address is assumed to be below the 0x10000 mark
(only bits 0-15 used) for now.
2015-03-27 11:53:26 +01:00
Reto Buerki
00921e4a5c hw_x86_64: Create Tss instance in mtc region
Use the _mt_tss label and the placement new operator to create the
Tss class instance in the mtc region. Update the hard-coded
TSS base address to use the virtual mtc address.
2015-03-27 11:53:25 +01:00
Reto Buerki
b9fe4a8d48 hw_x86_64: Reserve space for TSS in mtc region 2015-03-27 11:53:25 +01:00
Reto Buerki
34a25d3160 hw_x86_64: Make Tss member functions non-static
Add appropriate Tss object to Genode::Cpu class.
2015-03-27 11:53:25 +01:00
Reto Buerki
ec028ea06f hw_x86_64: Move GDT into mtc region
The GDT must be visible for non-core threads too.
2015-03-27 11:53:25 +01:00
Reto Buerki
bf5118fe54 hw_x86_64: Make _virt_idt_addr member more generic
Add label argument to function and rename it to _virt_mtc_addr. It can
be used to retrieve the virtual mtc address of any given label.
2015-03-27 11:53:25 +01:00
Reto Buerki
b8e2249f51 hw_x86_64: Use _virt_idt_addr member in Idt::load
Load the virtual address in the mode transition pages into Interrupt
Descriptor Table Register (IDTR).
2015-03-27 11:53:25 +01:00
Reto Buerki
9c2d071654 hw_x86_64: Add virt_base argument to Idt::load
The argument specifies the virtual base address of the mode transition
pages.
2015-03-27 11:53:24 +01:00
Reto Buerki
ecaad9ecce hw_x86_64: Add private _virt_idt_address member to Idt class
This function calculates the address of the IDT for a given virtual
mode transition base address.
2015-03-27 11:53:24 +01:00
Reto Buerki
89add00518 hw_x86_64: Create Idt instance in mtc region
Use the _mt_idt label and the placement new operator to create the Idt
instance in the mtc region.
2015-03-27 11:53:24 +01:00
Reto Buerki
9c8109c276 hw_x86_64: Reserve space for IDT on mode transition pages
On exception, the CPU first checks the IDT in order to find the
associated ISR. The IDT must therefore be placed in the mode transition
pages to make them available for non-core threads.
2015-03-27 11:53:24 +01:00
Reto Buerki
d8a10448bb hw_x86_64: Make Idt member functions non-static
Add appropriate Idt object to Genode::Cpu class. Update the hard-coded
TSS base address.
2015-03-27 11:53:24 +01:00
Reto Buerki
e3332c6c53 hw_x86_64: Drop obsolete isr.s assembly file 2015-03-27 11:53:24 +01:00
Reto Buerki
a361fbd2bc hw_x86_64: Move ISR entries to mode transition page
This is needed to make them available for non-core threads which
initially only have the mode transition page mapped.
2015-03-27 11:53:23 +01:00
Reto Buerki
d1a4eaed0d hw_x86_64: Add fake Timer::ms_to_tics implementation
This makes the scheduler happy and it starts scheduling threads.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger
4946f21302 hw_x86_64: Set base address and limit of TSS descriptor
The limit is set to match the TSS size - 1 and the base address is
hardcoded to the *current* address of the TSS instance (0x3a1100).

TODO: Set the base address using the 'tss' label. If the TSS descriptor
      format were not so utterly unusable this would be straightforward.
      Changes to the code that indirectly lead to a different location
      of the tss result in #GP since the base address will be invalid.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger
58e5f9b2fe hw_x86_64: Jump to actual kernel entry on interrupt 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger
9f825ffb17 hw_x86_64: Setup and load Task State Segment 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger
2af5aaa54d hw_x86_64: Add Tss class
The class Genode::Tss represents a 64-bit Task State Segment (TSS) as
specified by Intel SDM Vol. 3A, section 7.7.

The setup function sets the stack pointers for privilege levels 0-2 to
the kernel stack address. The load function loads the TSS segment
selector into the task register.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger
793b5264e3 hw_x86_64: Set dpl of syscall IDT entry to 3
Since this IDT entry is called from usermode the descriptor privilege
level must be 3.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
ed06c46233 hw_x86_64: Specify user argument to register mapping
Implement user argument setter and getter support functions. The mapping of
the state registers corresponds to the system call parameter passing
convention.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
16a15237a4 hw_x86_64: Continue execution of the kernel
The instruction pointer is the first field of the master context and can
directly be used as a jump argument, which avoids additional register
copy operations.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
ecfb954eb9 hw_x86_64: Restore kernel stack pointer 2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
c62b4ea36a hw_x86_64: Restore kernel register values from master context
Set stack pointer to master context and restore kernel register by popping
the values from the master context.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
7b051c0531 hw_x86_64: Restore kernel segment registers
The segment registers are set to reference the kernel data segments of
the GDT.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger
fb5946b69c hw_x86_64: Save client register values to context
Point stack to client context region and save registers using push
instructions.

Note that since the push instruction first increments the stack pointer
and then stores the value on the stack, the RSP has to point one field
past RBP before pushing the first register value.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
1035efcf3f hw_x86_64: Save info on interrupt stack to client context
As the kernel entry is called from the interrupt handler the stack
layout is as specified by Intel SDM Vol. 3A, figure 6-8. An additional
vector number is stored at the top of the stack.

Gather the necessary client information from the interrupt stack frame
and store it in the client context.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
3d782282db hw_x86_64: Switch to kernel page tables
After switching to the kernel address space the client context region is
accessible to store the client register values.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
16496af371 hw_x86_64: Create temporary copy of client RAX in kernel entry
Copy client context RAX value to buffer to enable use of RAX as scratch
register.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
43bd925c7f hw_x86_64: Add offset constant for Cpu_state.trapno field 2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
408cec32f5 base: Add errcode to x86_64 Cpu_state
The new errcode field is used to store the error code that some
interrupts provide (e.g. #PF). Rework mode transition reserved space and
offset constants to match the new CPU_state layout.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger
1d762ca254 hw_x86_64: Implement syscall with one to six arguments 2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
04ad1340d5 hw_x86_64: Add syscall helper macros
The macros are used to assign syscall arguments to specific registers.
Using the AMD64 parameter passing convention avoids additional copying of
variables since the C++ function parameters are already in the right
registers.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
3e779e3ca1 hw_x86_64: Perform the user entry mode transition
The interrupt return instruction in IA-32e mode applies the prepared
interrupt stack frame to set the RFLAGS, CS and SS segment as well as
the RIP and RSP registers. It then continues execution of the user code.

For detailed information refer to Intel SDM Vol. 3A, section 6.14.3.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
ab9d7afa45 hw_x86_64: Finally restore RAX client register value
Set the stack to the mode transition buffer and pop the temporary copy
of the RAX client value into the register.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
1fc867f1d7 hw_x86_64: Switch to client page tables
After activating the client page tables the client context cannot be
accessed any longer. The mode transition buffer however is globally
mapped and can be used to restore the remaining register values.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
172dec209b hw_x86_64: Restore registers to client context values
Set the stack pointer to the R8 field in the client context to enable
restoring registers by popping values of the stack.

After this step the only remaining registers that do not contain client
values are RAX, RSP and RIP.

Note that the client value of RAX is pop'd to the global buffer region as
the register will still be used by subsequent steps. It will be restored to
the value in the buffer area just prior to resuming client code execution.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger
60e799f7b4 hw_x86_64: Set segment registers prior to mode transition
The registers for the ds, es, fs and gs segments are hardcoded to GDT
index 4 with requested privilege level set to 3.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
fe22858550 hw_x86_64: Adjust EFLAGS of prepared interrupt stack frame
Set I/O privilege level to 3 to allow core to perform port I/O from
userspace. Also make sure the IF flag is cleared for now until interrupt
handling is implemented.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
40862a81eb hw_x86_64: Prepare interrupt stack frame in mode transition buffer
Setup an IA-32e interrupt stack frame in the mode transition buffer region.
It will be used to perform the mode switch to userspace using the iret
instruction.

For detailed information about the IA-32e interrupt stack frame refer to
Intel SDM Vol. 3A, figure 6-8.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
4b7a5ced3b hw_x86_64: Declare CPU context offset constants
The constants specify offset values of CPU context member variables as
specified by Genode::Cpu_state [1] and Genode::Cpu::Context [2].

[1] - repos/base/include/x86_64/cpu/cpu_state.h
[2] - repos/base-hw/src/core/include/spec/x86/cpu.h
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
e3f10b5ce2 hw_x86_64: Reserve space for mode transition buffer
Since the buffer stores an IA-32e interrupt stack frame, its size must
be 6 * 8 bytes.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
03929b3cc9 hw_x86_64: Add 64-bit user code and data segments to GDT
The new entries specify a 64-bit code segment with DPL 3 at index 3 and a
64-bit data segment with DPL 3 at index 4.

These segments are needed for transitioning to user mode.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger
51d515c77f hw_x86_64: Explicitly set up segment selectors during boot 2015-03-27 11:53:18 +01:00
Adrian-Ken Rueegsegger
65de09c7a6 hw_x86_64: Reserve space for client context pointer
A pointer to the client context is placed in the mt_client_context_ptr area.
It is used to pass the current client context to the lowlevel mode-switching
assembly code.
2015-03-27 11:53:18 +01:00
Adrian-Ken Rueegsegger
4417fe6201 hw_x86_64: Implementation of IA-32e paging
IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses. Translation structures are hierarchical and four levels deep.
The current implementation supports regular 4KB and 1 GB and 2 MB large
page mappings.

Memory typing is not yet implemented since the encoded type bits depend
on the active page attribute table (PAT)*.

For detailed information refer to Intel SDM Vol. 3A, section 4.5.

* The default PAT after power up does not allow the encoding of the
  write-combining memory type, see Intel SDM Vol. 3A, section 11.12.4.
* Add common IA-32e paging descriptor type:
    The type represents a table entry and encompasses all fields shared by
    paging structure entries of all four levels (PML4, PDPT, PD and PT).
* Simplify PT entry type by using common descriptor:
    Differing fields are the physical address, the global flag and the memory
    type flags.
* Simplify directory entry type by using common descriptor:
    Page directory entries (PDPT and PD) have an additional 'page size' field
    that specifies if the entry references a next level paging structure or
    represents a large page mapping.
* Simplify PML4 entry type by using common descriptor
    Top-level paging structure entries (PML4) do not have a 'pat' flag and the
    memory type is specified by the 'pwt' and 'pcd' fields only.
* Implement access right merging for directory paging entries
    The access rights for translations are determined by the U/S, R/W and XD
    flags. Paging structure entries that reference other tables must provide
    the superset of rights required for all entries of the referenced table.
    Thus merge access rights of new mappings into existing directory entries to
    grant additional rights if needed.
* Add cr3 register definition:
    The control register 3 is used to set the current page-directory base
    register.
* Add cr3 variable to x86_64 Cpu Context
    The variable designates the address of the top-level paging structure.
* Return current cr3 value as translation table base
* Set context cr3 value on translation table assignment
* Implement switch to virtual mode in kernel
    Activate translation table in init_virt_kernel function by updating the
    cr3 register.
* Ignore accessed and dirty flags when comparing existing table entries
    These flags can be set by the MMU and must be disregarded.
2015-03-27 11:53:18 +01:00
Reto Buerki
c7cadf52a6 hw_x86_64: setup ISR and IDT
* Add isr.s assembler file:
    The file declares an array of Interrupt Service Routines (ISR) to handle
    the exception vectors from 0 to 19, see Intel SDM Vol. 3A, section
    6.3.1.
* Add Idt class:
  * The class Genode::Idt represents an Interrupt Descriptor Table as
    specified by Intel SDM Vol. 3A, section 6.10.
  * The setup function initializes the IDT with 20 entries using the ISR
    array defined in the isr.s assembly file.
* Setup and load IDT in Genode::Cpu ctor:
    The Idt::setup function is only executed once on the BSP.
* Declare ISRs for interrupts 20-255
* Set IDT size to 256
2015-03-27 11:53:18 +01:00
Reto Buerki
6e0f1a4466 hw_x86_64: Adjust size of _mt_master_context
The CPU state in IA-32e mode consists of 20 64-bit registers.
2015-03-27 11:53:18 +01:00
Reto Buerki
0f624cdde7 hw_x86_64: Perform indirect long jump to 64-bit code 2015-03-27 11:53:18 +01:00
Reto Buerki
15d0e86592 hw_x86_64: Load Global Descriptor Table register 2015-03-27 11:53:17 +01:00
Reto Buerki
27191b17ce hw_x86_64: Declare Global Descriptor Table (GDT) in .data
The table specifies a 64-bit code segment descriptor at index 1, a
64-bit data segment descriptor at index 2 and a task segment descriptor
at index 3.
2015-03-27 11:53:17 +01:00
Reto Buerki
59bba7624f hw_x86_64: Set system control flags of cr0 register
Enable paging, write protection, caching and native FPU error reporting,
see Intel SDM Vol. 3A, section 2.5.
2015-03-27 11:53:17 +01:00
Reto Buerki
032fc3b190 hw_x86_64: Enable IA-32e mode and execute-disable
Set bits 8 (LME) and 11 (NXE) in the IA32_EFER MSR to enable IA-32e mode
and execute-disable.
2015-03-27 11:53:17 +01:00
Reto Buerki
d23cd7e5ff hw_x86_64: Load initial pagetable address into cr3 2015-03-27 11:53:17 +01:00
Reto Buerki
bafb893a70 hw_x86_64: Declare initial pagetables in .data segment
The table specifies the initial identity mapping for the memory region
from 2 MiB to 4 MiB using one 2 MiB mapping.
2015-03-27 11:53:17 +01:00
Reto Buerki
be430b9648 hw_x86_64: Enable Physical Address Extension (PAE)
This is a prerequisite for IA-32e mode.
2015-03-27 11:53:16 +01:00
Adrian-Ken Rueegsegger
3ad0f06b06 hw: Drop unnecessary include in pd.h 2015-03-27 11:53:16 +01:00
Norman Feske
a974726e26 hw: skeleton for building on x86_64
This patch contains the initial code needed to build and bootstrap the
base-hw kernel on x86 64-bit platforms. It gets stuck earlier
because the binary contains 64-bit instructions, but it is started in
32-bit mode. The initial setup of page tables and switch to long mode is
still missing from the crt0 code.
2015-03-27 11:53:16 +01:00
Stefan Kalkowski
381711dbea hw: extend warning messages to ease debugging
To ease debugging without the need to tweak the kernel every time, and to
support userland developers with useful information this commit extends several
warnings and errors printed by the kernel/core by which thread/application
caused the problem, and what exactly failed.

Fix #1382
Fix #1406
2015-03-27 11:53:13 +01:00
Martin Stein
ff6595f150 hw: enable destruction of IRQ sessions
Implement the missing Irq_session_component destructor.

Fix #1460
2015-03-27 11:53:13 +01:00
Alexander Boettcher
1f8fad8fa1 base: refactor signal_transmitter::submit
Move it to platform specific .cc file, so that it may get re-implemented
platform specifically if needed.

Issue #1446
2015-03-19 09:32:52 +01:00
Martin Stein
d312f840bd hw: error message on unmap on broken RM clients
In the past, unmap sometimes occured on RM clients that have no thread,
PD, or translation table assigned. However, this shouldn't be the
case anymore.

Fixes #504
2015-03-19 08:57:20 +01:00
Stefan Kalkowski
657646e76e hw: adjust core bootstrap to fit generic process
* Introduce hw-specific crt0 for core that calls e.g.: init_main_thread
* re-map core's main thread UTCB to fit the right context area location
* switch core's main thread's stack to fit the right context area location

Fix #1440
2015-03-19 08:57:19 +01:00
Reto Buerki
ebfe3d8ff0 hw: Use mtc_size from Cpu class for mtc::SIZE
This decouples the size of the mode transition control region from the
minimal mapping size of the page tables implementation. Rather, the CPU
architecture is able to specify the actual size.

Rationale: For x86_64, we need the mtc region to span two pages in order
to store all the tables required to perform the mode switch.
2015-03-13 12:17:28 +01:00
Reto Buerki
32521cfd71 hw: Declare mtc_size constant in arm/cpu_support.h
This constant specifies the size of the mode transition control region.
2015-03-13 12:17:28 +01:00
Martin Stein
9737b5d966 tz_vmm: support USB-Armory board
For the USB-Armory, we use a newer version of Linux (3.18) as for the
i.MX53-QSB. The main difference is, that the newer Linux uses a DTB instead of
ATAGs.

Fixes #1422
2015-02-27 11:48:35 +01:00
Martin Stein
be392b3bf9 hw: support USB-Armory board
The USB Armory is almost the same as the i.MX53-QSB but it uses only
one of the two RAM banks available in i.MX53. Furthermore we use the USB
Armory only with Trustzone enabled.

Ref #1422
2015-02-27 11:48:35 +01:00
Stefan Kalkowski
7582396e9c hw_arndale: enable ARM virtualization extensions
* enables world-switch using ARM virtualization extensions
* split TrustZone and virtualization extensions hardly from platforms,
  where it is not used
* extend 'Vm_session' interface to enable configuration of guest-physical memory
* introduce VM destruction syscall
* add virtual machine monitor for hw_arndale that emulates a simplified version
  of ARM's Versatile Express Cortex A15 board for a Linux guest OS

Fixes #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
07c8d1652e hw_arndale: setup ARM hypervisor mode
To enable support of hardware virtualization for ARM on the Arndale board,
the cpu needs to be prepared to enter the non-secure mode, as long as it does
not already run in it. Therefore, especially the interrupt controller and
some TrustZone specific system registers need to be prepared. Moreover,
the exception vector for the hypervisor needs to be set up properly, before
booting normally in the supervisor mode of the non-secure world.

Ref #1405
2015-02-27 11:48:05 +01:00
Stefan Kalkowski
8e2b4d6f45 hw: extend kernel interrupt class
The generalization of interrupt objects in the kernel and the use of
C++ polymorphism instead of explicitely checking for special interrupts
within generic code (Cpu_job::_interrupt) enables the registration of
additional interrupts used by the kernel, which are needed for specific
aspects added to the kernel, like ARM hardware virtualization interrupts.

* Introduce generic base class for interrupt objects handled by the kernel
* Derive an interrupt class for those handled by the user-land
* Implement IPI-specific interrupt class
* Implement timer interrupts using the new generic base class

Ref #1405
2015-02-27 11:43:56 +01:00
Stefan Kalkowski
0836726df2 hw: use one IRQ for all cpus to send IPIs
Until now, one distinct software generated IRQ per cpu was used to
send signals between cpus. As ARM's GIC has 16 software generated
IRQs only, and they need to be partitioned between secure/non-secure
TrustZone world as well as virtual and non-virtual worlds, we should
save them.

Ref #1405
2015-02-27 11:43:56 +01:00
Stefan Kalkowski
a40932a324 hw: refactor irq controllers
* name irq controller memory mapped I/O regions consistently
  in board descriptions
* move irq controller and timer memory mapped I/O region descriptions
  from cpu class to board class
* eliminate artificial distinction between flavors of ARM's GIC
* factor cpu local initialization out of ARM's GIC interface description,
  which is needed if the GIC is initialized differently e.g. for TrustZone

Ref #1405
2015-02-27 11:43:56 +01:00
Martin Stein
3a40c27c26 hw_vea9x4: quickfix slow RAM access
Setting the ACTLR.SMP bit also without SMP support fastens RAM access
significantly. A proper solution would implement SMP support which must enable
the bit anyway.

Fixes #1353
2015-02-17 14:18:16 +01:00
Alexander Boettcher
95ff5ba11d base: support range restriction in allocator
Issue #696
2015-02-16 13:40:38 +01:00
Stefan Kalkowski
322be1b4fb hw: LPAE for Cortex a15 (fix #1387) 2015-02-16 13:40:37 +01:00
Stefan Kalkowski
21fd2fc582 hw: introduce ARM LPAE extension (ref #1387)
This patch adds support for the Large Physical Address Space Extension
for ARM v7.
2015-02-16 13:40:37 +01:00
Stefan Kalkowski
102444b82b hw: remove pointless, wasted memory in pd object
(ref #1387)
2015-02-16 13:40:37 +01:00
Stefan Kalkowski
34f169293f hw: fix page table handling of core (ref #1387)
There might be more then one nested slab allocation.
2015-02-16 13:40:37 +01:00
Martin Stein
5dea0b40aa hw: don't use ARM CPU-state stuff in generic code
Fixes #1404
2015-02-16 13:40:36 +01:00
Martin Stein
63f8a38b5a hw: default boot-modules vpath is generic
Ref #1404
2015-02-16 13:40:36 +01:00
Norman Feske
cb579ec8d7 hw: minor 64-bit fixes 2015-02-16 13:40:36 +01:00
Stefan Kalkowski
a3abf74d1e hw: remove code duplication related to Exynos5 SoC
Fixes #1396
2015-02-16 13:40:36 +01:00
Josef Söntgen
c706b1c0a7 run: modularize run tool 2015-01-26 12:28:40 +01:00
Stefan Kalkowski
901bff813d imx31: remove platform completely (fix #1360) 2015-01-12 14:24:15 +01:00
Martin Stein
9a4a0448be hw vea9x4: remove trustzone support
When building Genode for VEA9X4 as micro-hypervisor protected by the ARM
TrustZone hardware we ran into limitations regarding our basic daily
testing routines. The most significant is that, when speaking about RAM
partitioning, the only available options are to configure the whole SRAM
to be secure and the whole DDR-RAM to be non-secure or vice versa. The
SRAM however provides only 32 MB which isn't enough for both a
representative non-secure guest OS or a secure Genode that is still
capable of passing our basic tests. This initiated our decision to
remove the VEA9X4 TrustZone-support.

Fixes #1351
2015-01-08 13:28:42 +01:00
Martin Stein
be7d5b4827 hw: use context-area base that is ok for VEA9X4-TZ
On VEA9X4-TZ, the context-area overlaps with the virtual area of the
text, data and bss. However, we can't simply change the link address as
the core image (used physically respectively 1:1 mapped) needs to be in
this particular RAM-region as it is the only one that can be protected
against a VM. Thus I've moved the context area to a place where it
shouldn't disturb any HW-platform.

Fixes #1337
2015-01-07 10:41:22 +01:00
Martin Stein
e63092f1dd hw & cortex_a9: fix scheduling-timer speed
The estimation of the input clock of the Cortex A9 Private Timer module
was pretty miserable at every Cortex A9 board.

Fixes #1341
2015-01-06 15:22:07 +01:00
Martin Stein
ba321c20d1 hw vea9x4: let userland timer SP804 0/1 be secure
Declaring the SP804 0/1 module and its interrupt to be non-secure prevents the
secure Genode from receiving the interrupt and hence the timer driver in the
secure Genode doesn't work.

Fixes #1340
2015-01-06 15:16:02 +01:00
Martin Stein
659f6ff5c8 hw_vea9x4: quickfix for missing SMP awareness
This fix configures TTBRs and translation-table descriptors as if we would use
SMP although we don't to circumvent problems with UP-configurations.
This fix should be superseded later by full SMP support for the VEA9X4.

ref #1312
2014-12-19 13:58:49 +01:00
Martin Stein
d31492040c hw: fix race on pager-object dissolve
The HW-kernel, in contrast to other kernels, provides a direct reference
to the pager object with the fault signal that is send to the pager
activation. When accessing this reference directly we may fall into the
time span where the root parent-entrypoint of the faulter has alredy
dissolved the pager object from the pager entrypoint, but not yet
silenced the according signal context.  To avoid this we issue an
additional 'lookup_and_lock' with the received pager object. This isn't
optimal as we don't need the potentially cost-intensive lookup but only the
synchronization.

Fixes #1311.
Fixes #1332.
2014-12-19 13:58:48 +01:00
Martin Stein
d704563453 hw: helping on IPC
On base-hw, each thread owns exactly one scheduling context for its
whole lifetime. However, introducing helping on IPC, a thread might get
executed on scheduling contexts that it doesn't own. Figuratively
spoken, the IPC-helping relation spans trees between threads. These
trees are identical to those of the IPC relation between threads. The
root of such a tree is executed on all scheduling contexts in the tree.
All other threads in the tree are not executed on any scheduling context
as long as they remain in this position. Consequently, the ready-state
of all scheduling contexts in an IPC-helping tree always equals the
state of the root context.

fix #1102
2014-12-19 13:58:47 +01:00
Martin Stein
6370b6880a hw: rename Thread::State SCHEDULED in ACTIVE
As soon as helping is used, a thread may also be in a blocking state when its
scheduling context is ready. Hence, the state designation SCHEDULED for an active
thread would be pretty misleading.

ref #1102
2014-12-19 13:58:47 +01:00
Martin Stein
6f377ec4c5 hw: add FIFO variant with for_each() method
ref #1102
2014-12-19 13:58:47 +01:00
Martin Stein
9c027fd9bd hw: remove deprecated TLB declaration
fix #1320
2014-12-19 13:58:47 +01:00
Stefan Kalkowski
4d3fa001e0 hw: remove memory region duplicate (fix #1304)
On the Versatile Express Cortex A9x4 platform the first memory region
0x0 - 0x4000000 is a hardware remapped memory area, containing flash
and DDR RAM copies and thus should not be added in addition to all
DDR RAM regions and the SRAM region.
2014-11-28 12:02:40 +01:00
Martin Stein
8f9355b360 thread API & CPU session: accounting of CPU quota
In the init configuration one can configure the donation of CPU time via
'resource' tags that have the attribute 'name' set to "CPU" and the
attribute 'quantum' set to the percentage of CPU quota that init shall
donate. The pattern is the same as when donating RAM quota.

! <start name="test">
!   <resource name="CPU" quantum="75"/>
! </start>

This would cause init to try donating 75% of its CPU quota to the child
"test".  Init and core do not preserve CPU quota for their own
requirements by default as it is done with RAM quota.

The CPU quota that a process owns can be applied through the thread
constructor. The constructor has been enhanced by an argument that
indicates the percentage of the programs CPU quota that shall be granted
to the new thread. So 'Thread(33, "test")' would cause the backing CPU
session to try to grant 33% of the programs CPU quota to the thread
"test". By now, the CPU quota of a thread can't be altered after
construction. Constructing a thread with CPU quota 0 doesn't mean the
thread gets never scheduled but that the thread has no guaranty to receive
CPU time. Such threads have to live with excess CPU time.

Threads that already existed in the official repositories of Genode were
adapted in the way that they receive a quota of 0.

This commit also provides a run test 'cpu_quota' in base-hw (the only
kernel that applies the CPU-quota scheme currently). The test basically
runs three threads with different physical CPU quota. The threads simply
count for 30 seconds each and the test then checks wether the counter
values relate to the CPU-quota distribution.

fix #1275
2014-11-28 12:02:37 +01:00
Martin Stein
09e6c3457f hw_arndale: consider timer resets
On Arndale, the kernel timer resets to the initial value of the last
count-down and continues as soon as it reaches zero. We must check this
via the interrupt status when we read out the timer value and in case
return 0 instead of the real value.

fix #1299
2014-11-28 12:02:37 +01:00
Martin Stein
b8ba3a7a22 hw: rename Kernel::Processor Kernel::Cpu
Kernel::Processor was a confusing remnant from the old scheme where we had a
Processor_driver (now Genode::Cpu) and a Processor (now Kernel::Cpu).
This commit also updates the in-code documentation and the variable and
function naming accordingly.

fix #1274
2014-11-28 12:02:35 +01:00
Martin Stein
b3655902ed hw & arm_v7: provide run/hw_info
The run test 'hw_info' prints the content of the basic ARMv7 identification and
feature registers in a pretty readable format. It is a kernel-internal test
because many of these registers are restricted to privilege level 1 or higher.

fix #1278
2014-11-28 12:02:35 +01:00
Martin Stein
1b1fd1e1f9 hw: add and test totally sophisticated scheduler
The new scheduler serves the orthogonal requirements of both
high-throughput-oriented scheduling contexts (shortly called fill in the
scheduler) and low-latency-oriented scheduling contexts (shortly called
claim in the scheduler). Thus it knows two scheduling modes. Every claim
owns a CPU-time-quota expressed as percentage of a super period
(currently 1 second) and a priority that is absolute as long as the
claim has quota left for the current super period. At the end of a super
period the quota of all claims gets refreshed. During a super period,
the claim mode is dominant as long as any active claim has quota left.
Every time this isn't the case, the scheduler switches to scheduling of
fills. Fills are scheduled in a simple round robin with identical time
slices. Order and time-slices of the fill scheduling are not affected by
the super period. Now on thread creation, two arguments, priority and
quota are needed. If quota is 0, the new thread participates in CPU
scheduling with a fill only.  Otherwise he participates with both a
claim and a fill. This concept dovetails nicely with Genodes quota based
resource management as any process can grant subsets of its own
CPU-time and priorities to its child without knowing the global means of
CPU-time and priority.

The commit also adds a run script that enables an automated unit test of the
scheduler implementation.

fix #1225
2014-11-28 12:02:35 +01:00
Martin Stein
a00eb9a66a hw: enhance and test double-list data-structure
To serve the needs of the coming CPU scheduler, the double list needs
additional methods such as 'to_tail' and 'insert_head'.

The commit also adds a run script that enables an automated unit test
of the list implementation.

ref #1225
2014-11-28 12:02:35 +01:00
Martin Stein
0ab5310b8a hw: enable kernel-internal tests via run tool
Kernel tests are done by replacing the implementation of an otherwise
empty function 'Kernel::test' that gets called once at the primary CPU
as soon as all kernel initialization is done. To achieve this, the test
binary that implements 'Kernel::test' must be linked against the core
lib and must then replace the core binary when composing the boot image.
The latter can be done conveniently in a run script by setting the new
argument 'core_type' of the function 'build_boot_image' to the falue
'test'. If no kernel test is needed the argument does not have to be
given - it is set to 'core' by default which results in a "normal"
Genode image.

ref #1225
2014-11-28 12:02:34 +01:00
Martin Stein
b3bc9bd549 hw: idle execution context is no thread anymore
Previously, Idle_thread inherited from Thread which caused an extra
processor_pool.h and processor_pool.cc and also made class models for
processor and scheduling more complex. However, this inheritance makes
not much sense anyway as an idle context doesn't trigger most of the code
in Thread.

ref #1225
2014-11-28 12:02:34 +01:00
Martin Stein
ec6c19a487 base: memory barriers in lock implementations
The memory barrier prevents the compiler from changing the program order
of memory accesses in such a way that accesses to the guarded resource
get outside the guarded stage. As cmpxchg() defines the start of the
guarded stage it also represents an effective memory barrier.

On x86, the architecture ensures to not reorder writes with older reads,
writes to memory with other writes (except in cases that are not
relevant for our locks), or read/write instructions with I/O
instructions, locked instructions, and serializing instructions.

However on ARM, the architectural memory model allows not only that
memory accesses take local effect in another order as their program
order but also that different observers (components that can access
memory like data-busses, TLBs and branch predictors) observe these
effects each in another order. Thus, a correct program order isn't
sufficient for a correct observation order. An additional architectural
preservation of the memory barrier is needed to achieve this.

Fixes #692
2014-11-28 12:02:34 +01:00
Stefan Kalkowski
d452f37c25 hw: print page faults of core (fix #1286) 2014-11-28 12:00:44 +01:00
Martin Stein
635de1791f hw: fix panda instability on kernel exits
Invalidating all branch predictors before switching the PD
fixes instability problems on Panda and has not much effect
on the performance of other boards. However, we neither know why
this is a fix nor wether it fixes the real cause of the problem.

fix #1294
2014-11-20 16:39:16 +01:00
Stefan Kalkowski
0ffc89ee30 hw: clrex during context switch (Fixes #1196) 2014-11-20 16:39:16 +01:00
Martin Stein
8dad54c914 hw: fix scheduler timing on prio preemption
Previously, the timer was used to remember the state of the time slices.
This was sufficient before priorities entered the scene as a thread always
received a fresh time slice when he was scheduled away. However, with
priorities this isn't always the case. A thread can be preempted by another
thread due to a higher priority. In this case the low-priority thread must
remember how much time he has consumed from its current time slice because
the timer gets re-programmed. Otherwise, if we have high-priority threads
that block and unblock with high frequency, the head of the next lower
priority would start with a fresh time slice all the time and is never
superseded.

fix #1287
2014-11-14 12:00:45 +01:00
Norman Feske
58a1e42201 hw/rpi: USB SOF interrupt filtering 2014-10-13 14:52:43 +02:00
Norman Feske
d59d3c684f hw: don't preserve mmio of core devices
Fixes #1269
2014-10-13 14:51:55 +02:00
Stefan Kalkowski
3befb64afe hw: correctly flush cache on ARM (fix #1257)
* When flushing the data and unified cache on ARM, clean and invalidate
  instead of just cleaning the corresponding cache lines
* After zero-ing a freshly constructed dataspace in core, invalidate
  corresponding cache lines from the instruction cache
2014-10-10 13:02:30 +02:00
Stefan Kalkowski
f0fae2a5f2 hw: set TTBR0 according to CPU facilities
Fixes #1195
2014-10-10 13:02:30 +02:00
Martin Stein
14e9a89cba hw: no superfluous ORing of zeros and clean up
fix #710
2014-08-15 10:19:49 +02:00
Martin Stein
e7d57ded36 hw & trustzone: fix alignm. of VM exception-vector
After modifying mode transition for branch prediction tz_vmm wasn't
working anymore on hw_imx53_tz but the modifications had nothing to do
with the VM code. However, the amount of instructions in the MT before the
VM exception-vector changed. So I tried stuffing the last working version with
NOPs and found that tz_vmm worked for some NOP amounts and for others not.
Thus, I increased the alignment of the VM exception-vector from 16 bytes to 32
bytes, é voila, its working with any amount of NOPs as well as with branch
prediction commits.

ref #474
2014-08-15 10:19:49 +02:00
Martin Stein
c03b277a34 hw & arm_v7: enable branch prediction
fix #474
2014-08-15 10:19:49 +02:00
Martin Stein
9da42dde2f hw & arm_v7: mode transition via transit ttbr0
Previously, we did the protection-domain switches without a transitional
translation table that contains only global mappings. This was fine as long
as the CPU did no speculative memory accesses. However, to enabling branch
prediction triggers such accesses. Thus, if we don't want to invalidate
predictors on every context switch, we need to switch more carefully.

ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
03cd76821c hw & arm: exceptions to asserts in transl. table
ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
e686aee5f9 hw: provide 'bool aligned' function in util.h
ref #474
2014-08-15 10:19:48 +02:00
Martin Stein
d48d0e7b43 hw: rename processor CPU
fix #1217
2014-08-15 10:19:48 +02:00
Martin Stein
1cba71208f hw: cpu_support to kernel/thread_base
ref #1217
2014-08-15 10:19:48 +02:00
Martin Stein
a5cf09fa6e hw: re-organize file structure
fix #1197
2014-08-15 10:19:48 +02:00
Martin Stein
1bc8de83ff hw & arm_v6: fix bug in calculation of kernel SP
For ARMv6, this aspect wasn't updatet to the new kernel-stack
managment that came up with SMP support.

ref #1199
2014-07-24 10:18:08 +02:00
Christian Prochaska
a46de84f89 Fix race condition in page fault notification
When a page fault cannot be resolved, the GDB monitor can get a hint about
which thread faulted by evaluating the thread state object returned by
'Cpu_session::state()'. Unfortunately, with the current implementation,
the signal which informs GDB monitor about the page fault is sent before
the thread state object of the faulted thread has been updated, so it
can happen that the faulted thread cannot be determined immediately
after receiving the signal.

With this commit, the thread state gets updated before the signal is sent.

At least on base-nova it can also happen that the thread state is not
accessible yet after receiving the page fault notification. For this
reason, GDB monitor needs to retry its query until the state is
accessible.

Fixes #1206.
2014-07-24 10:18:07 +02:00
Martin Stein
6cb9559feb hw: core as library
The build config for core is now provided through libraries to enable
implicit config composition through specifiers and thereby avoid
consideration of inappropriate targets.

fix #1199
2014-07-24 10:18:06 +02:00
Martin Stein
5f145b74a5 hw_imx31: fix compilation error in timer.h
fix #1200
2014-07-24 10:18:06 +02:00
Stefan Kalkowski
609f7abb0a hw: map a dataspace in core according to its flags
Thereby removing obsolete quirk for uncached CPU state dataspace
in VM session.

Fixes #1198
2014-07-24 10:18:06 +02:00
Stefan Kalkowski
8f57ff1f27 hw: re-enable the L2 cache for i.MX53 (Ref #1194) 2014-07-09 16:26:06 +02:00
Stefan Kalkowski
1c11099f09 hw: clean cache lines of altered translation table
For Cortex A8, and ARM1176JZF clean cache lines of altered MMU translation
tables.

Fix #1194
2014-07-09 16:26:06 +02:00
Stefan Kalkowski
1c99ee951a hw: set pages shareable in SMP systems only
Fixes #1181
2014-07-09 16:26:05 +02:00
Martin Stein
f3ae42275a hw: move global TLB flush to extra class
A subject that inherits from Processor_client not necessarily has the need for
doing a processor-global TLB flush (e.g. VMs). At the other hand the Thread
class (as representation of the only source of TLB flushes) is already one of
the largest classes in base-hw because it provides all the syscall backends
and should therefore not accumulate other aspects without a functional reason.
Hence, I decided to move the aspect of synchronizing a TLB flush over all
processors to a dedicated class named Processor_domain_update.
Additionally a singleton of Processor_domain_update_list is used to enable
each processor to see all update-domain requests that are currently pending.

fix #1174
2014-06-26 13:42:52 +02:00
Martin Stein
6e993d31d4 hw: for_each & safer type casts in Double_list
ref #1174
2014-06-26 12:09:40 +02:00
Martin Stein
f0478ee214 hw: move double list to extra header
ref #1174
2014-06-26 12:09:26 +02:00
Stefan Kalkowski
e45fc7f0d7 hw: avoid locks before cache initialization
Fix #1190
2014-06-26 12:04:31 +02:00
Stefan Kalkowski
b8798fc026 hw: prevent from off-by-one bugs in PIC classes
Instead of using Pic::MAX_INTERRUPT_ID this commit introduces more
conveniently the Pic:NR_OF_IRQ.

Ref #1169
2014-06-26 11:40:07 +02:00
Stefan Kalkowski
6d12f4eba7 hw: off-by-one bug when determining the last IRQ
Fix #1169
2014-06-26 11:39:55 +02:00
Stefan Kalkowski
a492366eea hw: fix the TrustZone VM entry path
Commit 6a3368ee that refactored the mode transition assembler path, and
high-level entry point, fundamentally broke that part for the TrustZone VMs.
Instead of jumping to the appropriated address, the instruction value at that
point where used as target address.
Moreover, the TrustZone part of the mode transition page was not included into
the boundary check.

Ref #1182
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
7b5237f9ff hw: add CSU I/O memory to core's memory regions
The central security regions has to be mapped when starting the hw-kernel
on the i.MX53 and using the TrustZone mechanisms.

Ref #1182
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
7ca56e3fc4 hw: fix compilation errors for i.MX53/TrustZone
Fix #1182
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
e5b78a6494 hw: disable L2 cache for imx53 platform
Currently the L2 cache for i.MX53 doesn't work correctly in the
hw-kernel, so we temporarily disable it.

Ref #1182
2014-06-26 10:57:27 +02:00
Stefan Kalkowski
786fe805da base: introduce caching attributes (fix #1184)
On ARM it's relevant to not only distinguish between ordinary cached memory
and write-combined one, but also having non-cached memory too. To insert the
appropriated page table entries e.g.: in the base-hw kernel, we need to preserve
the information about the kind of memory from allocation until the pager
resolves a page fault. Therefore, this commit introduces a new Cache_attribute
type, and replaces the write_combined boolean with the new type where necessary.
2014-06-26 10:57:26 +02:00
Stefan Kalkowski
031cabf862 hw: let assembler constants be upper-case (Ref #1180) 2014-06-26 10:57:26 +02:00
Stefan Kalkowski
00ee2b565a hw: define assembler constants in global scope
Don't define assembler constants inside macros, thereby calling the
corresponding macros isn't needed anymore. To prevent having to much
constants included in files where they aren't needed, split macros.s
file into a generic mode_transition.s part, and globally used macros.s.

Fix #1180
2014-06-26 10:57:26 +02:00
Martin Stein
f5fdcc8f1e hw: get a thread cap in Thread_base constructor
Previously this was not done before Thread_base::start(..) in
base-hw as it was not needed to have a valid cap that early. However,
when changing the affinity of a thread we need the cap to be valid
before Thread_base::start(..).

fix #1151
2014-06-26 10:57:26 +02:00
Martin Stein
ccba43574f hw: fix bug in scheduler timing
By now the scheduling timer was only refreshed for a new scheduling timeout
when the choosen scheduling context has changed. But we want it to be refreshed
also when the scheduled context yields without an effect to the schedulers
choice (this is the case e.g. when the idle thread gets a scheduling timeout
or a thread yields without any competitor in its priority band).

ref #1151
2014-06-26 10:57:26 +02:00
Martin Stein
4b7d58fccc hw & cortex_a9: do lazy FPU-context switch
ref #1126
2014-06-26 10:57:25 +02:00
Stefan Kalkowski
05603951b6 hw: enable and maintain outer l2 cache
Fix #1170
2014-06-26 10:57:25 +02:00
Martin Stein
8d145bd80c hw & rpi: provide Pic::MAX_INTERRUPT_ID
fix #1160
2014-06-06 14:54:31 +02:00
Martin Stein
f53e4ff8f5 hw: align kernel stack appropriately
fix #1161
2014-06-06 14:54:31 +02:00
Martin Stein
8d43b67ca6 hw: map binaries of boot modules on demand
fix #1139
2014-06-06 14:54:31 +02:00
Christian Helmuth
06a10b3695 hw: log "Test succeeded" in nested_init.run 2014-06-06 14:54:30 +02:00
Stefan Kalkowski
7138b2740a hw: fix section insertion in translation tables
Fixes an alignment problem introduced by commit "hw: map core on demand"
where physical address alignment wasn't checked anymore, when inserting
a section within the first-level table of ARM's short translation table
format.

Many thanks to Christian Prochaska for helping to debug the problem.
2014-05-28 12:28:11 +02:00
Christian Prochaska
078883fda3 base: interface for D- and I-cache synchronization
On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes #1153.
2014-05-27 11:14:45 +02:00
Norman Feske
ca971bbfd8 Move repositories to 'repos/' subdirectory
This patch changes the top-level directory layout as a preparatory
step for improving the tools for managing 3rd-party source codes.
The rationale is described in the issue referenced below.

Issue #1082
2014-05-14 16:08:00 +02:00