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The implementation initializes the Local APIC (LAPIC) of CPU 0 in xapic mode (mmio register access) and uses the I/O APIC to remap, mask and unmask hardware IRQs. The remapping offset of IRQs is 48. Also initialize the legacy PIC and mask all interrupts in order to disable it. For more information about LAPIC and I/O APIC see Intel SDM Vol. 3A, chapter 10 and the Intel 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) specification Set bit 9 in the RFLAGS register of user CPU context to enable interrupts on kernel- to usermode switch. |
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