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hw_x86_64: Explicitly set all FPU-related CR flags
Perform all FPU-related setup in the Cpu class' init_fpu function instead of the general system bring-up assembly code. Set all required control register 0 and 4 flags according to Intel SDM Vol. 3A, sections 9.2 and 9.6 instead of only enabling FPU error reporting and OSFXSR.
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repos/base-hw/src/core
@ -256,10 +256,25 @@ class Genode::Cpu
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static void _enable_fpu() { asm volatile ("clts"); }
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/**
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* Initialize FPU without checking for pending unmasked floating-point
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* exceptions.
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* Initialize FPU with SSE extensions by setting required CR0 and CR4
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* bits to configure the FPU environment according to Intel SDM Vol.
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* 3A, sections 9.2 and 9.6.
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*/
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static void _init_fpu() { asm volatile ("fninit"); }
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static void _init_fpu()
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{
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Cr0::access_t cr0_value = Cr0::read();
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Cr4::access_t cr4_value = Cr4::read();
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Cr0::Mp::set(cr0_value);
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Cr0::Em::clear(cr0_value);
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Cr0::Ts::set(cr0_value);
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Cr0::Ne::set(cr0_value);
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Cr0::write(cr0_value);
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Cr4::Osfxsr::set(cr4_value);
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Cr4::Osxmmexcpt::set(cr4_value);
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Cr4::write(cr4_value);
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}
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/**
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* Returns True if the FPU is enabled.
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@ -41,10 +41,9 @@
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xor %eax, %eax
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rep stosl
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/* Enable PAE (prerequisite for IA-32e mode) and OSFXSR */
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/* Enable PAE (prerequisite for IA-32e mode) */
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movl %cr4, %eax
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btsl $5, %eax
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btsl $9, %eax
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movl %eax, %cr4
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/* Load initial pagetables */
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@ -58,9 +57,8 @@
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btsl $11, %eax
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wrmsr
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/* Enable paging, write protection, caching and FPU error reporting */
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/* Enable paging, write protection and caching */
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movl %cr0, %eax
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btsl $5, %eax
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btsl $16, %eax
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btrl $29, %eax
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btrl $30, %eax
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