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base: interface for D- and I-cache synchronization

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On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes #1153.
This commit is contained in:
Christian Prochaska 2014-05-20 22:52:56 +02:00 committed by Norman Feske
parent b28a551538
commit 078883fda3
14 changed files with 139 additions and 0 deletions
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1
repos/base-codezero/lib/mk/base.mk
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@ -1,4 +1,5 @@
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread_start.cc

1
repos/base-fiasco/lib/mk/base.mk
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@ -7,6 +7,7 @@
LIBS += base-common
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread_start.cc

1
repos/base-foc/lib/mk/base.mk
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@ -7,6 +7,7 @@
LIBS += base-common
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc \
env/cap_map_remove.cc env/cap_alloc.cc
SRC_CC += thread/thread_start.cc

23
repos/base-foc/src/base/cpu/cache.cc Normal file
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@ -0,0 +1,23 @@
/*
* \brief Implementation of the cache operations
* \author Christian Prochaska
* \date 2014-05-13
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
namespace Fiasco {
#include <l4/sys/cache.h>
}
#include <cpu/cache.h>
void Genode::cache_coherent(Genode::addr_t addr, Genode::size_t size)
{
Fiasco::l4_cache_coherent(addr, addr + size);
}

1
repos/base-hw/lib/mk/base.mk
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@ -7,6 +7,7 @@
LIBS += base-common startup
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread.cc thread_support.cc

21
repos/base-hw/src/base/cpu/cache.cc Normal file
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@ -0,0 +1,21 @@
/*
* \brief Implementation of the cache operations
* \author Christian Prochaska
* \date 2014-05-13
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#include <kernel/interface.h>
#include <cpu/cache.h>
void Genode::cache_coherent(Genode::addr_t addr, Genode::size_t size)
{
Kernel::update_instr_region(addr, size);
}

9
repos/base-linux/lib/mk/arm/base.mk Normal file
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@ -0,0 +1,9 @@
#
# \brief ARM-specific base lib parts that are not used by hybrid applications
# \author Christian Prochaska
# \date 2014-05-14
#
SRC_CC += cpu/arm/cache.cc
include $(REP_DIR)/lib/mk/base.mk

9
repos/base-linux/lib/mk/x86/base.mk Normal file
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@ -0,0 +1,9 @@
#
# \brief x86-specific base lib parts that are not used by hybrid applications
# \author Christian Prochaska
# \date 2014-05-14
#
SRC_CC += cpu/cache.cc
include $(REP_DIR)/lib/mk/base.mk

21
repos/base-linux/src/base/cpu/arm/cache.cc Normal file
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@ -0,0 +1,21 @@
/*
* \brief Implementation of the cache operations
* \author Christian Prochaska
* \date 2014-05-13
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#include <linux_syscalls.h>
#include <cpu/cache.h>
void Genode::cache_coherent(Genode::addr_t addr, Genode::size_t size)
{
lx_syscall(__ARM_NR_cacheflush, addr, addr + size, 0);
}

1
repos/base-nova/lib/mk/base.mk
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@ -7,6 +7,7 @@
LIBS += base-common
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread_nova.cc

1
repos/base-okl4/lib/mk/base.mk
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@ -1,4 +1,5 @@
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread_start.cc

1
repos/base-pistachio/lib/mk/base.mk
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@ -7,6 +7,7 @@
LIBS += base-common
SRC_CC += console/log_console.cc
SRC_CC += cpu/cache.cc
SRC_CC += env/env.cc env/context_area.cc env/reinitialize.cc
SRC_CC += thread/thread_start.cc

28
repos/base/include/cpu/cache.h Normal file
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@ -0,0 +1,28 @@
/*
* \brief Cache operations
* \author Christian Prochaska
* \date 2014-05-13
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__CPU__CACHE_H_
#define _INCLUDE__CPU__CACHE_H_
#include <base/stdint.h>
namespace Genode {
/*
* Make D-Cache and I-Cache coherent
*/
void cache_coherent(Genode::addr_t addr, Genode::size_t size);
}
#endif /* _INCLUDE__CPU__CACHE_H_ */

21
repos/base/src/base/cpu/cache.cc Normal file
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@ -0,0 +1,21 @@
/*
* \brief Implementation of the cache operations
* \author Christian Prochaska
* \date 2014-05-13
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#include <cpu/cache.h>
/*
* This function needs to be implemented only for base platforms with ARM
* support right now, so the default implementation does nothing.
*/
void cache_coherent(Genode::addr_t, Genode::size_t) { }