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hw & rpi: provide Pic::MAX_INTERRUPT_ID

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fix #1160
This commit is contained in:
Martin Stein 2014-04-29 12:46:36 +02:00 committed by Christian Helmuth
parent f53e4ff8f5
commit 8d145bd80c
1 changed files with 20 additions and 16 deletions
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36
repos/base-hw/src/core/rpi/pic.h
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@ -25,25 +25,29 @@ namespace Kernel
{
class Pic : Genode::Mmio
{
struct Irq_pending_basic : Register<0x0, 32>
{
struct Timer : Bitfield<0, 1> { };
struct Gpu : Bitfield<8, 2> { };
};
public:
struct Irq_pending_gpu_1 : Register<0x04, 32> { };
struct Irq_pending_gpu_2 : Register<0x08, 32> { };
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
struct Irq_enable_basic : Register<0x18, 32> { };
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
struct Irq_disable_basic : Register<0x24, 32> { };
enum { MAX_INTERRUPT_ID = 64 };
private:
struct Irq_pending_basic : Register<0x0, 32>
{
struct Timer : Bitfield<0, 1> { };
struct Gpu : Bitfield<8, 2> { };
};
struct Irq_pending_gpu_1 : Register<0x04, 32> { };
struct Irq_pending_gpu_2 : Register<0x08, 32> { };
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
struct Irq_enable_basic : Register<0x18, 32> { };
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
struct Irq_disable_basic : Register<0x24, 32> { };
typedef Genode::uint32_t uint32_t;
/**
@ -76,7 +80,7 @@ namespace Kernel
}
/* search for lowest set bit in pending masks */
for (unsigned i = 0; i < 64; i++) {
for (unsigned i = 0; i < MAX_INTERRUPT_ID; i++) {
if (!_is_pending(i, p1, p2))
continue;