Xianjun Jiao
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913a9e947c
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add ack disable register in xpu in case ack needs to be disabled in monitor mode
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2021-04-05 21:51:47 +02:00 |
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Xianjun Jiao
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bb0a2c5897
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in xpu.v slv_reg19 and slv_reg8 are not twistted anymore. slv_reg6 is added to assist the register map in xpu more clear. separate registers for different purpose. separate registers for dynamic and static configurations in driver (sdr.c).
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2021-04-05 21:49:59 +02:00 |
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Jiao Xianjun
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55c2866f7c
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Merge pull request #54 from lnceballosz/master
NGI0 - Updating licensing aspects according REUSE
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2021-02-03 16:14:49 +01:00 |
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Jiao Xianjun
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9e7be83fb0
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Update xpu.c
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2021-02-03 15:45:09 +01:00 |
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weiliu
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2238b42bb8
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improve csma state machine, force ch_idle high after decode, log cw and num_slot_random in the last attempt
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2021-01-28 14:15:29 +01:00 |
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Lina Ceballos
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a6085186d9
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adding license and copyright headers
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2021-01-20 13:30:12 +01:00 |
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weiliu
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5680efab70
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enable dynamic cw
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2020-12-28 16:03:51 +01:00 |
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Xianjun Jiao
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5deb8d18f6
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sync internal
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2020-12-14 13:32:15 +01:00 |
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Xianjun Jiao
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838a9007cf
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update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
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2020-06-12 10:50:34 +02:00 |
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Xianjun Jiao
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febc5adf73
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prepare upgrade
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2020-04-27 09:37:04 +02:00 |
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Xianjun Jiao
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2a1e074623
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fix the potential memory access over boundary issue of openwifi_rx_interrupt and make necessary configuration for new FPGA that tx sending out I/Q immediately after tx_start which achieves 10us SIFS in 2.4GHz
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2020-01-07 14:17:08 +01:00 |
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Xianjun Jiao
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2ee6717882
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initial commit
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2019-12-10 14:03:47 +01:00 |
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