15 Commits

Author	SHA1	Message	Date
Jinghao Shi	701cbb70c9	variable name	2017-04-14 11:00:46 -04:00
Jinghao Shi	0b0723899a	rotate	2017-04-14 11:00:33 -04:00
Jinghao Shi	47577f7099	fix comment	2017-04-14 11:00:12 -04:00
Jinghao Shi	191b197d5e	fix polarity pattern	2017-04-14 11:00:01 -04:00
Jinghao Shi	297162af13	working	2017-04-07 16:51:06 -04:00
Jinghao Shi	20279b42a4	fix long preamble sample beginning index	2017-04-07 16:49:41 -04:00
Jinghao Shi	779b3651a4	remove unused verilog files	2017-04-07 11:36:51 -04:00
Jinghao Shi	8375779a03	refactor name	2017-04-07 11:36:41 -04:00
Jinghao Shi	4dd053ebf8	use delayT	2017-04-07 11:36:21 -04:00
Jinghao Shi	cf42e1b7ae	working	2017-04-03 15:48:25 -04:00
Jinghao Shi	506472dec3	add sim_out dir	2017-04-03 15:25:48 -04:00
Jinghao Shi	1ad9302fc3	readme	2017-04-03 14:31:25 -04:00
Jinghao Shi	d3ff9e7ce8	makefile	2017-04-03 14:05:07 -04:00
Jinghao Shi	bf4701fb39	makefile	2017-04-03 12:59:32 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00