The ESW core needs to be reset together with FE core, so after the
relevant reset controller lines are moved under FE, drop rst_esw and all
related code, which would not execute anyway, because rst_esw would be
NULL. While at that, ensure that if reset line for EPHY cannot be
claimed, a proper error message is reported.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f393ffcac1)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Enabling the FE core too early causes the system to hang during boot
uncondtionally, after the reset is released. Increate it to 1-1.2ms
range.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split previous commit, provide rationale]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 7eb0458c1f)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Use devm_reset_control_array_get_exclusive to register multiple
reset lines in FE driver. This is required to reattach ESW reset to FE
driver again, based on device tree bindings.
While at that, remove unused fe_priv.rst_ppe field, and add error
message if getting the reset fails.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 3f1be8edee)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
In the current state, nvmem cells are only detected on platform device.
To quickly fix the problem, we register the affected problematic driver
with the of_platform but that is more an hack than a real solution.
Backport from net-next the required patch so that nvmem can work also
with non-platform devices and rework our current patch.
Drop the mediatek and dsa workaround and rework the ath10k patches.
Rework every driver that use the of_get_mac_address api.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Ensure the esw is initialized before the ethernet device is sending
packets. Further implement carrier detection similar to mt7620.
If any port has a link, the ethernet device will detect a carrier.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
For rt3050 the switch needs to be initialized before the ethernet start sending
packets. Allow switch_init to return -EPROBE_DEFER.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The dts defines the reset fe for all architectures. However
the soc code used direct register access of the reset controller.
Replace the custom soc reset with a generic fe_reset_fe().
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The fe_reset function direct access the reset controller instead
using the reset controller api. In preparation to use the
reset controller.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Define and use some missing macros,
and use them instead of BIT() or numbers for more readable code.
Add comment for a bit change that seems unrelated to ethernet
but is actually needed (PCIe Root Complex mode).
Remove unknown and unused macro RST_CTRL_MCM
(probably from MT7621 / MT7622)
This is the last of a series of fixes, so bump version.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
the register bits for TX delay and RX delay are opposites:
when TX delay bit is set, delay is enabled
when RX delay bit is set, delay is disabled
So, when both bits are unset, it is RX delay
and when both bits are set, it is TX delay
Note: TXID is the default RGMII mode of the SOC
Fixes: 5410a8e295 ("ramips: mt7620: add rgmii delays support")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Add back the register write to disable internal PHYs
as a separate option in the code that can be set using a DTS property.
Set the option to true by default
when an external mt7530 switch is identified.
This makes the driver more in sync with original SDK code
while keeping the lines separated into different options
to accommodate any board with any PHY layout.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
The function mt7620_mdio_mode is only called once
and both the function and mdio_mode block have been named incorrectly,
leading to confusion and useless commits.
These lines in the mdio_mode block of mt7620_hw_init
are only intended for boards with an external mt7530 switch.
(see commit 194ca6127e)
Therefore, move lines from mdio_mode to the place in soc_mt7620.c
where the type of mt7530 switch is identified,
and move lines from mt7620_mdio_mode to a main function.
mt7620_mdio_mode was called from mt7620_gsw_init
where the priv struct is available,
so the lines must stay in mt7620_gsw_init function.
In order to keep things as simple as possible,
keep the DTS property related function calls together,
by moving them from mt7620_gsw_probe to init.
Remove the now useless DTS properties and extra phy nodes.
Fixes: 5a6229a93d ("ramips: remove superfluous & confusing DT binding")
Fixes: b85fe43ec8 ("ramips: mt7620: add force use of mdio-mode")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
When the new variable ephy_base was introduced,
it was not applied to the if block for mdio_mode.
The first line in the mdio_mode if block
sets the EPHY base address to 12 in the SOC by writing a register,
but the corresponding variable in the driver
was still set to the default of 0.
This causes subsequent lines that write registers with the function
_mt7620_mii_write
to write to PHY addresses 0 through 4
while internal PHYs have been moved to addresses 12 through 16.
All of these lines are intended only for PHYs on the SOC internal switch,
however, they are being written to external ethernet switches
if they exist at those PHY addresses 0 through 4.
This causes some ethernet ports to be broken on boards with AR8327 or QCA8337 switch.
Other suggested fixes move those lines to the else block of mdio_mode,
but removing the else block completely also fixes it.
Therefore, move the lines to the mt7620_hw_init function main block,
and have only one instance of the function mtk_switch_w32
for writing the register with the EPHY base address.
In theory, this also allows for boards that have both external switches
and internal PHYs that lead to ethernet ports to be supported.
Fixes: 391df37829 ("ramips: mt7620: add EPHY base mdio address changing possibility")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
A workaround was added to the switch driver
to set SOC port 4 as an RGMII GMAC interface
based on the DTS property mediatek,port4-gmac.
(previously mediatek,port4)
However, the ethernet driver already does this,
but is being blocked by a return statement
whenever the phy-handle and fixed-link properties
are both missing from nodes that define the port properties.
Revert the workaround, so that both the switch driver
and ethernet driver are not doing the same thing
and move the phy-handle related lines down
so nothing is ending the function prematurely.
While at it, clean up kernel messages
and delete useless return statements.
Fixes: f6d81e2fa1 ("mt7620: gsw: make IntPHY and ExtPHY share mdio addr 4 possible")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
These nodes are used for configuring a GMAC interface
and for defining external PHYs to be accessed with MDIO.
None of this is possible on MT7620N, only MT7620A,
so remove them from all MT7620N DTS.
When the mdio-bus node is missing, the driver returns -NODEV
which causes the internal switch to not initialize.
Replace that return so that everything works without the DTS node.
Also, an extra kernel message to indicate for all error conditions
that mdio-bus is disabled.
Fixes: d482356322 ("ramips: mt7620n: add mdio node and disable port4 by default")
Fixes: aa5014dd1a ("ramips: mt7620n: enable port 4 as EPHY by default")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
There are only 2 options in the driver
for the function of mt7620 internal switch port 4:
EPHY mode (RJ-45, internal PHY)
GMAC mode (RGMII, external PHY)
Let the DTS property be boolean instead of string
where EPHY mode is the default.
Fix how the properties are written
for all DTS that use them,
and add missing nodes where applicable,
and remove useless nodes,
and minor DTS formatting.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
This enables autonegotiation for all ephy ports on probe.
Some devices do not configure the ports, particularly port 4.
Signed-off-by: Gaspare Bruno <gaspare@anlix.io>
[replace magic values ; reword commit message]
Signed-off-by: David Bauer <mail@david-bauer.net>
The basic mode control register of the ESW PHYs is modified in this
codeblock. Use the respective macros to make this code more readable.
Signed-off-by: David Bauer <mail@david-bauer.net>
The mt7530_{r,w}32 operation over MDIO uses 3 mdiobus operations and
does not hold a lock, which causes a race condition when multiple
threads try to access a register, they may get unexpected results.
To avoid this, handle the MDIO lock manually, and use the unlocked
__mdiobus_{read,write} in the critical section.
This fixes the "Ghost VLAN" artifact[1] in MT7530/7621 when the VLAN
operation and the swconfig LED link status poll race between each other.
[1] https://forum.openwrt.org/t/mysterious-vlan-ids-on-mt7621-device/64495
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Enable testing kernel.
Fix compile errors by using new kernel APIs.
Fix fuzz by manually editing patches to ensure the code goes in the
right place.
For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit
a307593a6 to keep the OpenWrt ralink driver operational.
Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693
and #3952.
Run automatic quilt refresh on the rest.
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
This reverts commit b4aad29a1d.
This was accidentally folded into a single commit. Remove it and
apply it properly again.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Enable testing kernel.
Delete upstreamed patches:
0098-disable_cm.patch can be dropped, upstream fixed CM handling.
Fix compile errors by using new kernel APIs.
Fix fuzz by manually editing patches to ensure the code goes in the
right place.
For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit
a307593a6 to keep the OpenWrt ralink driver operational.
Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693
and #3952.
Rename patches to follow the 3-digit classification from the OpenWrt
Developer Guide.
Run automatic quilt refresh.
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
The ramips target only supports 5.4, so drop all kernel version
switches for older kernels there.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
While commit 734a8c46e7 focussed on removing stuff directly
selected by the NET_RALINK_* symbols, this patch removes additional
unused mt7621-specific code from the ethernet driver.
As with the previous patch, the main reason is to reduce the amount
of code we have to maintain and care about.
Note that this patch still keeps a few lines with
IS_ENABLED(CONFIG_SOC_MT7621) in mtk_eth_soc.h/.c, as this file is
still selected for the mt7621 subtarget.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
The mt7621 subtarget has been switched to DSA quite a while ago and
seems to run sufficiently fine. Build with older kernels than 5.4 has
been disabled directly during the kernel bump, so our local ethernet
driver is unused in master since then.
Therefore, let's remove the mt7621-specific parts of "our" ethernet
driver, so we don't have to maintain them and it's obvious to
everybody that they are not used anymore.
This also drops the offloading components as this was specifically
implemented to depend on mt7621.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
of_get_mac_address can return ERR_PTR since 5.2, so the return pointer should be
checked before used. Otherwise it might cause an oops during boot.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
The default switch frame size (with FCS + header) is 1536 bytes. But the
GMAC only accepted frames up to 1522 bytes. Setting it to 1536 allows to
receive ethernet frames using the full of MTU 1500 + an extra VLAN header +
VLAN header added by the switch.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 47117
The driver assumes that the maximum received buffer for non-jumbo frames is
1536 bytes. But the allocation of the rx fragment doesn't reflect that. It
currently allocates fragments which will only be large enough to be used as
rx buffer with the size of 1534 bytes. This is problematic because the GMAC
will now try to write to 2 bytes which don't belong to its receive buffer
when a large enough ethernet frame is received.
This may already be a problem on existing chips but will at least become a
problem when the 1536 byte rx modus is enabled on MT7621a. It is required
on this SoC to receive ethernet frames which use their full 1500 bytes MTU
and a VLAN header next to the switch VLAN tag.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 47116
The length of the DMA rx buffer was always set to 0 because the function
for extracting the length was used to calculate the value for setting it.
Instead the macro has to be split in a get and set function similar to the
TX_DMA_(GET_|)PLEN(0|1) macro.
No problem was noticed on MT7621a before this was changed and thus maybe it
was hidden by different problem which is not yet fixed.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 47115
The MT7530 switch driver with enable_vlan set will automatically set all
ports to the user port mode. The hardware will remove the incoming vlan tag
on these ports and use it for its internal vlan. This is usually not wanted
and makes it impossible to communicate via vlan over the switch in both
directions.
It is possible to configure a switch port to "transparent mode" when this
port is only used as untag in the switch VLANs. This will disable the VLAN
untagging of packets when they were received on this port. The tagging on
"tag" ports based on the vlan id is still working.
The transparent port mode cannot be used when a port is both used in a VLAN
as "tag" and in another one as "untag" port.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 47114
if there is any new tx need to clean up. do it in next napi poll.
collect tx related members to fe_tx_ring struct. for better
cache usage and more readable.
Signed-off-by: michael lee <igvtee@gmail.com>
SVN-Revision: 45895
when open device. first ready napi software rx.
then enable hardware interrupt.
final start software tx queue to send data.
Signed-off-by: michael lee <igvtee@gmail.com>
SVN-Revision: 45894
