Xianjun Jiao
54c67c7a2f
No need to consider 4 last pkt from 4 queue in master branch:
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Always assume Linux schedule 4 priority queue to 4 FPGA queue via 1 on 1 mapping
2022-03-28 20:41:00 +02:00
Xianjun Jiao
0cbb687387
Change the default bb_gain from 290 to 250 in tx_intf:
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- 2022-03-04 detailed test result:
- - bb_gain 290 work for 11a/g all mcs
- - bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr)
- - bb_gain 290 destroy 11n mcs 0 long (MTU 1500) tx pkt due to high PAPR (Peak to Average Power Ratio)
- - bb_gain 250 work for 11n mcs 0
So, a conservative bb_gain 250 should be used
2022-03-28 20:38:25 +02:00
Xianjun Jiao
469b96d342
Remove/modify the tx_intf register API according to the new FPGA:
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1. mixer/duc is not needed because we will not use offset tuning after the ad9361 tx lo control via FPGA is supported.
2. source selection register is not needed as well.
3. arbitrary IQ register is added.
2022-03-28 20:35:17 +02:00
mmehari
0c0d5d827e
use FPGA fifo count registers instead of software queue_cnt
2022-01-06 15:07:50 +01:00
mmehari
2d12c07d4d
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type
2022-01-06 14:43:32 +01:00
mmehari
f738aefa50
A-MPDU tx aggregation support
2022-01-06 14:42:01 +01:00
Xianjun Jiao
d14d06e508
CSI fuzzer feature -- document to be finished
2021-05-13 17:45:39 +02:00
Xianjun Jiao
95d3c7c5f3
remove all the compiling warnings when build 32bit driver
2021-04-05 21:42:46 +02:00
Jiao Xianjun
55c2866f7c
Merge pull request #54 from lnceballosz/master
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NGI0 - Updating licensing aspects according REUSE
2021-02-03 16:14:49 +01:00
Jiao Xianjun
c4306a8baf
Update tx_intf.c
2021-02-03 15:42:49 +01:00
Lina Ceballos
a6085186d9
adding license and copyright headers
2021-01-20 13:30:12 +01:00
mmehari
6e3730c0c1
Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information
2020-12-29 21:33:36 +01:00
Xianjun Jiao
22dd0cc486
the side channel (timestamp, frequency offset, CSI, equalizer) feature
2020-10-08 15:07:57 +02:00
Xianjun Jiao
838a9007cf
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
2020-06-12 10:50:34 +02:00
Xianjun Jiao
febc5adf73
prepare upgrade
2020-04-27 09:37:04 +02:00
Xianjun Jiao
b73660ad79
prepare for release
2020-03-04 19:39:12 +01:00
Xianjun Jiao
2ee6717882
initial commit
2019-12-10 14:03:47 +01:00
